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MAX6900ETT-T
I2C-Compatible RTC in a TDFN
General DescriptionThe MAX6900, I2C™-bus-compatible real-time clock
(RTC) in a 6-pin TDFN package contains a real-time
clock/calendar and 31-byte ✕8-bit wide of static ran-
dom access memory (SRAM). The real-time clock/cal-
endar provides seconds, minutes, hours, day, date,
month, and year information. The end of the month date
is automatically adjusted for months with fewer than 31
days, including corrections for leap year up to the year
2100. The clock operates in either the 24hr or 12hr for-
mat with an AM/PM indicator.
ApplicationsPortable Instruments
Point-of-Sale Equipment
Intelligent Instruments
Battery-Powered Products
FeaturesReal-Time Clock Counts Seconds, Minutes,
Hours, Date, Month, Day, and Year Leap Year Compensation Valid up to Year 2100Fast (400kHz) I2C-Bus-Compatible Interface from
2.0V to 5.5V31 ✕8 SRAM for Scratchpad Data StorageUses Standard 32.768kHz, 12.5pF Load, Watch
CrystalUltra-Low 225nA (typ) Timekeeping CurrentSingle-Byte or Multiple-Byte (Burst Mode) Data
Transfer for Read or Write of Clock Registers or
SRAM6-Pin 3mm x 3mm x 0.8mm TDFN Surface-Mount
PackageNo External Crystal Bias Resistors or Capacitors
Required
MAX69002C-Compatible RTC in a TDFN19-1942; Rev 3; 6/03
ypical Operating Circuit
Pin Configuration
Ordering Information
Related Real-Time Clock ProductsI2C is a trademark of Philips Corp. Purchase of I2C components
of Maxim Integrated Products, Inc., or one of its sublicensed
Associated Companies, conveys a license under the Philips I2C
Patent Rights to use these components in an I2C system, provid-
ed that the system conforms to the I2C Standard Specification
as defined by Philips.
MAX69002C-Compatible RTC in a TDFN
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND..............................................................-0.3V to +6V
All Other Pins to GND ................................-0.3V to (VCC+ 0.3V)
Input Current
All Pins ............................................................................20mA
Output Current
All Outputs.......................................................................20mA
Rate of Rise, VCC............................................................100V/µs
Continuous Power Dissipation (TA= +70°C)
6-Pin TDFN (derate 24.4mW/°C above +70°C).......1951.0mW
Operating Temperature Range...............................TMINto TMAX
MAX6900 ETT-T .......................TMIN= -40°C, TMAX= +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range............................-65°C to +150°C
ESD Protection (all pins, Human Body model)..................2000V
Lead Temperature (soldering, 10s)...…………………….+300°C
DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
MAX69002C-Compatible RTC in a TDFN
AC ELECTRICAL CHARACTERISTICS (continued)(VCC= +2.0V to +5.5V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.) (Notes 1, 6)
Note 1:All parameters are 100% tested at TA= +25°C. Limits over temperature are guaranteed by design and not production tested.
Note 2:ICCis specified with SCL = 400kHz and SDA = 400kHz.
Note 3:ITKis specified with SCL = Logic High (4.7kΩpullup resistor) and SDA = Logic High (4.7kΩpullup resistor); 2C-compatible bus inactive.
Note 4:MAX6900 I/O pins do not obstruct the SDA and SCL lines if VCCis switched off.
Note 5:Guaranteed by design. Not subject to production testing.
Note 6:All values referred to VIHminand VILmaxlevels.
Note 7:The MAX6900 internally provides a hold time of at least 300ns for the SDA signal (referred to the VIHminof the SCL signal)
in order to bridge the undefined region of the falling edge of SCL.
Note 8:CB= total capacitance of one bus line in pF.
Note 9:The maximum tffor the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tfis
specified at 250ns. This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL
bus lines without exceeding the maximum specified tf.
Detailed Description 2C-2C-bus-compatible timing
Real-Time Clock
MAX69002C-Compatible RTC in a TDFN
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
days, including corrections for leap year up to the year
Crystal Oscillator
The MAX6900 uses an external, standard 12.5pF load
watch crystal. No other external components are
required for this timekeeping oscillator. Power-up oscil-
lator start-time is dependent mainly upon applied VCC
and ambient temperature. The MAX6900, because of
its low timekeeping current, exhibits a typical startup
time between 5s to 10s.
2C-Compatible InterfaceInterfacing the MAX6900 with a microprocessor or
other I2C master is made easier by using the serial, I2C-
bus-compatible or other I2C master interface. Only 2
wires are required to communicate with the clock and
SRAM: SCL (serial clock) and SDA (data line). Data is
transferred to and from the MAX6900 over the I/O data
line, SDA. The MAX6900 uses 7-bit slave ID address-
ing. The MAX6900 does not respond to general call
address commands.
Applications Information2C-Bus-Compatible InterfaceThe I2C-bus-compatible serial interface allows bidirec-
tional, 2-wire communication between multiple ICs. The
two lines are SDA and SCL. Connect both lines to a
positive supply through individual pullup resistors. A
device on the I2C-compatible bus that generates a
message is called a transmitter and a device that
receives the message is a receiver. The device that
controls the message is the master and the devices
that are controlled by the master are called slaves
(Figure 3). The word message refers to data in the form
of three 8-bit bytes for a Single Read or Write. The first
byte is the Slave ID byte, the second byte is the
Address/Command byte, and the third is the data.
Data transfer can only be initiated when the bus is not
busy (both SDA and SCL are high). A high-to-low tran-
sition of SDA while SCL is high is defined as the Start
(S) condition; low-to-high transition of the data line
while SCL is high is defined as the Stop (P) condition
(Figure 4).
MAX69002C-Compatible RTC in a TDFNFigure 2. Functional Diagram
MAX69002C-Compatible RTC in a TDFNAfter the Start condition occurs, 1 bit of data is trans-
ferred for each clock pulse. The data on SDA must
remain stable during the high portion of the clock pulse
as changes in data during this time are interpreted as a
control signal (Figure 5). Any time a start condition
occurs, the Slave ID must follow immediately, regard-
less of completion of the previous data transfer.
Before any data is transmitted on the I2C-bus-compati-
ble serial interface, the device that is expected to
respond is addressed first. The first byte sent after the
start (S) procedure is the Address byte or 7-bit Slave
ID. The MAX6900 acts as a slave transmitter/receiver.
Therefore, SCL is only an input clock signal and SDA is
a bidirectional data line. The Slave Address for the
MAX6900 is shown in Figure 6.
Figure 3. I2C Bus System Configuration
Figure 4. I2C Bus Start and Stop Conditions
MAX69002C-Compatible RTC in a TDFNAn unlimited number of data bytes between the start
and stop conditions can be sent between the transmit-
ter and receiver. Each 8-bit byte is followed by an
acknowledge bit. Also, a master receiver must gener-
ate an acknowledge after each byte it receives that has
been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse (Figure 7), so
that the SDA line is stable low during the high period of
the acknowledge clock pulse (setup and hold times
must also be met). A master receiver must signal an
end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked
out of the slave. In this case, the transmitter must leave
SDA high to enable the master to generate a stop con-
dition. Any time a stop condition is received before the
current byte of data transfer is complete, the last incom-
plete byte is ignored.
The second byte of data sent after the start condition is
the Address/Command byte (Figure 8). Each data
transfer is initiated by an Address/Command byte. The
MSB (bit 7) must be a logic 1. When the MSB is zero,
Writes to the MAX6900 are disabled. Bit 6 specifies
clock/calendar data if logic 0 or RAM data if logic 1
(Tables 1 and 2). Bits 1 through 5 specify the designat-
ed registers to be input or output. The LSB (bit 0) spec-
ifies a Write operation (input) if logic 0 or Read
operation (output) if logic 1. The Command byte is
always input starting with the MSB (bit 7).
Reading from the Timekeeping
RegistersThe timekeeping registers (Seconds, Minutes, Hours,
Date, Month, Day, Year, and Century) read either with a
Single Read or a Burst Read. Since the clock runs con-
tinuously and a Read takes a finite amount of time, it is
possible that the clock counters could change during a
Read operation, thereby reporting inaccurate timekeep-
ing data. In the MAX6900, the clock counter data is
buffered by a latch. Clock counter data is latched by the
I2C-bus-compatible read command (on the falling edge
of SCL when the Slave Acknowledge bit is sent after the
Address/Command byte has been sent by the master to
read a timekeeping register). Collision-detection circuitry
ensures that this does not happen coincident with a sec-
onds counter update to ensure accurate time data is
being read. This avoids time data changes during a
Read operation. The clock counters continue to count
and keep accurate time during the Read operation.
When using a Single Read to read each of the time-
keeping registers individually, perform error checking
MAX69002C-Compatible RTC in a TDFN
Table 1. Register Address Definition
MAX69002C-Compatible RTC in a TDFN
Table 1. Register Address Definition (continued)
Table 2. Hex Register Address Definition
Note: POR STATEdefines power-on reset state of register contents.
