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MAX6620ATI+T
Quad Linear Fan-Speed Controller
MAX6620
Quad Linear Fan-Speed Controller
EVALUATION KIT AVAILABLE
General Description
The MAX6620 controls the speeds of up to four fans
using four independent linear voltage outputs. The
drive voltages for the fans are controlled directly over
the I2C interface. Each output drives the base of an
external bipolar transistor or the gate of a FET in high-
side drive configuration. Voltage feedback at the fan’s
power-supply terminal is used to force the correct out-
put voltage.
The MAX6620 offers two methods for fan control. In
RPM mode, the MAX6620 monitors four fan tachometer
logic outputs for precise (±1%) control of fan RPM and
detection of fan failure. In DAC mode, each fan is dri-
ven with a voltage resolution of 9 bits and the tachome-
ter outputs of the fans are monitored for failure.
The DAC_START input selects the fan power-supply
voltage at startup to ensure appropriate fan drive when
power is first applied. A watchdog feature turns the
fans fully on to protect the system if there are no valid
I2C communications within a preset timeout period.
The MAX6620 operates from a 3.0V to 5.5V power sup-
ply with low 250µA supply current, and the I2C-compati-
ble interface makes it ideal for fan control in a wide
range of cooling applications. The MAX6620 is avail-
able in a 28-pin TQFN package and operates over the
-40°C to +125°C automotive temperature range.
Applications
Consumer Products
Servers
Communications Equipment
Storage Equipment
FeaturesControls Up to Four Independent Fans With
Linear (DC) DriveUses Four External Low-Cost Pass Transistors1% Accuracy Precision RPM ControlControlled Voltage Rate-Of-Change for Best
AcousticsI2C Bus Interface3.0V to 5.5V Supply Voltage Range250µA (typ) Operating Supply Current3µA (typ) Shutdown Supply CurrentSmall 5mm x 5mm Footprint
MAX6620
TQFN
TOP VIEW
SDA
GND
ADDR
DAC_START
SPINUP_START
SCL
DACFB2GNDDACOUT3TACH2DACFB3TACH3
GND672119171615
FAN
VCC
DACOUT4
GND
GND
WD_START
DACOUT28FAN_FAILX1
DACOUT113DACFB4DACFB114TACH4TACH1
Pin Configuration
Ordering Information
+Denotes a lead-free package.
*EP = Exposed paddle.
PARTTEMP RANGEPIN-PACKAGE
MAX6620ATI+-40°C to +125°C28 TQFN-EP*
Typical Application Circuit appears at end of data sheet.
MAX6620
Quad Linear Fan-Speed Controller
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(TA= -40°C to +125°C, VCC= 3.0V to 5.5V, unless otherwise noted. Typical values are at TA= +25°C, VCC= 3.3V.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND..........................................................-0.3V to +6.0V
FAN_FAIL, SDA, SCL to GND...............................-0.3V to +6.0V
ADDR, SPINUP_START, DAC_START, WD_START,
X1, X2 to GND........................................-0.3V to (VCC + 0.3V)
All Other Pins to GND..........................................-0.3V to +13.5V
Input Current at DACOUT_ Pins (Note 1)...............+5mA/-50mA
Input Current at Any Pin (Note 1)..........................................5mA
ESD Protection (all pins, Human Body Model) (Note 2)...±2000V
Continuous Power Dissipation (TA= +70°C)
28-Pin TQFN (derate 34.5mW/°C above +70°C)....2758.6mW
Operating Temperature Range.........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Soldering Temperature (reflow).......................................+260°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONMINTYPMAXUNITS
Operating Supply VoltageVCC3.05.5V
Operating Supply CurrentICCVCC = 5.5V0.250.60mA
I2C inactive0.20.5mAQuiescent Supply CurrentShutdown mode320µA
VFANHI101213.5VFAN Supply VoltageVFANLO4.05.05.5V
VGND + 10V < VDACOUT_ < 11.5V,
VFAN = 12V-18
DACOUT_ Output CurrentIDACOUT_VGND + 3V < VDACOUT_ < 10V,
VFAN = 12V-16
DACOUT_ Output VoltageVDACOUT_IDACOUT_ = 5mA0.05VFAN -
0.1V
VFAN = VFANHI256/535
VFAN = VFANLO256/567
VFAN = 12V5.545.745.94
DAC Feedback Voltage at Half
ScaleDACFBHS
At DACFB_,
code = 0x100,
IDACOUT_ = 5mA
VFAN = 5V2.052.252.45
VFAN = VFANHI511/535DACFBFSVFAN = VFANLO511/567
VFAN = 12V11.2511.4511.65
DAC Feedback Voltage at Full
Scale
VDACFB511
At DACFB_,
code = 0x1FF,
IDACOUT_ = 5mA
VFAN = 5V4.34.54.7
Drive Voltage Resolution9Bit
DACFB_ ImpedanceRDACFB1MΩ
TACH Minimum Input Pulse Width25µs
Internal Reference Frequency
Accuracy(Note 4)-3+3%
Using 32.768kHz crystal-0.1+0.1
Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifica-
tions do not apply when operating the device beyond its rated operating conditions.
Note 2:Human Body Model, 100pF discharged through a 1.5kΩresistor.
MAX6620
Quad Linear Fan-Speed Controller
ELECTRICAL CHARACTERISTICS (continued)
(TA= -40°C to +125°C, VCC= 3.0V to 5.5V, unless otherwise noted. Typical values are at TA= +25°C, VCC= 3.3V.) (Note 3)
PARAMETERSYMBOLCONDITIONMINTYPMAXUNITS
Using 32.768kHz crystal, test at 850RPM-1+1Fan Control Accuracy (Note 4)Using on-chip oscillator-3+3%
XTAL Oscillator Startup Time2s
X1 Input Threshold0.7V
VCC2POR ThresholdVFAN3.5V
LOGIC (SDA, SCL, FAN_FAIL, WD_START, TACH_)
Input High VoltageVIHVCC x
0.7V
Input Low VoltageVILVCC x
0.3V
Input High CurrentIIH1.0µA
Input Low CurrentIIL-1.0µA
Input CapacitanceAll digital inputs6pF
Output High Current100µA
Output Low VoltageIOL = 3mA0.4V
LOGIC (DAC_START, SPIN_START, ADDR)
Input High VoltageVIHVCC -
0.5V
Input Low VoltageVIL0.5V
Input High CurrentIIH1.0µA
Input Low CurrentIIL-1.0µA
Input CapacitanceAll digital inputs6pF2C-COMPATIBLE TIMING (Notes 5, 6)
Serial Clock FrequencyfSCL400kHz
Bus Free Time Between STOP
and START ConditionstBUF1.3µs
START Condition Hold TimetHD:STA0.6µs
STOP Condition Setup TimetSU:STO600ns
Clock Low PeriodtLOW1.3µs
Clock High PeriodtHIGH0.6µs
START Condition Setup TimetSU:STA600ns
Data Setup TimetSU:DAT100ns
Data Out Hold TimetDH100ns
Data In Hold TimetHD:DAT(Note 6)00.9µs
Maximum Receive SCL/SDA Rise
TimetR(Note 8)300ns
Minimum Receive SCL/SDA Rise
TimetR(Note 7)20 + 0.1
x CBns
MAX6620
Quad Linear Fan-Speed Controller
ELECTRICAL CHARACTERISTICS (continued)
(TA= -40°C to +125°C, VCC= 3.0V to 5.5V, unless otherwise noted. Typical values are at TA= +25°C, VCC= 3.3V.) (Note 3)
PARAMETERSYMBOLCONDITIONMINTYPMAXUNITS
Maximum Receive SCL/SDA Fall
TimetF300ns
Minimum Receive SCL/SDA Fall
TimetF(Note 7)20 + 0.1
x CBns
Transmit SDA Fall TimetF(Note 7)20 + 0.1
x CB250ns
Pulse Width of Suppressed SpiketSP(Note 8)050ns
Output Fall TimeCL = 400pF, IOUT = 3mA250ns
SDA Time Low for Reset of Serial
InterfacetTIMEOUT(Note 9)2050ms
Note 3:All parts will operate properly over the VCCsupply voltage range of 3.0V to 5.5V.
Note 4:Guaranteed by design and characterization.
Note 5:All timing specifications are guaranteed by design.
Note 6:A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling edge.
Note 7:CB= total capacitance of one bus line in pF. Tested with CB= 400pF.
Note 8:Input filters on SDA and SCL suppress noise spikes less than 50ns.
Note 9:Holding the SDA line low for a time greater than tTIMEOUTwill cause the devices to reset SDA to the idle state of the serial
bus communication (SDA set high).
tHD,STAtHIGHtF
tHD,STASrA
SCL
SDA
tSU,STAtSU,STOtF
tBUF
tLOW
tSU,DATtHD,DAT
Figure 1. I2C Serial Interface Timing
TACH COUNT ACCURACY WITH INT CLK
vs. SUPPLY VOLTAGE
MAX6620 toc01
SUPPLY VOLTAGE (V)
TACH COUNT ACCURACY WITH INT CLK (%)
VFAN = 12V
TA = 0°CTA = +25°C
TA = +125°CTA = +70°C
TACH COUNT ACCURACY WITH EXT CLK
vs. SUPPLY VOLTAGE
MAX6620 toc02
SUPPLY VOLTAGE (V)
TACH COUNT ACCURACY WITH EXT CLK (%)
VFAN = 12V
TA = 0°C, +70°C, +125°C
TA = +25°C
TACH COUNT ACCURACY WITH INT CLK
vs. TEMPERATURE
MAX6620 toc03
TEMPERATURE (°C)
TACH COUNT ACCURACY WITH INT CLK (%)35-10
VFAN = 12V
VCC = 5.0V
VCC = 3.3V
TACH COUNT ACCURACY WITH EXT CLK
vs. TEMPERATURE
MAX6620 toc04
TEMPERATURE (°C)
TACH COUNT ACCURACY WITH EXT CLK (%)35-10
VFAN = 12V
VCC = 3.3V, 5.0V
DACFB_ VOLTAGE ACCURACY
vs. TEMPERATURE
MAX6620 toc05
TEMPERATURE (°C)
DACFB VOLTAGE ACCURACY (%)35-10
VFAN = 12V
VCC = 3.0V, 3.3V, 5.0V
DACFB_ VOLTAGE ACCURACY
vs. SUPPLY VOLTAGE
MAX6620 toc06
SUPPLY VOLTAGE (V)
DACFB VOLTAGE ACCURACY (%)
VFAN = 12V
DACFB_ VOLTAGE ACCURACY
vs. OUTPUT CURRENT
MAX6620 toc07
DACFB VOLTAGE ACCURACY (%)
VFAN = 12V
VCC = 3.0V, 3.3V
VCC = 5.5V
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX6620 toc08
STANDBY SUPPLY CURRENT (
VFAN = 12V
INT CLK
EXT CLK
OPERATING SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX6620 toc09
OPERATING SUPPLY CURRENT (mA)
VFAN = 12V
INT CLK
EXT CLK
Typical Operating Characteristics
(VCC= 3.3V, VFAN= 12V, TA= +25°C, unless otherwise noted.)
MAX6620
Quad Linear Fan-Speed Controller
MAX6620
Quad Linear Fan-Speed Controller
TACH COUNT ACCURACY WITH INT CLK
vs. SUPPLY VOLTAGE
MAX6620 toc10
SUPPLY VOLTAGE (V)
TACH COUNT ACCURACY WITH INT CLK (%)
VFAN = 5.0V
TA = 0°CTA = +25°C
TA = +125°CTA = +70°C
TACH COUNT ACCURACY WITH EXT CLK
vs. SUPPLY VOLTAGE
MAX6620 toc11
SUPPLY VOLTAGE (V)
TACH COUNT ACCURACY WITH EXT CLK (%)
VFAN = 5.0V
TA = 0°C, +70°C, +125°C
TA = +25°C
TACH COUNT ACCURACY WITH INT CLK
vs. TEMPERATURE
MAX6620 toc12
TEMPERATURE (°C)
TACH COUNT ACCURACY WITH INT CLK (%)35-10
VFAN = 5.0V
VCC = 3.3V
VCC = 5.0V
TACH COUNT ACCURACY WITH EXT CLK
vs. TEMPERATURE
MAX6620 toc13
TEMPERATURE (°C)
TACH COUNT ACCURACY WITH EXT CLK (%)35-10
VFAN = 5.0V
VCC = 3.3V, 5.0V
DACFB_ VOLTAGE ACCURACY
vs. TEMPERATURE
MAX6620 toc14
TEMPERATURE (°C)
DACFB VOLTAGE ACCURACY (%)35-10
VFAN = 5.0V
VCC = 3.0V
VCC = 3.3VVCC = 5.5V
DACFB_ VOLTAGE ACCURACY
vs. SUPPLY VOLTAGE
MAX6620 toc15
SUPPLY VOLTAGE (V)
DACFB VOLTAGE ACCURACY (%)
VFAN = 5.0V
DACFB_ VOLTAGE ACCURACY
vs. OUTPUT CURRENT
MAX6620 toc16
DACFB VOLTAGE ACCURACY (%)
VFAN = 5.0V
VCC = 3.0V, 3.3V
VCC = 5.5V
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX6620 toc17
STANDBY SUPPLY CURRENT (
VFAN = 5.0V
INT CLK
EXT CLK
OPERATING SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX6620 toc18
OPERATING SUPPLY CURRENT (mA)
VFAN = 5.0V
INT CLK
EXT CLK
Typical Operating Characteristics (continued)
(VCC= 3.3V, VFAN= 12V, TA= +25°C, unless otherwise noted.)
Pin Description
PINNAMEFUNCTIONSCLI2C Serial-Clock Input. Can be pulled up to 5.5V regardless of VCC. Open circuit when VCC = 0V.SDAOpen-Drain, I2C Serial-Data Input/Output. Can be pulled up to 5.5V regardless of VCC. Open
circuit when VCC = 0V.WD_START
Startup Watchdog Set Input. This input is sampled when power is first applied and sets the initial2C watchdog behavior. When connected to GND, the watchdog function is disabled. When
connected to VCC, the MAX6620 monitors SDA. If 10s elapse without a valid I2C transaction, the
fan drive goes to 100%.
4, 10, 11, 18,GNDGroundADDR2C Address Set Input. This input is sampled when power is first applied and sets the I2C slave
address. When connected to GND, the slave address will be 0x50. When unconnected, the slave
address will be 0x52. When connected to VCC, the slave address will be 0x54.DAC_START
Startup Fan Drive DAC Set Input. This input is sampled when power is first applied and sets the
power-up value for the fan drive voltage. When connected to GND, the fan drive voltage will be
0%. When unconnected, the fan drive voltage will be 75%. When connected to VCC, the fan drive
voltage will be 100%.
7S P IN U P _S TART
Startup Spin-Up Set Input. This input is sampled when power is first applied and sets the initial
spin-up behavior. When connected to GND, spin-up is disabled. When connected to VCC at
power-up, the fan is driven with a full-scale drive voltage until two tachometer pulses have been
detected, or 1s has elapsed. When unconnected, the fan is driven with a full-scale drive voltage
until two tachometer pulses have been detected, or 0.5s has elapsed. Spin-up behavior may be
modified by writing appropriate settings to the MAX6620’s registers.
8, 9X1, X2
Crystal Oscillator Inputs. Connections for a standard 32.768kHz quartz crystal. The internal
oscillator circuitry is designed for operation with a crystal having a specified load capacitance
(CL) of 12pF. Connect an external 32.768kHz oscillator across X1 and X2 for operation with the
external oscillator. If no crystal or external oscillator is connected, the MAX6620 will use its
internal oscillator.
12, 17, 19, 24DACOUT4–
DACOUT1
Fan Drive DAC Outputs. Connect to the gate of a p-channel MOSFET or base of a PNP bipolar
transistor.
13, 16, 20, 23DACFB4–
DACFB1AC Feed b ack Inp uts. C onnect a 0.1µF cap aci tor b etw een these p i ns and GN D . C onnect to the
sup p l y p i n of the fan and to the d r ai n of a p - channel M O S FE T or col l ector of a P N P b i p ol ar tr ansi stor .
14, 15, 21, 22TACH4–TACH1Fan Tachometer Logic Inputs. These inputs accept input voltages up to VFAN.FANFan Power-Supply Voltage Input. Connect to the fan power supply (VFAN). Bypass with a 0.1µF
capacitor to GND.VCCPower-Supply Input. 3.3V nominal. Bypass VCC to GND with a 0.1µF capacitor.FAN_FAILActive-Low, Open-Drain Fan Failure Output. Active only when fault is present; open-circuit when
VCC = 0V. This pin can be pulled up to 5.5V regardless of VCC.
—EPExposed Paddle. Internally connected to GND. Connect to a large ground plane to maximize
thermal performance. Not intended as an electrical connection point.
MAX6620
Quad Linear Fan-Speed Controller
MAX6620
Quad Linear Fan-Speed Controller
Write Byte Format
Read Byte Format
Send Byte FormatReceive Byte Format
Slave Address: equiva-
lent to chip-select line of
a 3-wire interface
Command Byte: selects which
register you are writing to
Data Byte: data goes into the register
set by the command byte (to set
thresholds, configuration masks, and
sampling rate)
Slave Address: equiva-
lent to chip-select line
Command Byte: selects
which register you are
reading from
Slave Address: repeated
due to change in data-
flow direction
Data Byte: reads from
the register set by the
command byte
Command Byte: sends com-
mand with no data, usually
used for one-shot command
Data Byte: reads data from
the register commanded
by the last read byte or
write byte transmission;
also used for SMBus alert
response return address
S = START CONDITIONSHADED = SLAVE TRANSMISSION
P = STOP CONDITIONA= NOT ACKNOWLEDGED
Figure 2. I2C ProtocolsADDRESSRDADATAAP
7 bits8 bitsSACOMMANDAP
8 bits
ADDRESS
7 bitsDATA
8 bitsCOMMAND
8 bitsWRADDRESS
7 bitsADDRESSWRACOMMANDASADDRESS
7 bits8 bits7 bitsADATA
8 bitsP
Detailed Description
The MAX6620 controls the speeds of up to four fans
using four independent linear voltage outputs. The
drive voltages for the fans are controlled directly over
the I2C interface. Each of the outputs (DACOUT1–
DACOUT4) drive the base of an external PNP or the
gate of a p-channel MOSFET. Voltage feedback at the
fan’s power-supply terminal is used to force the output
voltage.
The MAX6620 monitors fan tachometer logic outputs for
precise (1%) control of fan RPM and detection of fan
failure. When the MAX6620 is used with 2-wire fans,
these inputs are not used, and the fans can be driven
to the desired voltage without using tachometer feed-
back.
Three inputs set the fan drive status on application of
power. The DAC_START input selects the fan-supply
voltage (100%, 75%, or 0%) at startup to ensure appro-
priate fan drive when power is first applied. The
SPIN_START input selects whether spin-up will be
applied to the fans at power-up. WD_START selects
whether lack of I2C activity will force the fans to full
speed. When the watchdog function is enabled, the
fans will be driven to full speed if there is no I2C activity
for a period of 2s, 6s, or 10s.
Digital Interface
The MAX6620 features an I2C-compatible, 2-wire serial
interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate bidirectional communication between the MAX6620
and the master at rates up to 400kHz. The master (typi-
cally a microcontroller) initiates data transfer on the bus
and generates SCL. SDA and SCL require 4.7kΩ(typ)
pullup resistors.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data into or out of the MAX6620. The data on SDA must
remain stable during the high period of the SCL clock
pulse, as changes in SDA while SCL is high are control
signals (see the START and STOP Conditionssection).
Both SDA and SCL idle high.
MAX6620
Quad Linear Fan-Speed Controller
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP condi-
tion (P), a low-to-high transition on SDA while SCL is high
(Figure 3). The STOP condition frees the bus and places
all devices in F/S mode (Figure 1). Use a repeated
START condition (Sr) in place of a STOP condition to
leave the bus active and in its current timing mode.
Acknowledge Bits
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX6620 (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (9th pulse), and keep it
low during the high period of the clock pulse (Figure 4).
To generate a not acknowledge, the receiver allows
SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse, and leaves it high
during the high period of the clock pulse. Monitoring
the acknowledge bits allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
happens if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the master should reattempt communication at
a later time.
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = MASTER PULLS DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
SCLCDEFGHIJK
SDA
tSU:STAtHD:STA
tLOWtHIGH
tSU:DATtHD:DATtSU:STOtBUFM
Figure 3. I2C Write Timing Diagram
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
I = MASTER PULLS DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
SCLCDEFGHIJ
SDA
tSU:STAtHD:STA
tLOWtHIGH
tSU:DATtSU:STOtBUFK
Figure 4. I2C Read Timing Diagram
MAX6620
Quad Linear Fan-Speed Controller
Slave Address
A master initiates communication with a slave device by
issuing a START condition followed by a slave address
byte. As shown in Figure 5, the slave address byte con-
sists of 7 address bits and a read/write bit (R/W). When
idle, the MAX6620 continuously waits for a START con-
dition followed by its slave address. The first four bits
(MSBs) of the slave address have been factory pro-
grammed and are always 0101and the seventh bit is 0.
Connect ADDR to GND or VCC, or leave it unconnected
to program D2 and D1 of the slave address according
to Table 1.
After receiving the address, the MAX6620 (slave)
issues an acknowledgement by pulling SDA low for one
clock cycle.
Data Byte (Read and Write)
Single Read and Burst Read. A single read begins
with the bus master issuing a START condition followed
by the seven slave ID address bits and a zero (WR,
Figure 2), which is followed by an acknowledge bit (A)
from the slave corresponding to the slave ID. Next, the
master sends out an 8-bit register address, which is
also followed by an acknowledge bit from the slave.
The bus master issues another START condition and
the same seven slave ID address bits followed by a one
(RD, Figure 2), with the slave producing an acknowl-
edge bit. The slave then sends out the 8-bit data corre-
sponding to the register address previously written by
the master. The bus master sends back a not-acknowl-
edge bit (A). This completes the single read process
and a STOP condition is issued by the bus master.
In a burst read, the process is the same as a single
read except that the bus master issues an acknowl-
edge bit after each byte transmitted by the slave. After
each acknowledge bit, the register address increments
by one, and the data from the next register is transmit-
ted by the slave. The process continues, with data
reads followed by acknowledges. After the register with
the highest address is read, the register pointer rolls
over to point to the first register. To terminate a burst
read, the bus master issues a STOP condition.
Single Write and Burst Write.A single write begins
with the bus master issuing a START condition followed
by the seven slave ID address bits and a zero (WR,
Figure 2), which is followed by an acknowledge bit (A)
from the slave corresponding to the slave ID. Next, the
master sends out an 8-bit register address, which is
also followed by an acknowledge bit from the slave.
After the acknowledge bit, 8-bit data is written to the
register, and the slave issues a third acknowledgement.
A STOP condition is issued by the bus master to com-
plete the single write process.
In a burst write, the process is similar to a single write
except that the master does not issue a STOP condition
immediately after the first byte has been written. After
the first write is completed, the slave issues an
acknowledge bit, the register address increments by
one, and the data to be written to the next register is
transmitted by the master. The process continues, with
data writes followed by acknowledges. After the regis-
ter with the highest available address is written, the reg-
ister pointer rolls over to point to the first register. To
terminate a burst write, the bus master issues a STOP
condition.
Fan Drive
The MAX6620 uses external pass transistors to power
the fans. DACOUT1–DACOUT4 adjust the power-
supply voltage for each fan by driving the base of a
PNP bipolar transistor, or the gate of a p-MOSFET. The
resulting fan-supply voltage is fed back to DACFB_.
This closes the voltage feedback loop. The system
power supply for the output devices is VFAN. VFANis
SLAVE ADDRESSADDR CONNECTIONHEXBINARY
GND0x500101 000
Unconnected0x520101 010
VCC0x540101 100
Table 1. Slave Address Setting with
ADDR Pin
SDA
SCL01
1234D10R/W
ACKNOWLEDGE
MAX6620
Quad Linear Fan-Speed Controller
BIT 7…………….……………… BIT 0 ACK BIT BIT 7…………….…………………BIT ACK BIT
8-BIT DATA
8-BIT REGISTER ADDRESS
8-BIT REGISTER ADDRESS
8-BIT REGISTER ADDRESS
BIT 7…….…….…………BIT 0 ACK BIT
7-BIT SLAVE ID
SINGLE WRITESINGLE READBURST WRITEBURST READ
BIT 7…………….……….BIT 0 ACK BIT
BIT 7………….…………BIT 0
ACK BIT
BIT 7…………….……………BIT 0 ACK BIT
8-BIT DATA
BIT 7…….…………BIT 0 ACK BIT
7-BIT SLAVE ID
7-BIT SLAVE ID
FIRST 8-BIT DATA
8-BIT REGISTER ADDRESS
BIT 7…………….…………BIT 0 ACK BIT
BIT 7…………….…………BIT 0 ACK BIT
BIT 7…………….………BIT 0 ACK BIT BIT 7…………….……………BIT 0 ACK BIT
7-BIT SLAVE ID
LAST 8-BIT DATA
BIT 7……….……………BIT 0 ACK BIT
BIT 7……….…………………BIT 0 ACK BIT
LAST 8-BIT DATA
BIT 7…………….………… BIT 0 ACK BIT
7-BIT SLAVE ID
7-BIT SLAVE ID
FIRST 8-BIT DATA
BIT 7…………….…………… BIT 0 ACK BIT
S: 2-WIRE BUS START CONDITION BY MASTERP: 2-WIRE BUS STOP CONDITION BY MASTERAS: ACKNOWLEDGE BY SLAVEAM: ACKNOWLEDGE BY MASTERAM: NO ACKNOWLEDGE BY MASTER
Figure 6. Read and Write Summary
MAX6620
Quad Linear Fan-Speed Controller
nominally 12V or 5V. The drive to the fans is proportion-
al to VFAN. See the Fan_ Target Drive Voltage Registers
and the Applications Informationsections for more
details.
Fan-Speed Control
DAC (Voltage) Mode. In DAC mode, the MAX6620 sim-
ply sets the voltage that powers the fan. The fan’s
speed is related, but not precisely proportional to, the
drive voltage. The drive voltage is set by the Fan_
Target Drive Voltage registers and may be read from
the Fan_ Drive Voltage registers. Because the output
voltage can ramp to new values at a controlled rate, the
values in the two registers may be different. See the
Register Descriptionsand Applications Informationsec-
tions for details.
RPM Mode. In RPM mode, the MAX6620 monitors
tachometer output pulses from the fan and adjusts the
fan drive voltage to force the fan’s speed to the desired
value. Fan speed is measured by counting the number
of internal 8192Hz clock cycles that take place during a
selectable number of tachometer periods. The number
of clock cycles counted (11-bit value) is stored in the
Fan_ TACH Count registers, and the desired number of
cycles is stored in the Fan_ Target TACH Count regis-
ters. See the Register Descriptionsand Applications
Informationsections for details.
Rate-of-Change Control. Sudden changes in fan
speed can be easily heard by users. The MAX6620
helps reduce the audibility of fan-speed changes by
controlling the rate at which the drive to the fan is incre-
mented. Four bits in the Fan_ Dynamics registers set
the rate at which the fan drive voltage is incremented.
This allows the time required for a change in fan speed
to be varied from 0 (in DAC mode only) to several min-
utes. See the Register Descriptionsand Applications
Informationsections for details.
Monitoring Tachometer Signals.The TACH_ inputs
accept tachometer or “locked-rotor” output signals from
3- or 4-wire fans. When measuring fan speed, the
MAX6620 counts the number of internal 8192Hz clock
cycles that occur during 1, 2, 4, 8, 16, or 32 tachometer
periods. The number of tachometer periods is selec-
table for each fan by using the appropriate Fan_
Dynamics register. Tachometer pulses <25µs in dura-
tion are ignored to minimize the effect of noise on the
tachometer lines.
The TACH count for a given RPM can be obtained from
the following equation:
where:
NP = number of tachometer pulses per revolution. Most
general-purpose brushless DC fans produce two
tachometer pulses per revolution.
SR = 1, 2, 4, 8, 16, or 32. See the Fan_ Speed Range
information in the Fan_ Dynamics Registers(06h, 07h,
08h, 09h)—POR = 0100 1100section.
The tachometer count consists of 11 bits in the Fan_
TACH Count registers and is available in RPM and DAC
modes. In RPM mode, the desired fan count is written
to the Fan_ Target TACH Count registers.
Fan Failure Detection
When enabled, the MAX6620 monitors the TACH_
inputs to determine when a fan has failed. For fans with
tachometer outputs, failure is detected in various ways
depending on the fan control mode. In every case, four
consecutive fault detections are required to decide
whether the fan has failed. In DAC mode, the Fan_
Target TACH Count registers hold the upper limit for
tachometer count values; a fault condition is identified
when a TACH count exceeds the value written to the
Fan_ Target TACH Count registers for more than 1s. In
RPM mode, a fault condition is identified when any of
the following three conditions occur for more than 1s: 1)
the TACH count exceeds the value of the Fan_ Target
TACH Count registers while the fan drive voltage is at
full-scale, 2) the TACH count exceeds two times the
Fan_ Target TACH Count value, or 3) the TACH count
reaches its full count of 7FFh.
Some fans have locked rotor outputs that produce a
logic-level output to indicate that the fan has stopped
spinning. These signals can be monitored by setting
D2:D1 in the Fan_ Configuration registers. D2 selects
locked rotor or tachometer monitoring and D1 selects the
polarity of the locked rotor signal. A fan fault has occurred
when a locked rotor signal has been present for 1s.
Fan failure is indicated in the Fan Fault register and
also with the open-drain FAN_FAILoutput. The
FAN_FAILoutput may be masked using the mask bits
in the Fan Fault register. When a fan failure is detected,
drive to the affected fan is removed. Drive may be
restored by writing a new DAC or fan count target to the
fan’s control registers. The global configuration regis-
TACHcountRPM
NP RPM NP SR =×××=×8192491520
MAX6620
Quad Linear Fan-Speed Controller
ter’s bit D4 can be used to cause a fan failure to force
the remaining fan speeds to 100%.
Watchdog
The MAX6620 includes an optional I2C watchdog func-
tion that monitors the I2C bus for transactions. When the
watchdog function is enabled, all fans will be forced to
full speed if no I2C transactions occur within a selected
period (2s, 6s, or 10s).
Spin-Up
When a fan is not spinning, and a voltage less than the
nominal fan-supply voltage is applied to its power-
supply terminals, it may fail to start spinning. To over-
come this, the full nominal supply voltage may be
applied to the fan terminals for a short time before a
lower voltage is applied. This “spin-up” period allows
the fan to overcome inertia and begin operating. Spin-
up is controlled using the Fan_ Configuration registers.
Spin-up can be disabled, or it can cause the fan to be
driven with the full supply voltage until it produces two
tachometer pulses, up to a maximum of 0.5s, 1s, or 2s
when the fan is started.
POR Options
Three inputs allow set up of the MAX6620’s behavior at
power-up. These inputs are sampled when power is
first applied to the MAX6620:WD_START.Connect WD_START to VCCto enable,
or to ground to disable, the watchdog function. When
enabled using WD_START, the timeout period is 10s.
After power is applied, the watchdog function may be
enabled or disabled through the global configuration
register.SPINUP_START.At power-up, spin-up operation is
controlled by the SPINUP_START pin, which can be
connected to ground (spin-up disabled), VCC(spin-
up for a maximum of 1s), or unconnected (spin-up for
a maximum of 0.5s).DAC_START.This input controls the fan drive volt-
age (for all four fans) at power-up. When connected
to ground, the initial fan drive voltage will be 0V.
When connected to VCC, the initial fan drive voltage
will be full scale. When unconnected, the initial fan
drive voltage will be 75% of VFAN.
MAX6620
Quad Linear Fan-Speed Controller
IST
ER
./A
ESS
R
A
N D
7 D
6 D
5 D
4 D
3 D
2 D
1 D
0
00h
X
Gl
al
g
at
i on
0 =
r un
1 =
tan
0 =
nor
m
1 =
r
meout
(35ms
0 = ena
led
di
Fans
to
100%
on
ilu
0 = ena
led
di
C
0 =
i
nter
nal
1 =
X
W
atchd
og
00 =
N
o w
atchd
og
01 =
2s
10 =
6s
11 =
10s
chd
og
tus
r ea
onl
y)
1 =
ap
se
01h
0 1111
Fan
Faul
Fan
4 Fau
l t
Fan
3 Fau
l t
Fan
2 Fau
l t
Fan
1 Fau
l t
Fan
4 M
Fan
3 M
Fan
2 M
Fan
1 M
02h
X
0 0000
Fan
g
at
i on
e:
0 =
D
1 =
RP
M
i n-
U
00 =
N
o s
i n-
up
01 =
tw
o TA
H
ounts
0.5s
10 =
tw
o TA
H
ounts
1s
11 =
tw
o TA
H
ounts
2s
H
i np
ut
ena
l e
H
Loc
0 =
TA
H
1 =
l
ock
r ot
Loc
ar
i ty
0 =
l
1 =
hi
g
03h
X
0 0000
Fan
g
at
i on
e as
an 1 C
onfi
g
ati
on
04h
X
0 0000
Fan
g
at
i on
e as
an 1 C
onfi
g
ati
on
05h
X
0 0000
Fan
g
at
i on
e as
an 1 C
onfi
g
ati
on
06h
Fan
i cs
Ra
e (
TA
H
p
i od
s)
1
2
4
8
16
32
32
32
R
te-
of-
C
e:
0s
er
LS
B (
D
m
e)
625s
er
LS
B (
RP
M
m
e)
0.0
15625s
er
LS
0.0
3125s
er
LS
0.0
625s
er
LS
0.1
25s
er
LS
0.2
er
LS
0.5
er
LS
1s
er
LS
07h
Fan
i cs
e as
an 1 D
nam
i cs
08h
Fan
i cs
e as
an 1 D
nam
i cs
09h
Fan
i cs
e as
an 1 D
nam
i cs
Register Map
Registers
MAX6620
Quad Linear Fan-Speed Controller
IS
ER
. /A
D
R
A
N D
7 D
6 D
5 D
4 D
3 D
2 D
1 D
0
10h
1 111
10
9D
8D
7D
6D
5D
4D
11h
0 0000
Fan
1 TA
H
1D
———
12h
1 1111
13h
0 0000
Fan
2 TA
H
e as
an 1 T
H
C
unt
14h
1 1111
15h
0 0000
Fan
3 TA
H
e as
an 1 T
H
C
unt
16h
1 1111
17h
0 0000
Fan
4 TA
H
e as
an 1 T
H
C
unt
18h
0 000
8D
7D
6D
5D
4D
3D
2D
19h
0 000
Fan
1 D
r
i ve
tag
————
l l
0 0000
0 0000
Fan
2 D
r
i ve
tag
e as
an 1 D
r i ve
ol
tag
0 0000
0 0000
Fan
3 D
r
i ve
tag
e as
an 1 D
r i ve
ol
tag
0 0000
1Fh
0 0000
Fan
4 D
r
i ve
tag
e as
an 1 D
r i ve
ol
tag
20h
1 1100
10
9D
8D
7D
6D
5D
4D
21h
0 000
Fan
1 Tar
g
H
C
oun
1D
———
22h
1 1100
23h
0 0000
Fan
2 Tar
g
H
C
oun
e as
an 1 T
g
et TA
H
C
ount
24h
1 1100
25h
0 0000
Fan
3 Tar
g
H
C
oun
e as
an 1 T
g
et TA
H
C
ount
26h
1 1100
27h
0 0000
Fan
4 Tar
g
H
C
oun
e as
an 1 T
g
et TA
H
C
ount
28h
X
X
X D
8D
7D
6D
5D
4D
3D
2D
29h
00
0 0000
Fan
1 Tar
g
r i ve
ol
tag
————
X
X
00
0 0000
Fan
2 Tar
g
r i ve
ol
tag
e as
an 1 T
g
et D
r i ve
ol
tag
hX
X
X
hX
00
0 0000
Fan
3 Tar
g
r i ve
ol
tag
e as
an 1 T
g
et D
r i ve
ol
tag
hX
X
X
2Fh
00
0 0000
Fan
4 Tar
g
r i ve
ol
tag
e as
an 1 T
g
et D
r i ve
ol
tag
X = Depends on input states at power-up.
Register Map (continued)

Partno	Mfg	Dc	Qty	Available	Descript
MAX6620ATI+T \|MAX6620ATIT	MAXIM	N/a	4486	avai	Quad Linear Fan-Speed Controller