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MAX6618AUB+T
PECI-to-I²C Translator
MAX6618
PECI-to-I2C Translator
General Description
The MAX6618 PECI(1.0)-to-I2C translator provides an
efficient, low-cost solution for PECI(1.0)-to-SMBus/I2C
protocol conversion. The PECI(1.0)-compliant host
reads temperature data directly from up to four
PECI(1.0)-enabled CPUs. This translator will only com-
municate with CPUs that support PECI 1.0.
The I2C interface provides an independent serial com-
munication channel to communicate synchronously with
peripheral devices in a multiple master or multiple slave
system. This interface allows a maximum serial-data
rate of 400kbps.
The MAX6618 is designed to operate from a +3.0V to
+3.6V supply voltage and ambient temperature range
of -20°C to +120°C.
Applications
Servers
Workstations
Desktop Computers
Features400kbps I2C-Compatible, 2-Wire Serial Interface+3V to +3.6V Supply VoltagePECI(1.0)-Compliant PortPECI(1.0)-to-I2C TranslationProgrammable Temperature Offsets-20°C to +120°C Operating Temperature RangeVREFInput Refers Logic Levels to the PECI
Supply VoltageAutomatic I2C Bus Lockup Timeout ResetLead-Free, 10-Pin µMAXPackage2C
MASTER
SDA
SCL
SDA
SCLPECI
+3.3V
VCPU
VTT
GND
CPU
INTERNAL
TEMP
SENSOR
VREF
VCC
AD0
AD1
AD2
MAX6618
Typical Application Circuit
Pin Configuration appears at end of data sheet.
Ordering Information
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
PARTTEMP RANGEPIN-PACKAGE
MAX6618AUB+-20°C to +120°C10 µMAX
MAX6618AUB+T-20°C to +120°C10 µMAX
µMAX is a registered trademark of Maxim Integrated Products.
MAX6618
PECI-to-I2C Translator
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC= +3V to +3.6V, VREF= +0.95V to +1.26V, TA= -20°C to +120°C, unless otherwise noted. Typical
values are at VCC= +3.3V, VREF= +1.0V, TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages with respect to GND.)
VCC..........................................................................-0.3V to +4V
AD0, AD1, AD2,..........................................-0.3V to (VCC+ 0.3V)
SCL, SDA .................................................................-0.3V to +6V
VREF.........................................................................-0.3V to +4V
PECI .........................................................-0.3V to (VREF+ 0.3V)
DC Current through SDA ...................................................10mA
Continuous Power Dissipation (TA= +70°C)
µMAX (derate 5.6mW/°C over TA= +70°C).................444mW
Operating Temperature Range.........................-20°C to +120°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SUPPLY
Operating Supply VoltageVCC3.03.6V
Operating Supply CurrentICCSCL = 400kHz47mA
Power-On-Reset VoltageVPOR2.602.95V
INPUT SCL, INPUT/OUTPUT SDA
Low-Level Input VoltageVIL0.3
x VCCV
High-Level Input VoltageVIH0.7
x VCC5.5V
Low-Level Output VoltageVOLIOL = 6mA0.4V
Leakage CurrentIL-1+1µA
Input CapacitanceCI10pF
ADDRESS INPUT AD0
Low-Level Input VoltageVIL0.3
x VCCV
High-Level Input VoltageVIH0.7
x VCC
VCC
+ 0.3V
Leakage CurrentIL-2+2µA
Input CapacitanceCI10pF
PECI
Supply Voltage to PECI CellVREF0.951.26V
Input Voltage RangeVIN-0.3VREF
+ 0.3V
Low-Level Input Voltage
ThresholdVIL0.275
x VREF
x VREFV
High-Level Input Voltage
ThresholdVIH0.550
x VREF
x VREFV
MAX6618
PECI-to-I2C Translator
ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, VCC= +3V to +3.6V, VREF= +0.95V to +1.26V, TA= -20°C to +120°C, unless otherwise noted. Typical
values are at VCC= +3.3V, VREF= +1.0V, TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
HysteresisVH0.1
x VREFV
Low-Level Sinking CurrentIIL0.51.0mA
High-Level Sourcing CurrentIIH-6mA
Input CapacitanceCI(Note 2)10pF
Signal-Noise Immunity Above
300MHzVN(Note 2)0.1
x VREFVP-P
TIMING CHARACTERISTICS
(Typical Application Circuit, VCC= +3V to +3.6V, VREF= +0.95V to +1.26V, TA= -20°C to +120°C, unless otherwise noted. Typical
values are at VCC= +3.3V, VREF= +1.0V, TA= +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS2C INTERFACE
Serial-Clock FrequencyfSCL400kHz
Bus Free Time Between a
STOP and a START ConditiontBUF1.3µs
Hold Time, (Repeated) START
ConditiontHD, STA0.6µs
Repeated START Condition
Setup TimetSU, STA0.6µs
STOP Condition Setup TimetSU, STO0.6µs
Data Hold TimetHD, DAT(Note 3)0.9µs
Data Setup TimetSU, DAT120ns
SCL Clock-Low PeriodtLOW1.3µs
SCL Clock-High PeriodtHIGH0.6µs
Rise Time of Both SDA and
SCL Signals, ReceivingtR(Notes 4, 5)20
+ 0.1Cb300ns
Fall Time of Both SDA and
SCL Signals, ReceivingtF(Notes 4, 5)20
+ 0.1Cb300ns
Fall Time of SDA TransmittingtF.TX(Notes 4, 5)20
+ 0.1Cb250ns
Pulse Width of Spike
SuppressedtSP(Notes 2, 6)50160ns
Capacitive Load for Each
Bus LineCb(Notes 2, 4)400pF
PECI INTERFACE
Overall time evident on PECI0.495500Bit Time (Note 7)tBITµs
MAX6618
PECI-to-I2C Translator
Note 1:All parameters are tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2:Guaranteed by design; not production tested.
Note 3:A master device must provide a hold time of at least 300ns for the SDA signal (referred to VILof the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 4:Cb= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VCCand 0.7 x VCC.
Note 5:ISINK≤6mA. Cb= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VCCand 0.7 x VCC.
Note 6:Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 7:The MAX6618 must drive a more restrictive time to allow for quantized sampling errors by a client yet still attain the mini-
mum time less than 500µs. tBITlimits apply equally to tBIT-Aand tBIT-M.
Note 8:The minimum and maximum bit times are relative to tBITdefined in the timing negotiation pulse.
Note 9:Extended trace lengths can appear as additional nodes.
Note 10:The client may deassert its low idle drive prior to the falling edge of the first bit of the message by using the rising edge to
detect a message start. However, the time delay must be sufficient to qualify the rising edge as a true message rather than
a noise spike.
Note 11:The message stop is defined by two consecutive periods when the bus has no rising edge. Tolerance around this time is
based on the tBIT-M error budget.
Note 12:tSETUPis not additive with tSTOP. Rather, these times may overlap.
TIMING CHARACTERISTICS (continued)
(Typical Application Circuit, VCC= +3V to +3.6V, VREF= +0.95V to +1.26V, TA= -20°C to +120°C, unless otherwise noted. Typical
values are at VCC= +3.3V, VREF= +1.0V, TA= +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Bit Time JittertBIT, jitter
Between adjacent bits in an PECI message
header or data bytes after timing has been
negotiated
Change in Bit TimetBIT, driftAcross a PECI address or PECI message
bits as driven by MAX66182%
High-Level Time for Logic-HightH1(Note 8)0.60.750.8x tBIT
High-Level Time for Logic-LowtH00.20.30.4x tBIT
Client Asserts PECI High
During Logic-HightSU00.2x tBIT-M
Rise TimetRMeasured from VOL to VPMAX,
VREF(nom) -5% (Note 9)
30 +
5/Nodens
Fall TimetFMeasured from VOH to VNMAX,
VREF(nom) +5% (Note 9)30/Nodens
Hold TimetHOLDTime for client to maintain a low idle drive
after MAX6618 begins a message (Note 10)0.5x tBIT-1
Stop TimetSTOPA constant low level driven by MAX6618
(Notes 8, 11)2x tBIT-M
Maximum Dwell Time of the
PECI ClienttRESET
From the end of a ResetDevice command
to the next message to which the reset
client must be able to respond
0.4ms
Minimum PECI Low Time
Preceding a MessagetSETUP
If the prior tBIT is not known by MAX6618,
the maximum tBIT must be assumed and
tSETUP = 1ms in this case (Note 12)
2x tBIT-X
MAX6618
PECI-to-I2C Translator
Pin Description
PINNAMEFUNCTIONPECIPlatform Environment Control Interface (PECI) Serial-Bus Input/OutputAGNDAnalog GroundAD0I2C Bus Device Address Selection Input A0SDAI2C Bus Data Input/OutputSCLI2C Bus Clock Input
6VCCPower Supply. Bypass to GND with a 0.1µF capacitor.GNDPower-Supply GroundAD2Internally Connected. Not used for I2C slave address selection. Must be connected to GND or VCC.AD1Internally Connected. Not used for I2C slave address selection. Must be connected to GND or VCC.VREFPECI Input Supply Voltage. Bypass VREF to AGND with a 0.1µF capacitor.
SDASCLI2C
PORT
PECI
TRANSLATION
ENGINE
PECI
PORT
VREFPECI
AD1
AD2
AD0
MAX6618
Block Diagram
MAX6618
PECI-to-I2C Translator
Configuration
The MAX6618 has four configuration registers (Table 1).
CONFIG0 is the main configuration register that enables
the PECI sockets, I2C bus timeout, PEC, alert activation,
and polling delay. CONFIG1 sets the numberof retries,
CONFIG2 sets the temperature offset, and CONFIG3
controls the temperature averaging. You can write to
the configuration registers to set the configuration or
read from the configuration registers to get the current
settings.
Detailed Description
The MAX6618 obtains temperature data from an inter-
nal temperature sensor in PECI-compliant hosts. Up to
four PECI hosts can be connected to the PECI I/O inter-
face. The MAX6618 handles all the PECI transmissions
and uses a 2-wire, I2C-compatible serial interface to
communicate with the PECI host.
Registers and Commands
The following is an overview of the I2C/SMBus regis-
ters/commands supported by the MAX6618.
ADDRESSDESCRIPTIONTRANSACTION TYPE
00hRead socket 0, domain 0 temperature registerReadWord
01hRead socket 0, domain 1 temperature registerReadWord
02hRead socket 1, domain 0 temperature registerReadWord
03hRead socket 1, domain 1 temperature registerReadWord
04hRead socket 2, domain 0 temperature registerReadWord
05hRead socket 2, domain 1 temperature registerReadWord
06hRead socket 3, domain 0 temperature registerReadWord
07hRead socket 3, domain 1 temperature registerReadWord
08hRead maximum temperature for all enabled sockets/domains registerReadWord
09hRead firmware version registerReadWord
0AhRead maximum temperature addressReadWord
0BhRead socket and domain that caused alertReadWord
0ChRead/write CONFIG0 registerReadWord/WriteWord
0DhRead/write CONFIG1 registerReadWord/WriteWord
0EhRead/write CONFIG2 registerReadWord/WriteWord
0FhRead/write CONFIG3 registerReadWord/WriteWord
10hRead/write alert temperature for socket 0ReadWord/WriteWord
11hRead/write alert temperature for socket 1ReadWord/WriteWord
12hRead/write alert temperature for socket 2ReadWord/WriteWord
13hRead/write alert temperature for socket 3ReadWord/WriteWord
14hRequest pollingSendByte
15hClear alertSendByte
COMMAND BYTEREGISTER DESCRIPTIONTYPERESULT
0ChCONFIG0 registerReadWord/WriteWordSee the CONFIG0 section.
0DhCONFIG1 registerReadWord/WriteWordSee the CONFIG1 section.
0EhCONFIG2 registerReadWord/WriteWordSee the CONFIG2 section.
0FhCONFIG3 registerReadWord/WriteWordSee the CONFIG3 section.
Table 1. Configuration Registers
MAX6618
PECI-to-I2C Translator
CONFIG0
The CONFIG0 register holds a bit mask for PECI sock-
ets and domains that are enabled for polling as well as
a polling delay (minimum delay between sets of polls)
and features enable/disable bits. Table 2 shows the
various options for CONFIG0.
The optional polling delay (bits 2:0) inserts after polling
the set of all sockets and domains that are enabled in
bits 15:8 with a minimal pause of 2.5ms between PECI
reads. After polling all enabled sockets and domains,
the device pauses PECI communications for the config-
ured time before starting to poll the set of enabled
sockets and domains again. Table 3 shows the various
polling delay options.
CONFIG1
The CONFIG1 register configures the maximum num-
ber of retries before aborting a PECI temperature read
as well as the originated (suggested) PECI bit time.
Table 4 shows the various options for CONFIG1.
Software must configure this value as the register
default may cause improper operation.
BIT(S)DESCRIPTIONDEFAULT
15:8Polling enable for sockets and domains00h1 = enable socket 3, domain 101 = enable socket 3, domain 001 = enable socket 2, domain 101 = enable socket 2, domain 001 = enable socket 1, domain 101 = enable socket 1, domain 001 = enable socket 0, domain 101 = enable socket 0, domain 001 = enable I2C bus lockup timeout
0 = Disable timeout11 = alternate data representation
0 = 16-bit data representation0
1 = enable I2C packet error checksum
(PEC) on device return data
0 = Disable PEC1 = mask temperature alerts
0 = Activate alerts0Reserved, set to 00
2:0Poll delay, see Table 35
Table 2. CONFIG0 Register
POLL DELAY VALUEDELAY BETWEEN POLLS (ms)Polling on request only2.5
450100 (default)500Reserved
Table 3. Polling Delay
BIT(S)DESCRIPTIONDEFAULT
15:8
Originated PECI bit time
(before negotiation)
01h: RESERVED
14h…0FFh: CONFIG1[15:8] + 1µs
Minimum: 14h (= 21µs / 47.62kHz)
Maximum: 0FFh (= 256µs / 3.906kHz)
02h
7:0Maximum number of retries for PECI
transactions03h
Table 4. CONFIG1 Register
MAX6618
PECI-to-I2C Translator
CONFIG2
The CONFIG2 register holds the offset that is added to
all temperature return values that are not error codes.
The offset is enabled in CONFIG0, bit 6; +95°C is set
as 17C0h or 005Fh, depending on the data format. To
represent +95°C in 16-bit representation, convert
+95°C to binary using two’s complement and left-shift
six times. The MAX6618 automatically converts the off-
set value to the equivalent value when the data format
is changed. See Table 5 for the default offset and Table
6 for some example values.
When configured in CONFIG2 and the return code is not
an error code (see the Error Codes section), the device
adds the offset value stored in CONFIG2 to the return
value. For example, if the CPU’s thermal control circuit
activation point is at +95°C, CONFIG2 can be set to
+95°C (005Fh or 17C0h) and all return values are con-
verted to absolute temperatures. Note that the thermal
control circuit activation point is CPU specific. The offset
value is represented in the current data format.
CONFIG3
CONFIG3 register configures the temperature averaging
function. See the Temperature Averagingsection for
more information. Table 7 shows the default settings.
Temperature Representation
Temperature data is formatted in 16-bit two’s comple-
ment representing a range from -512°C to +512°C in
steps of 1/64°C (Figure 1). Internally, the device always
uses the 16-bit data format. The temperature is given in
two’s complement and left-shifted so that the +1°C bit
is bit 6 (Figure 2). Temperatures can be represented
externally in alternate data format if fractional readings
are not needed. Table 8 shows some examples.
BIT(S)DESCRIPTIONDEFAULT
15:0Temperature offset0000h
Table 5. CONFIG2 Register
BINARYTEMP (°C)HEXRESHIRESLO0000h0000 00000000 0000
+250640h0000 01100100 0000
+500C80h0000 11001000 0000
+7512C0h0001 00101100 0000
+9517C0h0001 01111100 0000
Table 6. Example Offset Values in 16-Bit
Temperature Representation
BIT(S)DESCRIPTIONDEFAULT
15:8Reserved, set to 000h
7:0Averaging shift count, see formula00h
Table 7. CONFIG3 Register
RESLO
1°C1°C°C°C°C°C1234567
Figure 1. Temperature Measured in 1/64°C Steps
-50°C00110111
TWO'S
COMPLEMENT
RESLORESHI123456789101112131415
Figure 2. Conversion of Temperature Done in Two’s
Complement
BINARYTEMP
(°C)
RELATIVE
TEMP (°C)HEXRESHIRESLO
+94-1FFC0h1111 11111100 0000
+85-10FD80h1111 11011000 0000
+70-25FDC0h1111 11011100 0000
+45-50F380h1111 00111000 0000
+20-75ED30h1110 11010100 0000
Table 8. Example of 16-Bit Representation
with No Offset (Activation Point = +95°C)
MAX6618
PECI-to-I2C Translator
Alternate Temperature Value Representation
This optional feature can be enabled using bit 6 of
CONFIG0. When the alternate data format is enabled, the
temperature value is shifted right as shown in Table 9. The
most significant bits are set to all 0s or all 1s depending on
the sign bit 15, also shown as S in Figure 3.Table 10
shows some example values. This translation is not per-
formed for error codes (16-bit values from 8000h
through 81FFh).
Excluding error codes, the software only has to exam-
ine the RESLO data byte, as it represents an integer
value in the range from -128°C to +127°C in 1°C steps.
The RESHI byte is all 0s or all 1s for valid return codes,
and either 80h or 81h for all error codes.
Temperature Averaging
The MAX6618 can average several temperature read-
ings and return a value as calculated by:
where TOLDis the previously stored temperature, TPECI
is the new value read from PECI, and TNEWis the newly
stored temperature ready to be returned through I2C.
This calculation can cause significant bits to be lost.
Enable temperature averaging by writing the desired
averaging amount to the CONFIG3 register. Writing 00h
to the CONFIG3 register disables temperature averaging.TNEWCONFIGPECICONFIG=+−11133xTOLDXX1211109876XXXXXXSSSSSSSS1211109876
INTEGER VALUE (~ 1°C)(SIGN BITS)
RESHIRESLO
FRACTIONAL VALUE
Figure 3. Alternate Temperature Representation
DESCRIPTIONRESHIRESLO
16-bit value15:14:13:12:11:10:9:87:6:5:4:3:2:1:0
Alternate
representation15:15:15:15:15:15:15:1515:12:11:10:9:8:7:6
Table 9. Alternate Temperature
Representation
BINARYTEMP (°C)RELATIVE TEMP (°C)HEXRESHIRESLO
+94-1FFFFh1111 11111111 1111
+85-10FFF6h1111 11111111 0110
+70-25FFE7h1111 11111110 0111
+45-50FFCEh1111 11111100 1110
+20-75FFB5h1111 11111011 0101
Table 10. Example of Alternate Representation with No Offset (Activation Point = +95°C)

Partno	Mfg	Dc	Qty	Available	Descript
MAX6618AUB+T \|MAX6618AUBT	MAXIM	N/a	10000	avai	PECI-to-I²C Translator