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MAX6366LKA46-T
2.38 V, SOT23, low-power, mP supervisory circuit with battery backup and chip-enable gating
General DescriptionThe MAX6365–MAX6368 supervisory circuits simplify
power-supply monitoring, battery-backup control func-
tions, and memory write protection in microprocessor
(µP) systems. The circuits significantly improve the size,
accuracy, and reliability of modern systems with an ultra-
small integrated solution.
These devices perform four basic system functions:
1) Provide a µP reset output during VCCsupply power-
up, power-down, and brownout conditions.
2) Internally control VCCto backup-battery switching to
maintain data or low-power operation for CMOS
RAM, CMOS µPs, real-time clocks, and other digital
logic when the main supply fails.
3) Provide memory write protection through internal
chip-enable gating during supply or processor faults.
4) Include one of the following options: a manual reset
input (MAX6365), a watchdog timer function
(MAX6366), a battery-on output (MAX6367), or an
auxiliary user-adjustable reset input (MAX6368).
The MAX6365–MAX6368 operate from VCCsupply volt-
ages as low as 1.2V. The factory preset reset threshold
voltages range from 2.32V to 4.63V (see Ordering
Information). In addition, each part is offered in three
reset output versions: push-pull active low, open-drain
active low, or open-drain active high (see Selector
Guide). The MAX6365–MAX6368 are available in minia-
ture 8-pin SOT23 packages.
ApplicationsCritical µP/µC Power Portable/Battery-
Monitoring Powered Equipment
Fax MachinesSet-Top Boxes
Industrial ControlPOS Equipment
Computers/Controllers
FeaturesLow +1.2V Operating Supply Voltage (VCCor VBATT)Precision Monitoring of +5.0V, +3.3V, +3.0V, and
+2.5V Power-Supply VoltagesOn-Board Gating of Chip-Enable Signals, 1.5ns
Propagation DelayDebounced Manual Reset Input (MAX6365)Watchdog Timer, 1.6s Timeout (MAX6366)Battery-On Output Indicator (MAX6367)Auxiliary User-Adjustable RESET IN (MAX6368)Low 10µA Quiescent Supply CurrentThree Available Output Structures
Push-Pull RESET
Open-Drain RESET
Open-Drain RESETRESET/RESET Valid Down to 1.2V Guaranteed
(VCCor VBATT)Power-Supply Transient Immunity150ms min Reset Timeout PeriodMiniature 8-Pin SOT23 Package
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
Pin Configurations19-1658; Rev 1; 6/01
Ordering Information*These parts offer a choice of reset threshold voltages. From the
Reset Threshold Ranges table, insert the desired threshold volt-
age code in the blank to complete the part number. SOT parts
come in tape-and-reel only and must be ordered in 2500-piece
increments. See Device Marking Codes for a complete parts list,
including SOT top marks and standard threshold versions. See
Selector Guide for a listing of device features.
Typical Operating Circuit appears at end of data sheet.
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= +2.4V to +5.5V, VBATT= +3.0V, CEIN = VCC, reset not asserted, TA= -40°C to +85°C. Typical values are at TA= +25°C,
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Terminal Voltages (with respect to GND)
VCC, BATT, OUT.......................................................-0.3V to +6V
RESET(open drain), RESET (open drain)................-0.3V to +6V
BATT ON, RESET(push-pull), RESET IN,
WDI, CEIN, CEOUT...........................-0.3V to (VOUT+ 0.3V)MR..............................................................-0.3V to (VCC+ 0.3V)
Input Current
VCCPeak..............................................................................1A
VCCContinuous.............................................................250mA
BATT Peak.....................................................................250mA
BATT Continuous.............................................................40mA
GND...............................................................................75mA
Output Current
OUT...............................Short-Circuit Protected for up to 10s
RESET, RESET, BATT ON, CEOUT...............................20mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SOT23 (derate 8.75mW/°C above +70°C)........700mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature .....................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +2.4V to +5.5V, VBATT= +3.0V, CEIN = VCC, reset not asserted, TA= -40°C to +85°C. Typical values are at TA= +25°C,
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +2.4V to +5.5V, VBATT= +3.0V, CEIN = VCC, reset not asserted, TA= -40°C to +85°C. Typical values are at TA= +25°C,
Note 1:All devices are 100% production tested at TA= +25°C. Limits over temperature are guaranteed by design.
Note 2:VBATTcan be 0 anytime, or VCCcan go down to 0 if VBATTis active (except at startup).
Note 3:RESET is pulled up to OUT. Specifications apply for OUT = VCCor OUT = BATT.
Note 4:The chip-enable resistance is tested with VCC= VTH(MAX)and CEIN = VCC/2.
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
MAX6368
RESET IN THRESHOLD
vs. TEMPERATUREMAX6365/8 -10
TEMPERATURE (°C)
RTH
(V)
MAX6368
RESET IN TO RESET PROPAGATION DELAY
vs. TEMPERATURE
MAX6365/8-11
TEMPERATURE (°C)
PROPAGATION DELAY (
MAX6365/8-12
CLOAD (pF)
PROPAGATION DELAY (ns)10050150200
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCEMAX6365/8-13
TEMPERATURE (°C)
CE IN TO CE OUT ON-RESISTANCE (
CE IN TO CE OUT ON-RESISTANCE
vs. TEMPERATUREMAX6365/8-14
TEMPERATURE (°C)
WATCHDOG TIMEOUT PERIOD (s)
MAX6366
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
Typical Operating Characteristics (continued)(TA = +25°C, unless otherwise noted.)
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
Detailed DescriptionThe Typical Operating Circuitshows a typical connec-
tion for the MAX6365–MAX6368. OUT powers the static
random-access memory (SRAM). If VCCis greater than
the reset threshold (VTH), or if VCCis lower than VTH
but higher than VBATT, VCCis connected to OUT. If
VCCis lower than VTHand VCCis less than VBATT,
BATT is connected to OUT. OUT supplies up to 150mA
from VCC. In battery-backup mode, an internal MOSFET
connects the backup battery to OUT. The on-resistance
of the MOSFET is a function of backup-battery voltage
and is shown in the BATT-to-OUT On-Resistance vs.
Temperature graph in the Typical Operating Char-
acteristics.
Chip-Enable Signal GatingThe MAX6365–MAX6368 provide internal gating of CE
signals to prevent erroneous data from being written to
CMOS RAM in the event of a power failure. During nor-
mal operation, the CEgate is enabled and passes alltransitions. When reset asserts, this path becomes
disabled, preventing erroneous data from corrupting
the CMOS RAM. All of these devices use a series trans-
mission gate from CEIN to CEOUT. The 2ns propaga-
tion delay from CEIN to CEOUT allows the devices to
be used with most µPs and high-speed DSPs.
During normal operation, CEIN is connected to CE
OUT through a low on-resistance transmission gate.
This is valid when reset is not asserted. If CEIN is high
when reset is asserted, CEOUT remains high regard-
less of any subsequent transitions on CEIN during the
reset event.
If CEIN is low when reset is asserted, CEOUT is held
low for 12µs to allow completion of the read/write oper-
ation (Figure 1). After the 12µs delay expires, the CE
Functional Diagram
