MAX6367LKA29+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingApplicationsM A X6 36 7 LK A_ _-T -40°C to +85°C 8 SOT23Critical µP/µC Power Portable/Battery-M A ..
MAX6367PKA29+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingFeaturesThe MAX6365–MAX6368 supervisory circuits simplify ♦ Low +1.2V Operating Supply Voltage (V o ..
MAX6368LKA26+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingMAX6365–MAX6368 19-1658; Rev 5; 10/11SOT23, Low-Power µP Supervisory Circuitswith Battery Backup an ..
MAX6368LKA29+ ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable Gatingfeatures.MAX6365Devices are available in both leaded and lead(Pb)-free packaging.GND 3 6 OUTSpecify ..
MAX6368PKA29+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingFeaturesThe MAX6365–MAX6368 supervisory circuits simplify ♦ Low +1.2V Operating Supply Voltage (V o ..
MAX6368PKA31+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingMAX6365–MAX6368 19-1658; Rev 5; 10/11SOT23, Low-Power µP Supervisory Circuitswith Battery Backup an ..
MB15U10 ,Dual Serial Input PLL Frequency Synthesizer On-Chip 1.1 GHz PrescalerFUJITSU SEMICONDUCTORDS04-21339-2EDATA SHEETASSPDual Serial Input PLL Frequency SynthesizerOn-Chip ..
MB15U10PFV ,Dual Serial Input PLL Frequency Synthesizer On-Chip 1.1 GHz PrescalerFUJITSU SEMICONDUCTORDS04-21339-2EDATA SHEETASSPDual Serial Input PLL Frequency SynthesizerOn-Chip ..
MB15U36 ,Dual PLL Frequency Synthesizer with On-Chip PrescalerFeatures Very low spurious and phase noise characteristics 18-bit programmable divider:– Binary 7 ..
MB15U36PFV ,Dual PLL Frequency Synthesizer with On-Chip PrescalerFeatures Very low spurious and phase noise characteristics 18-bit programmable divider:– Binary 7 ..
MB2245BB ,16-bit transceivers with direction pins 3-State
MB2245BB ,16-bit transceivers with direction pins 3-State
MAX6365HKA46+T-MAX6365LKA31+-MAX6365LKA46+T-MAX6365PKA31+T-MAX6366LKA29+-MAX6366PKA29+T-MAX6367LKA29+T-MAX6367PKA29+T-MAX6368LKA26+T-MAX6368LKA29+-MAX6368PKA29+T-MAX6368PKA31+T-MAX6368PKA46+T
SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable Gating
General DescriptionThe MAX6365–MAX6368 supervisory circuits simplify
power-supply monitoring, battery-backup control func-
tions, and memory write protection in microprocessor
(µP) systems. The circuits significantly improve the size,
accuracy, and reliability of modern systems with an ultra-
small integrated solution.
These devices perform four basic system functions:
1) Provide a µP reset output during VCCsupply power-
up, power-down, and brownout conditions.
2) Internally control VCCto backup-battery switching to
maintain data or low-power operation for CMOS
RAM, CMOS µPs, real-time clocks, and other digital
logic when the main supply fails.
3) Provide memory write protection through internal
chip-enable gating during supply or processor faults.
4) Include one of the following options: a manual reset
input (MAX6365), a watchdog timer function
(MAX6366), a battery-on output (MAX6367), or an
auxiliary user-adjustable reset input (MAX6368).
The MAX6365–MAX6368 operate from VCCsupply volt-
ages as low as 1.2V. The factory preset reset threshold
voltages range from 2.32V to 4.63V (see the Ordering
Information). In addition, each part is offered in three
reset output versions: push-pull active low, open-drain
active low, or open-drain active high (see the Selector
Guide). The MAX6365–MAX6368 are available in minia-
ture 8-pin SOT23 packages.
ApplicationsCritical µP/µC Power Portable/Battery-
Monitoring Powered Equipment
Fax MachinesSet-Top Boxes
Industrial ControlPOS Equipment
Computers/Controllers
FeaturesLow +1.2V Operating Supply Voltage (VCCor VBATT)Precision Monitoring of +5.0V, +3.3V, +3.0V, and
+2.5V Power-Supply VoltagesOn-Board Gating of Chip-Enable Signals, 1.5ns
Propagation DelayDebounced Manual Reset Input (MAX6365)Watchdog Timer, 1.6s Timeout (MAX6366)Battery-On Output Indicator (MAX6367)Auxiliary User-Adjustable RESET IN (MAX6368)Low 10µA Quiescent Supply CurrentThree Available Output Structures
Push-Pull RESET
Open-Drain RESET
Open-Drain RESETRESET/RESET Valid Down to 1.2V Guaranteed
(VCCor VBATT)Power-Supply Transient Immunity150ms min Reset Timeout PeriodMiniature 8-Pin SOT23 Package
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable GatingOUT
VCCMR
CE OUT
BATTCE IN
GND
RESET, RESET
SOT23TOP VIEW
MAX6365
Pin Configurations19-1658; Rev 5; 10/11
Ordering Information*These parts offer a choice of reset threshold voltages. From the
Reset Threshold Ranges table, insert the desired threshold volt-
age code in the blank to complete the part number. SOT parts
come in tape and reel only and must be ordered in 2500-piece
increments. See Device Marking Codes for a complete parts list,
including SOT top marks and standard threshold versions. See
Selector Guide for a listing of device features.
Devices are available in both leaded and lead(Pb)-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
-Denotes a package containing lead(Pb).= Tape and reel.
/V Denotes an automotive qualified part.
PART*TEMP RANGEPIN-PACKAGEA X6 3 6 5 LK A_ _-T-40°C to +85°C8 SOT23
MAX6365PKA_ _-T-40°C to +85°C8 SOT23
MAX6365HKA_ _-T-40°C to +85°C8 SOT23
A X6 3 6 6 LK A_ _-T-40°C to +85°C8 SOT23A X 6 36 6P K A_ _-T-40°C to +85°C8 SOT23A X 6 36 6H K A_ _-T-40°C to +85°C8 SOT23
A X6 3 6 7 LK A_ _-T-40°C to +85°C8 SOT23A X 6 36 7P K A_ _-T-40°C to +85°C8 SOT23A X 6 36 7P K A_ _/V-T-40°C to +85°C8 SOT23A X 6 36 7H K A_ _-T-40°C to +85°C8 SOT23
A X6 3 6 8 LK A_ _-T-40°C to +85°C8 SOT23A X 6 36 8P K A_ _-T-40°C to +85°C8 SOT23A X 6 36 8H K A_ _-T-40°C to +85°C8 SOT23
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= +2.4V to +5.5V, VBATT= +3.0V, CEIN = VCC, reset not asserted, TA= -40°C to +85°C. Typical values are at TA= +25°C,
unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Terminal Voltages (with respect to GND)
VCC, BATT, OUT.......................................................-0.3V to +6V
RESET(open drain), RESET (open drain)................-0.3V to +6V
BATT ON, RESET(push-pull), RESET IN,
WDI, CEIN, CEOUT...........................-0.3V to (VOUT+ 0.3V)
MR..............................................................-0.3V to (VCC+ 0.3V)
Input Current
VCCPeak..............................................................................1A
VCCContinuous.............................................................250mA
BATT Peak.....................................................................250mA
BATT Continuous.............................................................40mA
GND...............................................................................75mA
Output Current
OUT...............................Short-Circuit Protected for up to 10s
RESET, RESET, BATT ON, CEOUT...............................20mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SOT23 (derate 8.75mW/°C above +70°C)........700mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature .....................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow)
Lead (Pb)-free packages..............................................+260°C
Packages containing lead (Pb).....................................+240°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOperating Voltage Range
(Note 2)VCC, VBATTNo load05.5V
VCC = 2.8V1030
VCC = 3.6V1235Supply Current
(Excluding IOUT)ICCNo load, VCC > VTH
VCC = 5.5V1550
TA = +25°C1Supply Current in Battery-
Backup Mode (Excluding IOUT)IBACKVBATT = 2.8V,
VCC = 0VTA = -40°C to +85°C3µA
TA = +25°C-0.10+0.02BATT Standby CurrentIBATT5.5V > VCC > (VBATT
+ 0.2V)TA = -40°C to +85°C-1.00+0.05µA
VCC = 4.75V, IOUT = 150mA3.1
VCC = 3.15V, IOUT = 65mA3.7VCC to OUT On-ResistanceRON
VCC = 2.38V, IOUT = 25mA4.6
VBATT = 4.5V, IOUT = 20mAVBATT -
VBATT = 3.0V, IOUT = 10mAVBATT -
Output Voltage in Battery-
Backup ModeVOUT
VBATT = 2.25V, IOUT = 5mAVBATT -
Power-up20Battery-Switchover Threshold
(VCC - VBATT) VSWVCC < VTHPower-down-20mV
MAX636_ _KA464.504.634.75
MAX636_ _KA444.254.384.50
MAX636_ _KA313.003.083.15
MAX636_ _KA292.852.933.00
MAX636_ _KA262.552.632.70
Reset ThresholdVTH
MAX636_ _KA232.252.322.38
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
ELECTRICAL CHARACTERISTICS (continued)(VCC= +2.4V to +5.5V, VBATT= +3.0V, CEIN = VCC, reset not asserted, TA= -40°C to +85°C. Typical values are at TA= +25°C,
unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSReset Active Timeout PeriodtRP150280ms
ISINK = 1.6mA,
VCC > 2.1V0.3
VOLReset asserted,
VBATT = 0VISINK = 100µA,
VCC > 1.2V0.4RESET Output Voltage
VOHReset not asserted
(MAX636_L only)
ISOURCE = 500µA,
VCC > VTH(MAX)
0.8 ✕
VCC
VOLReset not assertedISINK = 1.6mA,
VCC > VTH (MAX)0.3
ISOURCE = 1mA,
VCC > 1.8V
0.7 ✕
VCCRESET Output Voltage
VOH
Reset not asserted,
VBATT = 0V
(MAX636_H only)
(Note 3)
ISOURCE = 200µA,
VCC > 1.2V
0.8 ✕
VCC
RE S E T Outp ut Leakag e C ur r entILKGMAX636_P and MAX636_H only1µA
MANUAL RESET (MAX6365 only)VIL0.3 ✕
VCC
MR Input Voltage
VIH0.7 ✕
VCC
Pullup Resistance20kΩ
Minimum Pulse Width1µs
Glitch ImmunityVCC = 3.3V100ns
MR to Reset DelayVCC = 3.3V120ns
WATCHDOG (MAX6366 only)Watchdog Timeout PeriodtWD1.001.652.25s
Minimum WDI Input Pulse WidthtWDI100ns
VIL0.3 ✕
VCC
WDI Input Voltage
VIH0.7 ✕
VCC
WDI Input Current-1.01.0µA
BATT ON (MAX6367 only)Output VoltageVOLISINK = 3.2mA, VBATT = 2.1V0.4V
Sink current, VCC = 5V60mA
Output Short-Circuit Current
Source current, VBATT > 2V1030100µA
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE (NO LOAD)
MAX6365/8-01
TEMPERATURE (°C)
SUPPLY CURRENT (
VCC = 5.0V
VBATT = 0V
BATTERY SUPPLY CURRENT
(BACKUP MODE) vs. TEMPERATURE
MAX6365/8-02
TEMPERATURE (°C)
BATTERY SUPPLY CURRENT (
VBATT = 2.0V
VCC = 0
VBATT = 2.8V
BATT-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
MAX6365/8-03
TEMPERATURE (°C)
BATT-TO-OUT ON-RESISTANCE (
VBATT = 5.0V
VBATT = 2.0V
VBATT = 2.8V
IOUT = 25mA
VCC = 0V
ELECTRICAL CHARACTERISTICS (continued)(VCC= +2.4V to +5.5V, VBATT= +3.0V, CEIN = VCC, reset not asserted, TA= -40°C to +85°C. Typical values are at TA= +25°C,
unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
RESET IN (MAX6368 only)RESET IN ThresholdVRTH1.1851.2351.285V
RESET IN Leakage Current±0.01±25nA
RESET IN to Reset DelayVOD = 50mV, RESET IN falling1.5µs
CHIP-ENABLE GATINGCE IN Leakage CurrentReset asserted±1µA
CE IN to CE OUT ResistanceReset not asserted (Note 4)20100Ω
CE OUT Short-Circuit CurrentReset asserted, VCE OUT = 0V0.752.0mA
VCC = 4.75V1.57CE IN to CE OUT Propagation
Delay
50Ω source,
CLOAD = 6365 50pFVCC = 3.15V29ns
VCC = 5V, VCC > VBATT, ISOURCE = 100µA0.8 ✕ VCC
CE OUT Output Voltage High
VCC = 0V, VBATT > 2.2V, ISOURCE = 1µAVBATT -
Reset-to-CE OUT Delay12µs
Note 1:All devices are 100% production tested at TA= +25°C. Limits over temperature are guaranteed by design.
Note 2:VBATTcan be 0V anytime, or VCCcan go down to 0V if VBATTis active (except at startup).
Note 3:RESET is pulled up to OUT. Specifications apply for OUT = VCCor OUT = BATT.
Note 4:The chip-enable resistance is tested with VCC= VTH(MAX)and VCEIN= VCC/2.
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
Typical Operating Characteristics (continued)(TA = +25°C, unless otherwise noted.)
VCC TO OUT ON-RESISTANCE
vs. TEMPERATURE
MAX6365/8-04
TEMPERATURE (°C)
TO OUT ON-RESISTANCE (
VCC = 3.0V
IOUT = 65mA
VCC = 4.5V
IOUT = 150mA
VCC = 2.3V
IOUT = 25mA
RESET TIMEOUT PERIOD
vs. TEMPERATURE
MAX6365/8-05
TEMPERATURE (°C)
RESET TIMEOUT PERIOD (ms)
TEMPERATURE (°C)
PROPAGATION DELAY (
VCC TO RESET PROPAGATION DELAY
vs. TEMPERATURE
VCC FALLING
0.25V/ms
1V/ms
10V/ms
RESET THRESHOLD
vs. TEMPERATURE
MAX6365/8-07
TEMPERATURE (°C)
THRESHOLD (V)
MAX636_ 46 (VTH = 4.63V)
MAX636_ 26 (VTH = 2.63V)
110010100010,000
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVEMAX6365/8-08
RESET THRESHOLD OVERDRIVE VTH - VCC (mV)
MAXIMUM TRANSIENT DURATION (
MAX636_ 26
(VTH = 2.63V)
MAX636_ 46
(VTH = 4.63V)
RESET OCCURS
ABOVE CURVE0.51.01.52.02.53.03.5
BATTERY SUPPLY CURRENT
vs. SUPPLY VOLTAGEMAX6365/8-09
VCC (V)
BATTERY SUPPLY CURRENT (
VTH = 2.93V
VBATT = 2.8V
VBATT = 2.5V
VBATT = 2.3V
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable GatingMAX6368
RESET IN THRESHOLD
vs. TEMPERATURE
MAX6365/8 -10
TEMPERATURE (°C)
RTH
(V)
MAX6368
RESET IN TO RESET PROPAGATION DELAY
vs. TEMPERATURE
MAX6365/8-11
TEMPERATURE (°C)
PROPAGATION DELAY (
VOD = 50mV
MAX6365/8-12
CLOAD (pF)
PROPAGATION DELAY (ns)10050150200
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCEVCE IN = 0V TO VCC
DRIVER SOURCE
IMPEDANCE = 50Ω
VCC = 3V
VCC = 5V
MAX6365/8-13
TEMPERATURE (°C)
CE IN TO CE OUT ON-RESISTANCE (
CE IN TO CE OUT ON-RESISTANCE
vs. TEMPERATUREVCC = 3.0V
VCC = 5.0V
VCE IN = VCC/2
VBATT = 0V
MAX6365/8-14
TEMPERATURE (°C)
WATCHDOG TIMEOUT PERIOD (s)
MAX6366
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATUREVCC = 5.0V
VBATT = 0V
Typical Operating Characteristics (continued)(TA = +25°C, unless otherwise noted.)
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable Gating
Pin Description
PINNAMEFUNCTIONRESET
Acti ve- H i g h Reset Outp ut. RE S E T asser ts hi g h conti nuousl y w hen V C C i s b el ow the r eset thr eshol d ( V TH ) ,R i s l ow , or RE S E T IN i s l ow . It asser ts i n p ul ses w hen the inter nal w atchd og ti m es out. RE S E T r em ai ns
asser ted for the r eset ti m eout p er i od ( tRP ) after V C C r i ses ab ove the r eset thr eshol d , after the m anual r esetnp ut g oes fr om l ow to hi g h, after RE S E T IN g oes hi g h, or after the w atchd og tr i g g ers a r eset event.
RE S E T i s an op en- d r ai n acti ve- hi g h r eset outp ut.
RESET
Active-Low Reset Output. RESET asserts low continuously when V C C is below the reset threshold
(VTH), the manual reset input is low, or RESET IN is low. It asserts low in pulses when the internal
watchdog times out. RESET remains asserted low for the reset timeout period (tRP) after V C C
rises above the reset threshold, after the manual reset input goes from low to high, after RESET
IN goes high, or after the watchdog triggers a reset event. The MAX636_L is an active-low push-
pull output, while the MAX636_P is an active-low open-drain output.CE INChip-Enable Input. The input to chip-enable gating circuitry. Connect to GND or OUT if not used.GNDGround
MAX6365 Manual-Reset Input. Maintaining logic low on MR asserts a reset. Reset outputremains asserted as long as MR is low and for the reset timeout period (tRP) after MR transitions
from low to high. Leave unconnected, or connect to VCC if not used. MR has an internal 20kΩ
pullup to VCC.
WDI
MAX6366 Watchdog Input. If WDI remains high or low for longer than the watchdog timeoutperiod (t W D ), the internal watchdog timer runs out and a reset pulse is triggered for the reset
timeout period (tRP). The internal watchdog clears whenever reset asserts or whenever WDI sees
a rising or falling edge (Figure 2).
BATT ON
MAX6367 Battery-On Output. BATT ON goes high when in battery-backup mode.RESET IN
MAX6368 Reset Input. When RESET IN falls below 1.235V, reset asserts. Reset output remainsasserted as long as RESET IN is low and for at least tRP after RESET IN goes high.
5VCC
Supply Voltage, 1.2V to 5.5V. Reset asserts when V C C drops below the reset threshold voltage
(VTH). Reset remains asserted until V C C rises above VTH and for at least tRP after V C C rises
above VTH.OUTOutput. OUT sources from V C C when not in reset and from the greater of VCC or BATT when V C C
is below the reset threshold.BATT
Backup-Battery Input. When V C C falls below the reset threshold, OUT switches to BATT if VBATT
is 20mV greater than V C C . When V C C rises 20mV above VBATT, OUT switches to V C C . The 40mV
hysteresis prevents repeated switching if VCC falls slowly.CE OUT
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted. If CE
IN is low when reset is asserted, CE OUT will stay low for 12µs (typ) or until CE IN goes high,
whichever occurs first.
MAX6365–MAX6368
SOT23, Low-Power µP Supervisory Circuits
with Battery Backup and Chip-Enable GatingMAX6365
MAX6366
MAX6367
MAX6368
CHIP-ENABLE
OUTPUT
CONTROL
VCC
BATT
CE IN
20k
(MAX6365 ONLY)
WDI
(MAX6366 ONLY)
RESET IN
(MAX6368 ONLY)
RESET
GENERATOR
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
1.235V
GND
1.235V
RESET
(RESET)
CE OUT
OUT
BATT ON (MAX6367 ONLY)
Detailed DescriptionThe Typical Operating Circuitshows a typical connec-
tion for the MAX6365–MAX6368. OUT powers the static
random-access memory (SRAM). If VCCis greater than
the reset threshold (VTH), or if VCCis lower than VTH
but higher than VBATT, VCCis connected to OUT. If
VCCis lower than VTHand VCCis less than VBATT,
BATT is connected to OUT. OUT supplies up to 150mA
from VCC. In battery-backup mode, an internal MOSFET
connects the backup battery to OUT. The on-resistance
of the MOSFET is a function of backup-battery voltage
and is shown in the BATT-to-OUT On-Resistance vs.
Temperature graph in the Typical Operating Char-
acteristics.
Chip-Enable Signal GatingThe MAX6365–MAX6368 provide internal gating of CE
CMOS RAM in the event of a power failure. During nor-
mal operation, the CEgate is enabled and passes alltransitions. When reset asserts, this path becomes
disabled, preventing erroneous data from corrupting
the CMOS RAM. All of these devices use a series trans-
mission gate from CEIN to CEOUT. The 2ns propaga-
tion delay from CEIN to CEOUT allows the devices to
be used with most µPs and high-speed DSPs.
During normal operation, CEIN is connected to CE
OUT through a low on-resistance transmission gate.
This is valid when reset is not asserted. If CEIN is high
when reset is asserted, CEOUT remains high regard-
less of any subsequent transitions on CEIN during the
reset event.
If CEIN is low when reset is asserted, CEOUT is held
low for 12µs to allow completion of the read/write oper-
Functional Diagram
