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MAX6314US28D4-T-MAX6314US29D1-T-MAX6314US30D4-T-MAX6314US31D2-T-MAX6314US46D2-T-MAX6314US47D2-T
68HC11/Bidirectional-Compatible レP Reset Circuit
General DescriptionThe MAX6314 low-power CMOS microprocessor (µP)
supervisory circuit is designed to monitor power
supplies in µP and digital systems. The MAX6314’s
RESEToutput is bidirectional, allowing it to be directly
connected to µPs with bidirectional reset inputs, such
as the 68HC11. It provides excellent circuit reliability
and low cost by eliminating external components and
adjustments. The MAX6314 also provides a debounced
manual reset input.
This device performs a single function: it asserts a reset
signal whenever the VCCsupply voltage falls below a
preset threshold or whenever manual reset is
asserted. Reset remains asserted for an internally pro-
grammed interval (reset timeout period) after VCChas
risen above the reset threshold or manual reset is
deasserted.
The MAX6314 comes with factory-trimmed reset
threshold voltages in 100mV increments from 2.5V
to 5V. Preset timeout periods of 1ms, 20ms, 140ms,
and 1120ms (minimum) are also available. The device
comes in a SOT143 package.
For a µP supervisor with an open-drain reset pin, see
the MAX6315 data sheet.
________________________ApplicationsComputers
Controllers
Intelligent Instruments
Critical µP and µC Power Monitoring
Portable/Battery-Powered Equipment
FeaturesSmall SOT143 PackageRESET
Output Simplifies Interface to
Bidirectional Reset I/OsPrecision Factory-Set VCCReset Thresholds:
100mV Increments from 2.5V to 5V±1.8% Reset Threshold Accuracy at TA= +25°C±2.5% Reset Threshold Accuracy Over Temp.Four Reset Timeout Periods Available:
1ms, 20ms, 140ms, or 1120ms (minimum) Immune to Short VCCTransients5µA Supply CurrentPin-Compatible with MAX811
MAX6314*
68HC11/Bidirectional-Compatible
µP Reset Circuit
Pin Configurationypical Operating Circuit19-1090; Rev 1; 1/99
MAX6314
68HC11/Bidirectional-Compatible
µP Reset Circuit
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= +2.5V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:The MAX6314 monitors VCCthrough an internal, factory-trimmed voltage divider that programs the nominal reset threshold.
Factory-trimmed reset thresholds are available in 100mV increments from 2.5V to 5V (see Ordering and Marking Information).
Note 2:This is the minimum time RESETmust be held low by an external pull-down source to set the active pull-up flip-flop.
VCC........................................................................-0.3V to +6.0V
All Other Pins..............................................-0.3V to (VCC+ 0.3V)
Input Current (VCC).............................................................20mA
Output Current (RESET)......................................................20mA
Rate of Rise (VCC)...........................................................100V/µs
Continuous Power Dissipation (TA= +70°C)
SOT143 (derate 4mW/°C above +70°C).......................320mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX6314
68HC11/Bidirectional-Compatible
µP Reset Circuit
__________________________________________Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
MAX6314
68HC11/Bidirectional-Compatible
µP Reset Circuit
______________________________________________________________Pin Description
MAX6314
68HC11/Bidirectional-Compatible
µP Reset Circuit
_______________Detailed DescriptionThe MAX6314 has a reset output consisting of a 4.7kΩ
pull-up resistor in parallel with a P-channel transistor
and an N-channel pull down (Figure 1), allowing this IC
to directly interface with microprocessors (µPs) that
have bidirectional reset pins (see the Reset Output
section).
Reset OutputA µP’s reset input starts the µP in a known state. The
MAX6314 asserts reset to prevent code-execution
errors during power-up, power-down, or brownout
conditions. RESETis guaranteed to be a logic low for
VCC> 1V (see the Electrical Characteristics). Once
VCCexceeds the reset threshold, the internal timer
keeps reset asserted for the reset timeout period (tRP);
after this interval RESETgoes high. If a brownout condi-
tion occurs (monitored voltage dips below its pro-
grammed reset threshold), RESETgoes low. Any time
VCCdips below the reset threshold, the internal timer
resets to zero and RESETgoes low. The internal timer
starts when VCCreturns above the reset threshold, andRESETremains low for the reset timeout period.
The MAX6314’s RESEToutput is designed to interface
with µPs that have bidirectional reset pins, such as the
Motorola 68HC11. Like an open-drain output, the
MAX6314 allows the µP or other devices to pull RESET
low and assert a reset condition. However, unlike a
standard open-drain output, it includes the commonly
specified 4.7kΩpull-up resistor with a P-channel active
pull-up in parallel.
This configuration allows the MAX6314 to solve a prob-
lem associated with µPs that have bidirectional reset
pins in systems where several devices connect to
RESET. These µPs can often determine if a reset was
asserted by an external device (i.e., the supervisor IC)
or by the µP itself (due to a watchdog fault, clock error,
or other source), and then jump to a vector appropriate
for the source of the reset. However, if the µP does
assert reset, it does not retain the information, but must
determine the cause after the reset has occurred.
The following procedure describes how this is done
with the Motorola 68HC11. In all cases of reset, the µP
pulls RESETlow for about four E-clock cycles. It then
releases RESET, waits for two E-clock cycles, then
checks RESET’s state. If RESETis still low, the µP con-
cludes that the source of the reset was external and,
when RESETeventually reaches the high state, jumps
to the normal reset vector. In this case, stored state
information is erased and processing begins from
scratch. If, on the other hand, RESETis high after the
two E-clock cycle delay, the processor knows that it
caused the reset itself and can jump to a different vec-
tor and use stored state information to determine what
caused the reset.
The problem occurs with faster µPs; two E-clock cycles
is only 500ns at 4MHz. When there are several devices
on the reset line, the input capacitance and stray
capacitance can prevent RESETfrom reaching the
logic-high state (0.8 x VCC) in the allowed time if only a
passive pull-up resistor is used. In this case, all resets
will be interpreted as external. The µP is guaranteed to
sink only 1.6mA, so the rise time cannot be much
reduced by decreasing the recommended 4.7kΩ
pull-up resistance.
The MAX6314 solves this problem by including a pull-
up transistor in parallel with the recommended 4.7kΩ
resistor (Figure 1). The pull-up resistor holds the output
high until RESETis forced low by the µP reset I/O, or by
the MAX6314 itself. Once RESETgoes below 0.5V, a
comparator sets the transition edge flip-flop, indicating
that the next transition for RESETwill be low to high. As
soon as RESETis released, the 4.7kΩresistor pulls
RESETup toward VCC. When RESETrises above 0.5V,
the active P-channel pull-up turns on for the 2µs
duration of the one-shot. The parallel combination of the
4.7kΩpull-up and the P-channel transistor on-
resistance quickly charges stray capacitance on the
reset line, allowing RESETto transition low to high with-
in the required two E-clock period, even with several
devices on the reset line (Figure 2). Once the one-shot
times out, the P-channel transistor turns off. This
process occurs regardless of whether the reset was
caused by VCCdipping below the reset threshold, MR
being asserted, or the µP or other device asserting
RESET. Because the MAX6314 includes the standard
4.7kΩpull-up resistor, no external pull-up resistor is
required. To minimize current consumption, the internal
pull-up resistor is disconnected whenever the MAX6314
asserts RESET.
Manual Reset InputMany µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic low on MR
asserts reset. Reset remains asserted while MRis low,
and for the reset active timeout period after MRreturns
high. To minimize current consumption, the internal
4.7kΩpull-up resistor on RESETis disconnected
whenever RESETis asserted.
MAX6314
68HC11/Bidirectional-Compatible
µP Reset Circuithas an internal 63kΩpull-up resistor, so it can be
left open if not used. Connect a normally open momen-
tary switch from MRto GND to create a manual reset
function; external debounce circuitry is not required. Ifis driven from long cables or if the device is used in
a noisy environment, connecting a 0.1µF capacitor fromto ground provides additional noise immunity.
__________Applications Information
Negative-Going VCCTransientsIn addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these devices
are relatively immune to short-duration negative-going
transients (glitches). The Typical Operating Character-
isticsshow the Maximum Transient Duration vs. Reset
Threshold Overdrive, for which reset pulses are not
generated. The graph was produced using negative-
going pulses, starting at VRSTmax and ending below
the programmed reset threshold by the magnitude
indicated (reset threshold overdrive). The graph shows
the maximum pulse width that a negative-going VCC
transient may typically have without causing a reset
pulse to be issued. As the amplitude of the transient
increases (i.e., goes farther below the reset threshold),
the maximum allowable pulse width decreases. A 0.1µF
bypass capacitor mounted close to VCCprovides addi-
tional transient immunity.
Ensuring a Valid RESETOutput
Down to VCC= 0VWhen VCCfalls below 1V, RESETno longer sinks
current—it becomes an open circuit. Therefore, high-
impedance CMOS-logic inputs connected to RESET
can drift to undetermined voltages. This presents no
problem in most applications, since most µP and other
circuitry is inoperative with VCCbelow 1V. However, in
applications where RESETmust be valid down to
VCC = 0V, adding a pull-down resistor to RESETwill
cause any stray leakage currents to flow to ground,
holding RESETlow (Figure 3). R1’s value is not critical;
100kΩis large enough not to load RESETand small
enough to pull RESETto ground.
Figure 2. MAX6314 Supports Additional Devices on the Reset Bus
Figure 3. RESETValid to VCC= Ground Circuit
