MAX5940DESA+T ,IEEE 802.3af PD Interface Controller for Power-Over-EthernetELECTRICAL CHARACTERISTICS(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = V , T = ..
MAX5941ACSE ,IEEE 802.3af-Compliant Power-Over-Ethernet Interface/PWM Controller for Power DevicesFeaturesThe MAX5941A/MAX5941B integrate a complete power Powered Device InterfaceIC for powered de ..
MAX5941BCSE ,IEEE 802.3af-Compliant Power-Over-Ethernet Interface/PWM Controller for Power DevicesApplicationsMAX5941BCSE 0°C to +70°C 16 SO 50IP PhonesWireless Access NodesPin ConfigurationInterne ..
MAX5941BESE ,IEEE 802.3af-Compliant Power-Over-Ethernet Interface/PWM Controller for Power DevicesELECTRICAL CHARACTERISTICS (continued)(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OPEN, V- tied t ..
MAX5941BESE+T ,IEEE 802.3af-Compliant Power-Over-Ethernet Interface/PWM Controller for Power DevicesFeaturesThe MAX5941A/MAX5941B integrate a complete power♦ Powered Device InterfaceIC for powered de ..
MAX5942AESE ,IEEE 802.3af power-over-ethernet interface/PWM controller for power deviceFeaturesThe MAX5942A/MAX5942B integrate a complete power Powered Device InterfaceIC for powered d ..
MAZ8130-H ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8130L ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8130-L ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8130-M ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8150G ,Silicon planar typeFeatures Package Extremely low noise voltage caused from the diode (2.4 V to Code 39V, 1/3 to 1 ..
MAZ8150-H ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAX5940AESA+-MAX5940BESA+-MAX5940CESA+-MAX5940DESA+T
IEEE 802.3af PD Interface Controller for Power-Over-Ethernet
General DescriptionThe MAX5940A/MAX5940B/MAX5940C/MAX5940D pro-
vide complete interface function for a powered device
(PD) to comply with the IEEE 802.3af standard in a
power-over-ethernet system. MAX5940A/MAX5940B/
MAX5940C/MAX5940D provide the PD with a detection
signature, a classification signature, and an integrated
isolation switch with programmable inrush current control.
These devices also feature power-mode undervoltage
lockout (UVLO) with wide hysteresis and power-
good outputs. The MAX5940A/MAX5940B are available
with an absolute maximum rating of 80V and the
MAX5940C/MAX5940D are rated for an absolute maxi-
mum rating of 90V.
An integrated MOSFET provides PD isolation during
detection and classification. All devices guarantee a leak-
age current offset of less than 10µA during the detection
phase. A programmable current limit prevents high inrush
current during power-on. The device features power-
mode UVLO with wide hysteresis and long deglitch time
to compensate for twisted-pair cable resistive drop and to
assure glitch-free transition between detection, classifica-
tion, and power-on/-off phases.
The MAX5940A/MAX5940C provide an active-high
(PGOOD) open-drain output and a fixed UVLO threshold.
The MAX5940B/MAX5940D provide both active-high
(PGOOD) and active-low (PGOOD)outputs and have an
adjustable UVLO threshold with the default value compli-
ant to the 802.3af standard. All devices are designed to
work with or without an external diode bridge.
The MAX5940A/MAX5940B/MAX5940C/MAX5940D are
available in 8-pin SO packages and are rated over the
extended temperature range of -40°C to +85°C.
ApplicationsIP PhonesSecurity Cameras
Wireless Access NodesIEEE 802.3af Power Devices
Computer Telephony
FeaturesFully Integrated IEEE 802.3af-Compliant PD
InterfacePD Detection and Programmable Classification
SignaturesLess than 10µA Leakage Current Offset During
DetectionIntegrated MOSFET For Isolation and Inrush
Current Limiting90V Absolute Maximum Rating
(MAX5940C/MAX5940D)Gate Output Allows External Control of the
Internal Isolation MOSFETProgrammable Inrush Current ControlProgrammable Undervoltage Lockout
(MAX5940B/MAX5940D Only)Wide UVLO Hysteresis Accommodates Twisted-
Pair Cable Voltage DropPGOOD/PGOODOutputs to Enable Downstream
DC-DC Converters-40°C to +85°C Operating Temperature Range
MAX5940A/MAX5940B/MAX5940C/MAX5940D
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Ordering Information60V68nF
GND
VEE
GATE
RCLASS
PGOOD
DC-DC CONVERTERGND
-48V
RCL
*OPTIONAL.
GND
LOAD
VREG
D1*
OUT5
COUT
CGATE
RDISC
25.5kΩ
SS_SHDN
MAX5014
MAX5940A
MAX5940C
D2*
Typical Operating Circuits19-2991; Rev 2; 2/06
EVALUATION KIT
AVAILABLE
Pin Configurations appear at end of data sheet.
PARTTEMP RANGEPIN-
PACKAGEUVLOMAX5940AESA-40°C to +85°C8 SOFixed
MAX5940BESA-40°C to +85°C8 SOAdjustable
MAX5940CESA-40°C to +85°C8 SOFixed
MAX5940DESA-40°C to +85°C8 SOAdjustable
Typical Operating Circuits continued at end of data sheet.
MAX5940A/MAX5940B/MAX5940C/MAX5940D
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VIN= (GND - VEE) = 48V, GATE = PGOOD= PGOOD = OUT = OPEN, UVLO = VEE, TA= -40°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages are referenced to VEE, unless otherwise noted.)
GND (MAX5940A/MAX5940B)...............................-0.3V to +80V
GND (MAX5940C/MAX5940D)...............................-0.3V to +90V
OUT, PGOOD...........................................-0.3V to (GND + 0.3V)
RCLASS, GATE......................................................-0.3V to +12V
UVLO........................................................................-0.3V to +8V
PGOOD to OUT.........................................-0.3V to (GND + 0.3V)
Maximum Input/Output Current (continuous)
OUT to VEE...................................................................500mA
GND, RCLASS to VEE.....................................................70mA
UVLO, PGOOD, PGOOD to VEE.....................................20mA
GATE to VEE....................................................................80mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SO (derate 5.9mW/°C above +70°C)..................470mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) ................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DETECTION MODEInput Offset Current (Note 2)IOFFSETVIN = 1.4V to 10.1V10µA
Effective Differential Input
Resistance (Note 3)dRVIN = 1.4V up to 10.1V with 1V step,
OUT = PGOOD = GND550kΩ
CLASSIFICATION MODEClassification Current Turn-Off
Threshold (Note 4)VTH,CLSSVIN rising20.821.822.5V
Class 0, RCL = 10kΩ02
Class 1, RCL = 732Ω9.1711.83
Class 2, RCL = 392Ω17.2919.71
Class 3, RCL = 255Ω26.4529.55
Classification Current (Notes 5, 6)ICLASS
VIN = 12.6V to
20V, RDISC =
25.5kΩ
Class 4, RCL = 178Ω36.641.4
POWER MODEOperating Supply VoltageVINVIN = (GND - VEE)67V
Operating Supply CurrentIINMeasure at GND, not including RDISC0.41mA
MAX5940A/MAX5940C34.335.436.6
Default Power Turn-On VoltageVUVLO, ONVIN increasingMAX5940B/MAX5940D,
UVLO = VEE37.438.639.9V
Default Power Turn-Off VoltageVUVLO, OFFVIN decreasing, UVLO = VEE for
MAX5940B/MAX5940D30V
MAX5940A/MAX5940C4.2Default Power Turn-On/Off
Hysteresis
VHYST,
UVLOMAX5940B/MAX5940D, UVLO = VEE7.4V
External UVLO Programming
RangeVIN,EXSet UVLO externally (MAX5940B/
MAX5940D only) (Note 7)1267V
UVLO External Reference VoltageVREF, UVLO2.4002.4602.522V
UVLO External Reference Voltage
HysteresisHYSTRatio to VREF,UVLO19.22020.9%
UVLO Bias CurrentIUVLOUVLO = 2.460V-1.5+1.5µA
MAX5940A/MAX5940B/MAX5940C/MAX5940D
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Note 1:All min/max limits are production tested at +85°C. Limits at +25°C and -40°C are guaranteed by design.
Note 2:The input offset current is illustrated in Figure 1.
Note 3:Effective differential input resistance is defined as the differential resistance between GND and VEEwithout any external
resistance. See Figure 1.
Note 4: Classification current is turned off whenever the IC is in power mode.
Note 5:See Table2 in the PD Classification Modesection. RDISCand RCLmust be ±1%, 100ppm or better. ICLASSincludes the IC
bias current and the current drawn by RDISC.
Note 6:See the Thermal Dissipation sectionfor details.
Note 7:When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ(±1%), the turn-
on threshold set-point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when VINis at the maximum voltage (MAX5940B only).
Note 8:When the UVLO input voltage is below VTH,G,UVLO,the MAX5940B sets the UVLO threshold internally.
Note 9:An input voltage or VUVLOglitch below their respective thresholds shorter than or equal to tOFF_DLYdoes not cause the
MAX5940A/MAX5940B/MAX5940C/MAX5940D to exit power-on mode (as long as the input voltage remains above an opera-
ble voltage level of 12V).
Note 10:Guaranteed by design.
Note 11:PGOOD references to OUT while PGOODreferences to VEE.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSUVLO Input Ground Sense
Threshold (Note 8)VTH,G,UVLO50440mV
UVLO Input Ground Sense Glitch
RejectionUVLO = VEE7µs
Power Turn-Off Voltage,
Undervoltage Lockout Deglitch
Time (Note 9)
tOFF_DLYVIN, VUVLO falling0.32ms
TA = +25°C
(Note 10)0.61.1
Isolation Switch N-Channel
MOSFET On-ResistanceRON
Output current =
300mA, VGATE = 6V,
measured between
OUT and VEETA = +85°C0.81.5
Isolation Switch N-Channel
MOSFET Off-Threshold VoltageVGSTHOUT = GND, VGATE - VEE, output current
< 1µA0.5V
GATE Pulldown Switch ResistanceRGPower-off mode, VIN = 12V,
UVLO = VEE for MAX5940B3880Ω
GATE Charging CurrentIGVGATE = 2V51015µA
GATE High VoltageVGATEIGATE = 1µA5.595.765.93V
VOUT - VEE, |VOUT - VEE| decreasing,
VGATE = 5.75V1.161.231.31VPGOOD, PGOOD Assertion VOUT
ThresholdVOUTEN
Hysteresis70mV
(GATE - VEE) increasing, OUT = VEE4.624.764.91VPGOOD, PGOOD Assertion VGATE
ThresholdVGSENHysteresis80mV
PGOOD, PGOOD Output Low
Voltage (Note 11)VOLDCDCISINK = 2mA; for PGOOD, OUT ≤
(GND - 5V)0.4V
PGOOD Leakage Current (Note 11)GATE = high, GND - VOUT = 67V1µA
PGOOD Leakage Current (Note 11)GATE = VEE, PGOOD - VEE = 67V1µA
ELECTRICAL CHARACTERISTICS (continued)(VIN= (GND - VEE) = 48V, GATE = PGOOD= PGOOD = OUT = OPEN, UVLO = VEE, TA= -40°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
MAX5940A/MAX5940B/MAX5940C/MAX5940D
IEEE 802.3af PD Interface Controller
For Power-Over-EthernetIIN
IINi + 1
IINi
IOFFSET
dRiVINiVINi + 1
IOFFSET ≅ IINi - VINi
dRi
dRi ≅ (VINi + 1 - VINi) = 1V (IINi + 1 - IINi) (IINi + 1 - IINi)
VIN
Figure1. Effective Differential Input Resistance/Offset Current
DETECTION CURRENT vs. INPUT VOLTAGEMAX5940A/B toc01
INPUT VOLTAGE (V)
DETECTION CURRENT (mA)642
RDISC = 25.5kΩ
IIN + IRDISC
CLASSIFICATION CURRENT
vs. INPUT VOLTAGEMAX5940A/B toc02
INPUT VOLTAGE (V)
CLASSIFICATION CURRENT (mA)2015105
CLASS 0
CLASS 1
CLASS 2
CLASS 3
CLASS 4
EFFECTIVE DIFFERENTIAL INPUT
RESISTANCE vs. INPUT VOLTAGEMAX5940A/B toc03
INPUT VOLTAGE (V)
EFFECTIVE DIFFERENTIAL INPUT RESISTANCE (M8642
INPUT OFFSET CURRENT
vs. INPUT VOLTAGE
MAX5940A/B toc04
INPUT VOLTAGE (V)
INPUT OFFSET CURRENT (753
NORMALIZED UVLO
vs. TEMPERATURE
MAX5940A/B toc05
TEMPERATURE (°C)
NORMALIZED UVLO3510-15
UVLO = VEE
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENTMAX5940A/B toc06
ISINK (mA)
PGOOD
(mV)105
Typical Operating Characteristics
(VIN= (GND - VEE) = 48V, GATE = PGOOD= PGOOD = OUT = OPEN, UVLO = VEE(MAX5940B), TA= -40°C to +85°C. Typical values
are at TA= +25°C. All voltages are referenced to VEE, unless otherwise noted.)
MAX5940A/MAX5940B/MAX5940C/MAX5940D
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENTMAX5940A/B toc07
ISINK (mA)
PGOOD
(mV)105
OUT LEAKAGE CURRENT
vs. TEMPERATURE
MAX5940A/B toc08
TEMPERATURE (°C)
OUT LEAKAGE CURRENT (nA)3510-15
VOUT = 67V
INRUSH CURRENT CONTROL (VIN = 12V)MAX5940A/B toc09
1ms/div
VGATE
5V/div
IINRUSH
100mA/div
VOUT TO VEE
10V/div
PGOOD10V/div
INRUSH CURRENT CONTROL (VIN = 48V)MAX5940A/B toc10
2ms/div
VGATE
5V/div
IINRUSH
100mA/div
VOUT TO VEE
50V/div
PGOOD
50V/div
INRUSH CURRENT CONTROL (VIN = 67V)MAX5940A/B toc11
2ms/div
VGATE
5V/div
IINRUSH
100mA/div
VOUT TO VEE
50V/div
PGOOD
50V/div
ypical Operating Characteristics (continued)(VIN= (GND - VEE) = 48V, GATE = PGOOD= PGOOD = OUT = OPEN, UVLO = VEE(MAX5940B), TA= -40°C to +85°C. Typical values
are at TA= +25°C. All voltages are referenced to VEE, unless otherwise noted.)
MAX5940A/MAX5940B/MAX5940C/MAX5940D
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Pin Description
PIN
MAX5940A/
MAX5940C
MAX5940B/
MAX5940D
NAMEFUNCTION1, 7—N.C.No Connection. Not internally connected.UVLO
Undervoltage Lockout Programming Input for Power Mode. When UVLO is above its
threshold, the device enters power mode. Connect UVLO to VEE to use the default
undervoltage lockout threshold. Connect UVLO to an external resistor-divider to define a
threshold externally. The series resistance value of the external resistors must add to 25.5kΩ
(±1%) and replaces the detection resistor. To keep the device in undervoltage lockout, pull
UVLO to between VTH,G,UVLO and VREF,UVLO.RCLASSClassification Setting. Add a resistor from RCLASS to VEE to set a PD class (see Tables 1
and 2).GATE
Gate of Internal N-Channel Power MOSFET. GATE sources 10µA when the device enters
power mode. Connect an external 100V ceramic capacitor (CGATE) from GATE to OUT to
program the inrush current. Pull GATE to VEE to turn off the internal MOSFET. The detection
and classification functions operate normally when GATE is pulled to VEE.VEENegative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect
VEE to -48V.5OUTOutput Voltage. Drain of the integrated isolation N-channel power MOSFET.PGOOD
Power-Good Indicator Output, Active-High, Open-Drain. PGOOD is referenced to OUT.
PGOOD goes high impedance when VOUT is within 1.2V of VEE and when GATE is 5V above
VEE. Otherwise, PGOOD is pulled to OUT (given that VOUT is at least 5V below GND).
Connect PGOOD to the ON pin of a downstream DC-DC converter.PGOOD
Power-Good Indicator Output, Active-Low, Open-Drain. PGOOD is referenced to VEE.
PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and when GATE is 5V above VEE.
Otherwise, PGOOD goes high impedance. Connect PGOOD to the ON pin of a downstream
DC-DC converter.8GNDGround. GND is the positive input terminal.
Detailed Description
Operating ModesThe PD front-end section of the MAX5940_ operates in 3
different modes, PD detection signature, PD classifica-
tion, and PD power, depending on its input voltage (VIN=
GND - VEE). All voltage thresholds are designed to oper-
ate with or without the optional diode bridge while still
complying with the IEEE 802.3af standard (see Figure 4).
Detection Mode (1.4V ≤VIN≤
10.1V)In detection mode, the power source equipment (PSE)
applies two voltages on VINin the range of 1.4V to 10.1V
(1V step minimum), and then records the current mea-
surements at the two points. The PSE then computes
ΔV/ΔI to ensure the presence of the 25.5kΩsignature
resistor. In this mode, most of the MAX5940_ internal cir-
cuitry is off and the offset current is less than 10µA.
If the voltage applied to the PD is reversed, install pro-
tection diodes on the input terminal to prevent internal
damage to the MAX5940_ (see the Typical Application
Circuits). Since the PSE uses a slope technique (ΔV/ΔI)
to calculate the signature resistance, the DC offset due
to the protection diodes is subtracted and does not
affect the detection process.
Classification Mode (12.6V ≤VIN≤
20V)In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD.
This allows the PSE to efficiently manage power distri-
bution. The IEEE 802.3af standard defines five different
classes as shown in Table 1. An external resistor (RCL)
connected from RCLASS to VEEsets the classification
current.
The PSE determines the class of a PD by applying a volt-
age at the PD input and measures the current sourced
out of the PSE. When the PSE applies a voltage between
12.6V and 20V, the MAX5940_ exhibit a current charac-
teristic with values indicated in Table 2. The PSE uses the
classification current information to classify the power
requirement of the PD. The classification current includes
the current drawn by the 25.5kΩdetection signature
resistor and the supply current of the MAX5940_ so the
total current drawn by the PD is within the IEEE 802.3af
standard figures. The classification current is turned off
whenever the device is in power mode.
Power ModeDuring power mode, when VINrises above the under-
voltage lockout threshold (VUVLO,ON), the MAX5940_
gradually turn on the internal N-channel MOSFET Q1
(see Figure 2). The MAX5940_ charge the gate of Q1
with a constant current source (10µA, typ). The drain-
to-gate capacitance of Q1 limits the voltage rise rate at
the drain of the MOSFET, thereby limiting the inrush
current. To reduce the inrush current, add external
drain-to-gate capacitance (see the Inrush Current Limit
section). When the drain of Q1 is within 1.2V of its
source voltage and its gate-to-source voltage is above
5V, the MAX5940_ asserts the PGOOD/PGOODout-
puts. The MAX5940_ have a wide UVLO hysteresis and
turn-off deglitch time to compensate for the high
impedance of the twisted-pair cable.
Undervoltage LockoutThe MAX5940_ operate up to a 67V supply voltage with a
default UVLO turn-on (VUVLO,ON) set at 35V
(MAX5940A/MAX5940C) or 39V (MAX5940B/MAX5940D)
and a UVLO turn-off (VUVLO,OFF) set at 30V. The
MAX5940B/MAX5940D have an adjustable UVLO thresh-
old using a resistor-divider connected to UVLO (see
Figure 3). When the input voltage is above the UVLO
threshold, the IC is in power mode and the MOSFET is
on. When the input voltage goes below the UVLO thresh-
old for more than tOFF_DLY, the MOSFET turns off.
MAX5940A/MAX5940B/MAX5940C/MAX5940D
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
CLASSUSAGERCL (Ω)MAXIMUM POWER USED BY PD (W)Default10k0.44 to 12.95Optional7320.44 to 3.84Optional3923.84 to 6.49Optional2556.49 to 12.95Not Allowed178Reserved*
*Class 4 reserved for future use.
Table 1. PD Power Classification/RCLSelection
CLASS CURRENT SEEN AT VIN (mA)IEEE 802.3af PD CLASSIFICATION
CURRENT SPECIFICATION (mA)CLASSRCL (Ω)VIN* (V)
MINMAXMINMAX10k12.6 to 20020473212.6 to 209.1711.8391239212.6 to 2017.2919.71172025512.6 to 2026.4529.55263017812.6 to 2036.641.43644
*VINis measured across the MAX5940 input pins, which does not include the diode bridge voltage drop.
Table 2. Setting Classification Current
MAX5940A/MAX5940B/MAX5940C/MAX5940DTo adjust the UVLO threshold (MAX5940B/MAX5940D
only), connect an external resistor-divider from GND to
UVLO and from UVLO to VEE. Use the following equations
to calculate R1 and R2 for a desired UVLO threshold:
R1 = 25.5kΩ- R2
where VIN,EXis the desired UVLO threshold. Since the
resistor-divider replaces the 25.5kΩPD detection resis-
tor, ensure that the sum of R1 and R2 equals 25.5kΩ
±1%. When using the external resistor-divider, the
MAX5940B/MAX5940D has an external reference volt-
age hysteresis of 20% (typ). When UVLO is pro-
grammed externally, the turn-off threshold is 80% (typ)
of the new UVLO threshold.xV
REFUVLOEX
2255=.,
IEEE 802.3af PD Interface Controller
For Power-Over-EthernetGND
UVLO
GND
(UVLO)
( ) MAX5940B.
GATE
MAX5940B
MAX5940D
CLASSIFICATIONRCLASS
(PGOOD)
6.8VEN
REF
2.46V
200mV
VEE
VGATE
1.2V, REF
5V, REF
PGOOD
OUT
20%
Figure 2. Block Diagram
UVLO
GND
VEE
VIN = 12V TO 67V
MAX5940B
MAX5940D
Figure 3. Setting Undervoltage Lockout with an External
Resistor-Divider
