MAX5898EGK+D ,16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS InputsApplicationsBase Stations: 3G Multicarrier UMTS, CDMA, and GSMSimplified DiagramBroadband Wireless ..
MAX5900AAETT+T ,-100V, SOT23/TDFN, Simple Swapper Hot-Swap ControllersApplications Pin ConfigurationTelecom Line Cards Network Switches Requires No External Sense Resis ..
MAX5900AAEUT-T ,100 V, SOT23 simple swapper hot-swap controllerELECTRICAL CHARACTERISTICS(V = -9V to -100V, GND = 0, ON/OFF open circuit, T = -40°C to +85°C, unle ..
MAX5900ABEUT+ ,-100V, SOT23/TDFN, Simple Swapper Hot-Swap ControllersELECTRICAL CHARACTERISTICS(V = -9V to -100V, GND = 0, ON/OFF open circuit, T = -40°C to +85°C, unle ..
MAX5900ACEUT+T ,-100V, SOT23/TDFN, Simple Swapper Hot-Swap ControllersELECTRICAL CHARACTERISTICS(V = -9V to -100V, GND = 0, ON/OFF open circuit, T = -40°C to +85°C, unle ..
MAX5900ACEUT-T ,100 V, SOT23 simple swapper hot-swap controllerApplications Pin ConfigurationTelecom Line Cards Network Switches Requires No External Sense Resis ..
MAZ8056-H ,Silicon planar typeAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8056-L ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8056-M ,Silicon planar typeFeatures•Extremely low noise voltage caused from the diode (2.4V to 39V,1/3 to 1/10 of our conventi ..
MAZ8062 ,Small-signal deviceAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8062 ,Small-signal deviceElectrical Characteristics T = 25°C aParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8062-H ,Silicon planar typeelectrical characteristicsZ Zwithin part numbersReverse current I V ··············· Specified value ..
MAX5898EGK+D
16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS Inputs
General DescriptionThe MAX5898 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for high-
performance wideband, single- and multicarrier transmit
applications. The device integrates a selectable 2x/4x/8x
interpolating filter, a digital quadrature modulator, and
dual 16-bit, high-speed DACs on a single integrated cir-
cuit. At 30MHz output frequency and 500Msps update
rate, the in-band SFDR is 81dBc, while only consuming
1.2W. The device also delivers 71dB ACLR for four-
carrier WCDMA at a 61.44MHz output frequency.
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease recon-
struction filter requirements and enhance the passband
dynamic performance. Each channel includes offset and
gain programmability, allowing the user to calibrate out
local oscillator (LO) feedthrough and sideband suppres-
sion errors generated by analog quadrature modulators.
The MAX5898 features a fIM/ 4 digital image-reject
modulator. This modulator generates a quadrature-mod-
ulated IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at fIM/ 2 or fIM/ 4.
The MAX5898 features a standard LVDS interface for
low electromagnetic interference (EMI). Interleaved
data is applied through a single 16-bit bus. A 3.3V
SPI™ port is provided for mode configuration. The pro-
grammable modes include the selection of 2x/4x/8x
interpolating filters, fIM/ 2, fIM/ 4 or no digital quadra-
ture modulation with image rejection, individual channel
gain and offset adjustment, and offset binary or two’s-
complement data interface.
Compatible versions with CMOS interfaces and 12-, 14-,
and 16-bit resolutions are also available. Refer to the
MAX5893 data sheet for 12-bit CMOS, MAX5894 for 14-
bit CMOS, and the MAX5895 for 16-bit CMOS versions.
ApplicationsBase Stations: 3G Multicarrier UMTS, CDMA, and GSM
Broadband Wireless Transmitters
Broadband Cable Infrastructure
Instrumentation and Automatic Test Equipment (ATE)
Analog Quadrature Modulation Architectures
Features71dB ACLR at fOUT= 61.44MHz (Four-Carrier
WCDMA)Meets Multicarrier UMTS, cdma2000®, GSM
Spectral Masks (fOUT= 122MHz)Noise Spectral Density = -160dBFS/Hz at
fOUT= 16MHz90dBc SFDR at Low-IF Frequency (10MHz)88dBc SFDR at High-IF Frequency (50MHz)Low Power: 831mW (fCLK= 250MHz)User Programmable
Selectable 2x, 4x, or 8x Interpolating Filters
< 0.01dB Passband Ripple
> 95dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, fIM/ 2,
or fIM/ 4
Selectable Output Filter: Lowpass or Highpass
Per Channel Gain and Offset AdjustmentEV Kit Available (Order the MAX5898EVKIT)
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
PARTRESOLUTION
(BITS)
DAC UPDATE
RATE (Msps)
INPUT
LOGICMAX589312500CMOS
MAX589414500CMOS
MAX589516500CMOS
MAX589816500LVDS
PARTTEMP RANGEPIN-PACKAGEAX 5898E GK+ D-40°C to +85°C68 QFN-EP*
(10mm x 10mm)AX 5898E GK- D -40°C to +85°C68 QFN-EP*
(10mm x 10mm)
Selector Guide
Ordering InformationA SYNCHAND DEMUX
DACDATA PORT
DATACLK
OUTI
OUTQ
MODULA
TOR
INTERPOLA
TING
FIL
TERS1x/2x/4x
INTERPOLA
TING
FIL
TERS
DAC
Simplified Diagram19-3756; Rev 2; 8/10
SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of Telecommunications
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed paddle.
D = Dry pack
EVALUATION KIT
AVAILABLE
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ωdouble-terminated, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,
unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DVDD1.8, AVDD1.8to GND, DACREF..................-0.3V to +2.16V
AVDD3.3, AVCLK, DVDD3.3to GND, DACREF........-0.3V to +3.9V
DATACLKP, DATACLKN, D0P–D15P,
D0N–D15N, SELIQP, SELIQN to GND,
DACREF..........................................-0.3V to (DVDD1.8+ 0.3V)
CS, RESET, SCLK, DIN, DOUT to
GND, DACREF................................-0.3V to (DVDD3.3+ 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK+ 0.3V)
REFIO, FSADJ to GND, DACREF........-0.3V to (AVDD3.3+ 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF..................-1V to (AVDD3.3+ 0.3V)
DOUT, DATACLKP, DATACLKN Continuous Current..........8mA
Continuous Power Dissipation (TA= +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C)
(Note 1)...................................................................3333.3mW
Junction Temperature......................................................+150°C
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC PERFORMANCEResolution16Bits
Differential NonlinearityDNL±1LSB
Integral NonlinearityINL±3LSB
Offset ErrorOS-0.02±0.003+0.02%FS
Offset Drift±0.03ppm/°C
Gain ErrorGEFS(Note 3)-4±0.06+4%FS
Gain-Error Drift±110ppm/°C
Full-Scale Output CurrentIOUTFS(Note 3)220mA
Output Compliance-0.5+1.1V
Output ResistanceROUT1MΩ
Output CapacitanceCOUT5pF
DYNAMIC PERFORMANCEMaximum Clock FrequencyfCLK500MHz
Minimum Clock FrequencyfCLK10MHz
Maximum DAC Update RatefDACfDAC = fCLK or fDAC = fCLK / 2500Msps
Minimum DAC Update RatefDACfDAC = fCLK or fDAC = fCLK / 210Msps
Maximum Data Clock FrequencyfDATACLKInterleaved data250MHz
Maximum Input Data RatefDATAPer channel125MWps
No interpolation-156
2x interpolation-157
fDATA = 125Mwps,
fOUT = 16MHz, fOFFSET
= 10MHz, -12dBFS4x interpolation-157Noise Spectral Density
fDATA = 125Mwps,
fOUT = 16MHz, fOFFSET
4x interpolation-154
dBFS/
Note 1:Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ωdouble-terminated, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,
unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfOUT = 10MHz90
fOUT = 30MHz84
fDATA = 125Mwps,
interpolation off,
-0.1dBFSfOUT = 50MHz77
fOUT = 10MHz7989
fOUT = 30MHz83
fDATA = 125Mwps,
2x interpolation,
-0.1dBFSfOUT = 50MHz92
fOUT = 10MHz89
fOUT = 30MHz83
In-Band SFDR
(DC to fDATA / 2)SFDR
fDATA = 125Mwps,
4x interpolation,
-0.1dBFSfOUT = 50MHz89
dBc
No interpolation-96
2x interpolation-99
fDATA = 125Mwps,
fOUT1 = 9MHz, fOUT2 =
10MHz, -6.1dBFS4x interpolation-95
2x interpolation,
fIM / 4 complex
modulation
-81fDATA = 125Mwps,
fOUT1 = 79MHz,
fOUT2 = 80MHz,
-6.1dBFS4x interpolation,
fIM / 4 complex
modulation
fDATA = 62.5Mwps,
fOUT1 = 9MHz, fOUT2 =
10MHz, -6.1dBFS
8x interpolation-94
fDATA = 62.5Mwps,
fOUT1 = 69MHz, fOUT2
= 70MHz, -6.1dBFS
8x interpolation,
fIM / 4 complex
modulation
Two-Tone IMDTTIMD
fDATA = 62.5Mwps,
fOUT1 = 179MHz, fOUT2
= 180MHz, -6.1dBFS
8x, highpass
interpolation,
fIM / 4 complex
modulation
dBc
Four-Tone IMDFTIMD
fDATA = 125Mwps, fOUT spaced 1MHz
apart from 32MHz, -12dBFS, 2x
interpolation
-89dBc
4x interpolation79fDATA = 61.44Mwps,
fOUT = baseband8x interpolation79
fDATA = 122.88Mwps,
fOUT = 61.44MHz
2x interpolation,
fIM / 4 complex
modulationACLR for WCDMA
(Note 4)ACLR
fDATA = 122.88Mwps,
fOUT = 122.88MHz
4x interpolation,
fIM / 4 complex
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ωdouble-terminated, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,
unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOutput Propagation DelaytPD1x interpolation (Note 5)2.9ns
Output Rise TimetRISE10% to 90% (Note 6)0.75ns
Output Fall TimetFALL10% to 90% (Note 6)1ns
Output Settling TimeTo 0.5% (Note 6)11ns
Output Bandwidth-1dB bandwidth (Note 7)240MHz
Passband WidthRipple < -0.01dB0.4 x
fDATA
0.604 x fDATA, 2x interpolation100
0.604 x fDATA, 4x interpolation100Stopband Rejection
0.604 x fDATA, 8x interpolation100
1x interpolation22
2x interpolation70
4x interpolation146Data Latency
8x interpolation311
Clock
Cycles
DAC INTERCHANNEL MATCHINGGain MatchΔGainfOUT = DC - 80MHz, IOUTFS = 20mA±0.1dB
Gain-Match TempcoΔGain/°CIOUTFS = 20mA±0.02ppm/°C
Phase MatchΔPhasefOUT = 60MHz, IOUTFS = 20mA±0.13Deg
Phase-Match TempcoΔPhase/°CIOUTFS = 20mA±0.006Deg/°C
DC Gain MatchIOUTFS = 20mA (Note 3)-0.2±0.04+0.2dB
CrosstalkfOUT = 50MHz, fDAC = 250MHz-95dB
REFERENCEReference Input Range0.121.32V
Reference Output VoltageVREFIOInternal reference1.141.21.28V
Reference Input ResistanceRREFIO10kΩ
Reference Voltage Drift±50ppm/°C
CMOS LOGIC INPUTS (SCLK, CS, RESET, DIN)Input High VoltageVIH0.7 x
DVDD3.3V
Input Low VoltageVIL0.3 x
DVDD3.3V
Input CurrentIIN-10±0.1+10µA
Input CapacitanceCIN3pF
CMOS LOGIC OUTPUT (DOUT)Output High VoltageVOHILOAD = 200µA0.8 x
DVDD3.3V
Output Low VoltageVOLISINK = 200µA0.2 x
DVDD3.3V
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSRise/Fall TimeCLOAD = 10pF, 20% to 80%1.5ns
LVDS LOGIC INPUTS (D15P–D0P, D15N–D0N, SELIQP, SELIQN)Differential Input Logic HighVIH100mV
Differential Input Logic LowVIL-100mV
Input Common-Mode VoltageVICM1.1251.251.375V
Differential Input ResistanceRIN110Ω
Input CapacitanceCIN2.5pF
LVDS CLOCK INPUT/OUTPUT (DATACLKP, DATACLKN)Differential Input Amplitude HighVIH250mV
Differential Input Amplitude LowVIL-250mVi ffer enti al Outp ut Am p l i tud e H i g hVOHRLOAD = 100Ω d i ffer enti al ( N ote 3) 250340mV
Differential Output Amplitude LowVOLRLOAD = 100Ω d i ffer enti al ( N ote 3) -340-250mV
Output Common-Mode VoltageVOCM1.25V
Output Rise/Fall TimeRLOAD = 100Ω d i ffer enti al , CLOAD = 8pF,
20% to 80%0.9ns
CLOCK INPUTS (CLKP, CLKN) (Note 8)Sine-wave input> 1.5Differential Input Voltage SwingVDIFFSquare-wave input> 0.5VP-P
Differential Input Slew Rate> 100V/µs
Common-Mode VoltageVCOMAC-coupledAVCLK /V
Differential Input ResistanceRCLK5kΩ
Differential Input CapacitanceCCLK5pF
Minimum Clock Duty Cycle45%
Maximum Clock Duty Cycle55%
CLKP/CLKN, DATACLK TIMING (Figure 4) (Note 9)CLK to DATACLK DelaytDDATACLK output mode1.4ns
Data Hold TimetDH1.65ns
Data Setup TimetDS-0.65ns
SERIAL-PORT INTERFACE TIMING (Figure 3) (Note 9)SCLK FrequencyfSCLK10MHz
CS Setup TimetSS2.5ns
Input Hold TimetSDH0ns
Input Setup TimetSDS4.5ns
Data Valid DurationtSDV6.516.5ns
POWER SUPPLIESDigital Supply VoltageDVDD1.81.711.81.89V
Digital I/O Supply VoltageDVDD3.33.03.33.6V
ELECTRICAL CHARACTERISTICS (continued)(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ωdouble-terminated, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,
unless otherwise noted.) (Note 2)
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSClock Supply VoltageAVCLK3.1353.33.465V
AVDD3.33.1353.33.465Analog Supply VoltageAVDD1.81.711.81.89V
IAVDD3.3fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz111130
Analog Supply Current
IAVDD1.8fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz2732
Digital Supply CurrentIDVDD1.8fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz229250mA
Digital I/O Supply CurrentIDVDD3.3fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz912mA
Clock Supply CurrentIAVCLKfCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz2.34mA
Total Power DissipationPTOTALfCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz831mW
AVDD3.3530
AVDD1.81
DVDD1.826
DVDD3.3350
Power-Down Current
All I/O are static high or
low, bit 2 to bit 4 of
address 00h are set high
AVCLK2
AVDD3.3 Power-Supply Rejection
RatioPSRRA(Note 10)0.125%FS/V
ELECTRICAL CHARACTERISTICS (continued)(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ωdouble-terminated, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C,
unless otherwise noted.) (Note 2)
Note 2:All specifications are 100% tested at TA≥+25°C. Specifications at TA< +25°C are guaranteed by design and characterization.
Note 3:Specification is 100% production tested at TA≥+25°C.
Note 4:3.84MHz bandwidth, single carrier.
Note 5:Excludes data latency.
Note 6:Measured single-ended into a 50Ωload.
Note 7:Excludes sin(x)/x rolloff.
Note 8:Differential voltage swing defined as IVPI+ IVNI.
Note 9:Guaranteed by design and characterization.
Note 10:Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.V(CLKN)
V(CLKP)VN
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, NO INTERPOLATIONMAX5898 toc01
OUTPUT FREQUENCY (MHz)
SFDR (dBc)20304050
-0.1dBFS
-6dBFS
-12dBFS
-0.1dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 2x INTERPOLATIONMAX5898 toc02
OUTPUT FREQUENCY (MHz)
SFDR (dBc)302010
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
-0.1dBFS
-12dBFS-6dBFS
0UT-OF-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 2x INTERPOLATIONMAX5898 toc03
OUTPUT FREQUENCY (MHz)
SFDR (dBc)302010
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
-6dBFS-12dBFS
-0.1dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 2x INTERPOLATIONMAX5898 toc04
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
-0.1dBFS-6dBFS
-12dBFS-0.1dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATIONMAX5898 toc05
OUTPUT FREQUENCY (MHz)
SFDR (dBc)302010
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
-12dBFS
-0.1dBFS-6dBFS
OUT-OF-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATIONMAX5898 toc06
OUTPUT FREQUENCY (MHz)
SFDR (dBc)302010
SPURS MEASURED BETWEEN
62.5MHz AND 250MHz
-0.1dBFS
-6dBFS
-12dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATIONMAX5898 toc07
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
-0.1dBFS
-6dBFS
-12dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATIONMAX5898 toc08
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
125MHz AND 187.5MHz
-0.1dBFS-12dBFS
-6dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
fDATA = 125Mwps, NO INTERPOLATIONMAX5898 toc09
CENTER FREQUENCY (MHz)
TWO-TONE IMD (dBc)20253035
-6dBFS
-9dBFS
-12dBFS
1MHz CARRIER SPACING
Typical Operating Characteristics(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, DATACLK output mode, external reference, VREFIO= +1.25V,
RLOAD= 50Ωdouble-terminated, IOUTFS= 20mA, TA= +25°C, unless otherwise noted.)
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
TWO-TONE IMD vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 2x INTERPOLATIONMAX5898 toc10
CENTER FREQUENCY (MHz)
TWO-TONE IMD (dBc)40557085
1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz
-12dBFS
-6dBFS
-9dBFS
-6dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATIONMAX5898 toc11
CENTER FREQUENCY (MHz)
TWO-TONE IMD (dBc)6085110135
1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz
-12dBFS
-6dBFS
-12dBFS
-9dBFS
-6dBFS
CHANNEL-TO-CHANNEL
GAIN MISMATCH vs. TEMPERATURE
fDATA = 125Mwps, 2x INTERPOLATIONMAX5898 toc12
TEMPERATURE (°C)
GAIN MISMATCH (dB)3510-15
fOUT = 22.7MHz
AOUT = -6dBFS
EIGHT-TONE POWER RATIO PLOT
fDATA = 125Mwps, 2x INTERPOLATIONMAX5898 toc13
fCENTER = 35.7MHz, 1MHz TONE SPACING
SPAN = 12.5MHz, AOUT1 THROUGH AOUT8 = -18dBFS
OUTPUT POWER (dBm)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5898 toc14
DIGITAL INPUT CODE
DNL (LSB)
49,15232,76816,384
-1.065,536
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODEMAX5898 toc15
DIGITAL INPUT CODE
INL (LSB)
49,15232,76816,384
-5.065,536
SUPPLY CURRENT vs. DAC UPDATE RATE
2x INTERPOLATION, fOUT = 5MHzMAX5898 toc16
SUPPLY CURRENT (mA)
1.8V TOTAL
3.3V TOTAL
SUPPLY CURRENT vs. DAC UPDATE RATE
4x INTERPOLATION, fOUT = 5MHzMAX5898 toc17
SUPPLY CURRENT (mA)
1.8V TOTAL
3.3V TOTAL
SUPPLY CURRENT vs. DAC UPDATE RATE
8x INTERPOLATION, fOUT = 5MHzMAX5898 toc18
SUPPLY CURRENT (mA)
1.8V TOTAL
3.3V TOTAL
Typical Operating Characteristics (continued)(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, DATACLK output mode, external reference, VREFIO= +1.25V,
RLOAD= 50Ωdouble-terminated, IOUTFS= 20mA, TA= +25°C, unless otherwise noted.)
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS InputsNOISE DENSITY vs. DAC UPDATE RATE
fOUT = 16MHz, AOUT = -12dBFS, 10MHz OFFSET
MAX5898 toc19
fDAC (MHz)
NOISE DENSITY (dBFS/Hz)
8x INTERPOLATION
4x INTERPOLATION
2x INTERPOLATION
WCDMA ACLR vs. OUTPUT FREQUENCY
fDATA = 122.88Mwps, 4x INTERPOLATIONMAX5898 toc20
fCENTER (MHz)
ACLR (dB)
FOUR-CARRIER
ALTERNATE CHANNEL
FOUR-CARRIER
ADJACENT CHANNEL
ONE-CARRIER
ALTERNATE CHANNEL
ONE-CARRIER
ADJACENT CHANNEL
WCDMA ACLR vs. OUTPUT FREQUENCY
fDATA = 76.8Mwps, 4x INTERPOLATIONMAX5898 toc21
fCENTER (MHz)
ACLR (dB)
FOUR-CARRIER
ALTERNATE CHANNELFOUR-CARRIER
ADJACENT CHANNEL
ONE-CARRIER
ALTERNATE CHANNELONE-CARRIER
ADJACENT CHANNEL
MAX5898 toc22
WCDMA ACLR SPECTRAL PLOT
fDATA = 61.44Mwps, 8x INTERPOLATIONfCENTER = 61.44MHz
SPAN = 25.5MHz
OUTPUT POWER (dBm)
ACLR2 = 78dBACLR1 = 77dBACLR1 = 76dBACLR2 = 77dB
CARRIER = -11dBm
MAX5898 toc23
FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT
fDATA = 61.44Mwps, 8x INTERPOLATIONfCENTER = 61.44MHz
SPAN = 40.6MHz
OUTPUT POWER (dBm)
ACLR2 = 74dBACLR1 = 72dBACLR1 = 71dBACLR2 = 71dB
CARRIER = -17dBm
MAX5898 toc24
WCDMA ACLR SPECTRAL PLOT
fDATA = 122.88Mwps, 4x INTERPOLATIONfCENTER = 122.88MHz
SPAN = 25.5MHz
OUTPUT POWER (dBm)
ACLR2 = 70dBACLR1 = 68dBACLR1 = 68dBACLR2 = 70dB
CARRIER = -12dBm
MAX5898 toc25
FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT
fDATA = 122.88Mwps, 4x INTERPOLATIONfCENTER = 122.88MHz
SPAN = 40.6MHz
OUTPUT POWER (dBm)
ACLR2 = 65dBACLR1 = 64dBACLR1 = 63dBACLR2 = 63dB
CARRIER = -20dBm
Typical Operating Characteristics (continued)(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, DATACLK output mode, external reference, VREFIO= +1.25V,
RLOAD= 50Ωdouble-terminated, IOUTFS= 20mA, TA= +25°C, unless otherwise noted.)
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Pin Description
PINNAMEFUNCTIONCLKPNoninverting Differential Clock Input. Internally biased to AVCLK / 2.CLKNInverting Differential Clock Input. Internally biased to AVCLK / 2.N.C.Internally Connected. Do not connect.DATACLKPLVDS Data Clock Input/Output. External 100Ω termination to DATACLKN required.DATACLKNComplementary LVDS Data Clock Input/Output. External 100Ω termination to DATACLKP required.
6, 21, 30, 37DVDD1.8Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a
0.1µF capacitor as close to the pin as possible.SELIQN
Complementary LVDS Channel Select Input. Set SELIQN low and SELIQP high to direct data to
the channel. Set SELIQP low and SELIQN high to direct data to the channel. Internal 110Ω
termination to SELIQP.SELIQPLVDS Channel Select Input. Set SELIQN low and SELIQP high to direct data to the channel. Set
SELIQP low and SELIQN high to direct data to the channel. Internal 110Ω termination to SELIQN.D15NComplementary LVDS Data Bit 15 (MSB). Internal 110Ω termination to D15P.D15PLVDS Data Bit 15 (MSB). Internal 110Ω termination to D15N.D14NComplementary LVDS Data Bit 14. Internal 110Ω termination to D14P.D14PLVDS Data Bit 14. Internal 110Ω termination to D14N.D13NComplementary LVDS Data Bit 13. Internal 110Ω termination to D13P.D13PLVDS Data Bit 13. Internal 110Ω termination to D13N.D12NComplementary LVDS Data Bit 12. Internal 110Ω termination to D12P.D12PLVDS Data Bit 12. Internal 110Ω termination to D12N.D11NComplementary LVDS Data Bit 11. Internal 110Ω termination to D11P.D11PLVDS Data Bit 11. Internal 110Ω termination to D11N.D10NComplementary LVDS Data Bit 10. Internal 110Ω termination to D10P.D10PLVDS Data Bit 10. Internal 110Ω termination to D10N.D9NComplementary LVDS Data Bit 9. Internal 110Ω termination to D9P.D9PLVDS Data Bit 9. Internal 110Ω termination to D9N.D8NComplementary LVDS Data Bit 8. Internal 110Ω termination to D8P.D8PLVDS Data Bit 8. Internal 110Ω termination to D8N.D7NComplementary LVDS Data Bit 7. Internal 110Ω termination to D7P.D7PLVDS Data Bit 7. Internal 110Ω termination to D7N.D6NComplementary LVDS Data Bit 6. Internal 110Ω termination to D6P.D6PLVDS Data Bit 6. Internal 110Ω termination to D6N.D5NComplementary LVDS Data Bit 5. Internal 110Ω termination to D5P.D5PLVDS Data Bit 5. Internal 110Ω termination to D5N.D4NComplementary LVDS Data Bit 4. Internal 110Ω termination to D4P.D4PLVDS Data Bit 4. Internal 110Ω termination to D4N.
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Pin Description (continued)
PINNAMEFUNCTIOND3NComplementary LVDS Data Bit 3. Internal 110Ω termination to D3P.D3PLVDS Data Bit 3. Internal 110Ω termination to D3N.D2NComplementary LVDS Data Bit 2. Internal 110Ω termination to D2P.D2PLVDS Data Bit 2. Internal 110Ω termination to D2N.D1NComplementary LVDS Data Bit 1. Internal 110Ω termination to D1P.D1PLVDS Data Bit 1. Internal 110Ω termination to D1N.D0NComplementary LVDS Data Bit 0 (LSB). Internal 110Ω termination to D0P.D0PLVDS Data Bit 0 (LSB). Internal 110Ω termination to D0N.DVDD3.3I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass with a 0.1µF capacitor as close to
the pin as possible.DOUTSerial-Port Data OutputDINSerial-Port Data InputSCLKSerial-Port Clock Input. Data on DIN is latched on the rising edge of SCLK.CSSerial-Port Interface Select. Drive CS low to enable serial-port interface.RESETReset Input. Hold RESET low during power-up.REFIOReference Input/Output. Bypass to ground with a 1µF capacitor as close to the pin as possible.DACREFur r ent- S et Resi stor Retur n P ath. For a 20m A ful l - scal e outp ut cur r ent, use a 1.25V exter nal r efer ence
and connect a 2kΩ r esi stor b etw een FS AD J and D AC RE F. Inter nal l y connected to GN D . D
O NO T U SES AN EXT ER N A L GR O U N D C O N N EC T IO N . FSADJFull-Scale Adjust Input. For a 20m A ful l - scal e outp ut cur r ent, use a 1.25V exter nal r efer ence and
connect a 2kΩ r esi stor b etw een FS AD J and D AC RE F.
53, 67AVDD1.8Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with
a 0.1µF capacitor as close to the pin as possible.
54, 56, 59, 61,
64, 66GNDGround
55, 60, 65AVDD3.3Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a
0.1µF capacitor as close to the pin as possible.OUTQNInverting Differential DAC Current Output for Q ChannelOUTQPNoninverting Differential DAC Current Output for Q ChannelOUTINInverting Differential DAC Current Output for I ChannelOUTIPNoninverting Differential DAC Current Output for I ChannelAVCLKClock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1µF
capacitor as close to the pin as possible.EPExposed Paddle. Must be connected to GND through a low-impedance path.
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Detailed DescriptionThe MAX5898 dual, 500Msps, high-speed, 16-bit, cur-
rent-output DAC provides superior performance in com-
munication systems requiring low-distortion analog-signal
reconstruction. The MAX5898 combines two DAC cores
with 8x/4x/2x programmable digital interpolation filters, a
digital quadrature modulator, an SPI-compatible serial
interface for programming the device, and an on-chip
1.2V reference. Individual DAC channel gain and offset
adjustments are available to compensate for downstream
signal-path imbalances. The full-scale output current
range is adjustable from 2mA to 20mA to optimize power
dissipation and gain control.
Each channel contains three selectable interpolating fil-
ters making the MAX5898 capable of 2x, 4x, 8x, or no
interpolation, which allows for low input data rates and
high DAC update rates. When operating in 8x interpola-
tion mode, the interpolator increases the DAC conversion
rate by a factor of eight, providing an eight-fold increase
in separation between the reconstructed waveform spec-
trum and its first image. The MAX5898 accepts either
two’s complement or offset binary input data format on a
single interleaved LVDS input bus.
The MAX5898 includes modulation modes at fIM/ 2 and
fIM/ 4, where fIMis the data rate at the input of the mod-
ulator. If 2x interpolation is used, this data rate is 2x the
input data rate. If 4x or 8x interpolation is used, this data
rate is 4x the input data rate. Table 1 summarizes the
modulator operating data rates.
The power-down modes can be used to turn off each
DAC’s output current or the entire digital section.
Programming both DACs into power-down simultane-
ously powers down the digital interpolation filters. Note
that the SPI section is always active.
The analog and digital sections of the MAX5898 have
separate power-supply inputs (AVDD3.3, AVDD1.8,
Functional DiagramIDAC
OUTIP
OUTIN
QDAC
OUTQP
OUTQN
SELIQ
D0–D15
SERIAL INTERFACE
CONTROL REGISTERS
REFERENCE
MODULATOR
CLOCK BUFFERS
AND DIVIDERS
CLKPCLKN
RESET
fCLK
fDAC
fDAC
SYNCHAND DEMUX
MUXII
INTERPOLA
TING
FILT
INTERPOLA
TING
FIL
TER
INTERPOLA
TING
FIL
TER
INTERPOLA
TING
FIL
TER
INTERPOLA
TING
FIL
TER
INTERPOLA
TING
FIL
TER
MUX
MUX
MUX
MUX
MUXMUXMUXMUX
MUX
DIGITAL
OFFSET
ADJUST
DIGITAL
OFFSET
ADJUST
DIGITAL
GAIN
ADJUST/2
DOUTDINCSSCLKDACREFFSADJREFIO
DATACLK∑
fIM / 2, fIM / 4
DIGITAL
GAIN
ADJUST/2
MAX5898
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS InputsAVCLK, DVDD3.3, and DVDD1.8), which minimize noise
coupling from one supply to the other. AVDD1.8and
DVDD1.8operate from a typical 1.8V supply, and all
other supply inputs operate from a typical 3.3V supply.
Serial InterfaceThe SPI-compatible serial interface programs the
MAX5898 registers. The serial interface consists of CS,
DIN, SCLK, and DOUT. Data is shifted into DIN on the
rising edge of SCLK when CSis low. When CSis high,
data presented at DIN is ignored and DOUT is in high-
impedance mode.
Note: CS
must transition high
after each read/write operation.DOUT is the serial
data output for reading registers to facilitate easy
debugging during development. DIN and DOUT can
be connected together to form a 3-wire serial interface
bus or remain separate and form a 4-wire SPI bus.
The serial interface supports two-byte transfer in a
communication cycle. The first byte is a control byte
written to the MAX5898 only. The second byte is a data
byte and can be written to or read from the MAX5898.
When writing to the MAX5898, data is shifted into DIN;
data is shifted out of DOUT in a read operation. Bits 0 to
3 of the control byte are the address bits. These bits set
the address of the register to be written to or read from.
Bits 4 to 6 of the control byte must always be set to 0.
Bit 7 is a read/write bit: 0 for write operation and 1 for
read operation. The most significant bit (MSB) is shifted
in first in default mode. If the serial port is set to LSB-first
mode, both the control byte and data byte are shifted LSB
first. Figures 1 and 2 show the SPI serial-interface opera-
tion in the default write and read mode, respectively.
Figure 3 is a timing diagram for the SPI serial interface.
Table1. Quadrature Modulator Operating Data Rates (fIMis the Data Rate at the Input of
the Modulator)
INTERPOLATION RATEMODULATION MODE (fLO)MODULATION FREQUENCY
RELATIVE TO fDAC
MODULATION FREQUENCY
RELATIVE TO fDATAfIM / 2fDAC / 2fDATA / 21xfIM / 4fDAC / 4fDATA / 4
fIM / 2fDAC / 2fDATA2xfIM / 4fDAC / 4fDATA / 2
fIM / 2fDAC / 22 x fDATA4xfIM / 4fDAC / 4fDATA
fIM / 2fDAC / 42 x fDATA8xfIM / 4fDAC / 8fDATA
Figure1. SPI Serial-Interface Write Cycle, MSB-First Mode000A3A2A1A0D7D6D5D4D3D2D1D0
SCLK
DIN
DOUTHIGH IMPEDANCE
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS InputsSCLK
DIN
DOUT003210
HIGH
IMPEDANCE
IGNORED
ADDRESSDATA
READ CYCLE N - 1
DATA N - 2003210
HIGH
IMPEDANCE
IGNORED
ADDRESSDATA
READ CYCLE N
DATA N - 1003210
HIGH
IMPEDANCE
IGNORED
ADDRESSDATA
READ CYCLE N + 1
DATA N
Figure2. SPI Serial-Interface Read Cycle, MSB-First Mode
tSS
SCLK
DIN
tSDStSDH
tSDV
DOUT
Figure3. SPI Serial-Interface Timing Diagram
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Programming RegistersProgramming its registers with the SPI serial interface
sets the MAX5898 operation modes. Table 2 shows all
of the registers. The following are descriptions of each
register.
ADDBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 000hUnused
0 = MSB first1 = LSB first
Software Reset
0 = Normal1 = Reset all
registers
Interpolator
Power-Down
0 = Normal1 = Power-down
IDAC Power-
Down
0 = Normal1 = Power-down
QDAC Power-
Down
0 = Normal1 = Power-down
Unused
01h
Interpolation Rate
(Bit 7, Bit 6)
00 = No interpolation
01 = 2x interpolation
10 = 4x interpolation
11 = 8x interpolationThird
Interpolation
Filter
Configuration
0 = Lowpass1 = Highpass
Modulation Mode
(Bit 4, Bit 3)
00 = Modulation off
01 = fIM / 2
10 = fIM / 411 = fIM / 4
Mixer Modulation
Mode
0 = Complex
1 = RealModulation
Sign
0 = e-jω1 = e+jω
Unused
02h
0 = Two’s-
complement
input data1 = Offset
binary input
data
UnusedUnused
0 = Input data
latched on
rising clock
edge1 = Input data
latched on falling
clock edge
0 = Data clock
output disabled1 = Data clock
output enabled
Data
Synchronizer
Disable
0 = Enabled1 = Disabled
Unused
03hUnused
04h8-Bit IDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
05hUnused4-Bit IDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
06h10-Bit IDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 06h register are the MSB bits. Bit 1 and bit 0 are the LSB
bits in the 07h register. Default: 000h
07h
IDAC IOFFSET
Direction
0 = Current on
OUTIN1 = Current on
OUTIP
Unused
IDAC Offset
Adjustment
Bit 1
(see the 06h
register)
IDAC Offset
Adjustment
Bit 0
(see the 06h
register)
08h8-Bit QDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
09hUnused4-Bit QDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
0Ah10-Bit QDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 0Ah register are the MSB bits. Bit 1 and bit 0 are the
LSB bits in the 0Bh register. Default: 000h
0Bh
QDAC
IOFFSET
Direction
0 = Current on
OUTQN1 = Current on
OUTQP
Unused
QDAC Offset
Adjustment
Bit 1
(see the 0Ah
register)
QDAC Offset
Adjustment
Bit 0
(see the 0Ah
register)
0ChReserved, do not write to these bits.
0DhReserved, do not write to these bits.
0EhReserved, do not write to these bits.
Table2. MAX5898 Programmable RegistersConditions in boldare power-up defaults.
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Address 00hBit 6Logic 0 (default) causes the serial port to use
MSB first address/data format. When set to a
logic 1, the serial port uses LSB first address/
data format.
Bit 5When set to a logic 1 (default = 0), all registers
reset to their default state (this bit included).
Bit 4Logic 1 (default = 0) stops the clock to the
digital interpolators. DAC outputs hold last
value prior to interpolator power-down.
Bit 3IDAC power-down mode. A logic 1 (default = 0)
to this bit shuts down the output current from
the IDAC.
Bit 2QDAC power-down mode. A logic 1 (default = 0)
to this bit shuts down the output current from
the QDAC.
Note:If both bit 2 and bit 3 are 1, the MAX5898 is in
full-power-down mode, leaving only the serial interface
active.
Address 01hBits 7, 6Configure the interpolation filters according
to the following:1x (no interpolation)2x4x8x (default)
Bit 5Logic 0 configures FIR3 as a lowpass digital
filter (default). A logic 1 configures FIR3 as a
highpass digital filter.
Bits 4, 3Configure the modulation frequency accord-
ing to the following:No modulationfIM/ 2 modulationfIM/ 4 modulation (default)fIM/ 4 modulation
where fIMis the data rate at the input of the
modulator.
Bit 2Configures the modulation mode for either
real or complex (image reject) modulation.
Logic 1 sets the modulator to the real mode
(default). Complex modulation is only avail-
able for fIM / 4 modulation.
Bit 1 Quadrature modulator sign inversion. With I-
channel data leading Q-channel data by 90°,
logic 0 sets the complex modulation to be
e-jw(default), cancelling the upper image. A
logic 1 sets the complex modulation to be+jw, cancelling the lower image.
Address 02hBit 7Logic 0 (default) configures the data port for
two’s complement. A logic 1 configures the
data ports for offset binary.
Bit 4Logic 0 (default) sets the internal latches to
latch the data on the rising edge of DATACLK.
A logic 1 sets the internal latches to latch the
data on the falling edge of DATACLK.
Bit 3Logic 0 (default) configures the DATACLK
pin (pin 4 or pin 5) to be an input. A logic 1
configures the DATACLK pin to be an output.
Bit 2Logic 0 (default) enables the data synchro-
nizer circuitry. A logic 1 disables the data
synchronizer circuitry.
Address 04hBits 7–0These 8 bits define the binary number for
fine-gain adjustment of the IDAC full-scale
current (see the Gain Adjustmentsection). Bit
7 is the MSB. Default is all zeros.
Address 05hBits 3–0These four bits define the binary number for
the coarse-gain adjustment of the IDAC full-
scale current (see the Gain Adjustmentsec-
tion). Bit 3 is the MSB. Default is all ones.
Address 06h, Bits 7–0; Address 07h, Bit 1 and Bit 0These 10 bits represent a binary number that
defines the magnitude of the offset added to
the IDAC output (see the Offset Adjustment
section). Default is all zeros.
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Address 07hBit 7Logic 0 (default) adds the 10 bits offset cur-
rent to OUTIN. A logic 1 adds the 10 bits off-
set current to OUTIP.
Address 08hBits 7–0These 8 bits define the binary number for
fine-gain adjustment of the QDAC full-scale
current (see the Gain Adjustmentsection). Bit
7 is the MSB. Default is all zeros.
Address 09hBits 3–0These four bits define the binary number for
the coarse-gain adjustment of the QDAC full-
scale current (see the Gain Adjustmentsec-
tion). Bit 3 is the MSB. Default is all ones.
Address 0Ah, Bits 7–0; Address 0Bh, Bit 1 and Bit 0These 10 bits represent a binary number that
defines the magnitude of the offset added to
the QDAC output (see the Offset Adjustment
section). Default is all zeros.
Address 0BhBit 7Logic 0 (default) adds the 10 bits offset to
OUTQN. A logic 1 adds the 10 bits offset to
OUTQP.
Offset AdjustmentOffset adjustment is achieved by adding a digital code to
the DAC inputs. The code OFFSET (see equation below),
as stored in the relevant control registers, has a range
from 0 to 1023 and a sign bit. The applied DAC offset
is four times the code stored in the register, providing an
offset adjustment range of ±4092 LSB codes. The resolu-
tion is 4 LSB.
Gain TrimGain adjustment is peformed by varying the full-scale
current according to the following formula:
where IREFis the reference current (see the Reference
Input/Output section). COARSE is the register content
of registers 05h and 09h for the I and Q channel,
respectively. FINE is the register content of register 04h
and 08h for the I and Q channel, respectively. The
range of COARSEis from 0 to 15, with 15 being the
default. The range for FINE is from 0 to 255 with 0
being the default. The gain can be adjusted in steps of
approximately 0.01dB.
Data Input PortThe MAX5898 captures input data on a single LVDS
port (D15P/N–D0P/N). The channel for the input data is
determined through the state of SELIQP/SELIQN. When
SELIQP is set to logic-high and SELIQN is set to logic-
low the input data is presented to the I channel. Setting
SELIQP to logic-low and SELIQN to logic-high presents
the input data to the Q channel.
The MAX5898 control registers can be programmed to
allow either signed or unsigned binary format (bit 7,
address 02h) data. Table 3 shows the corresponding DAC
output levels when using signed or unsigned data modes.
Data Synchronization ModesData synchronization circuitry is provided to allow oper-
ation with an input data clock. The data clock must be
frequency locked to the DAC clock (fDAC), but can
have arbitrary phase with respect to the DAC clock.
The synchronization circuitry allows for phase jitter on
the input data clock of up to ±1 data clock cycles.
Synchronization is initially established when the reset
pin is asynchronously deasserted and the input data
clock has been running for at least four clock cycles.
Subsequently, the MAX5898 monitors the phase rela-
tionship and detects if the phase drifts more than ±1
data clock cycle. If this occurs, the synchronizer auto-
matically re-establishes synchronization. However, dur-
ing the resynchronization phase, up to 8 data words
may be lost or repeated.
Bit 2 of register 02h disables or enables (default) the
automatic data clock phase detection. Disabling the
data synchronization circuitry requires the data clock
and the DAC clock phase to be locked.ICOARSEIFINE
OUTFSREFREF =×⎛⎜⎞⎟+⎛⎜⎞⎟×⎛⎜⎞⎟⎛⎜⎞⎟⎡⎢⎤⎥⎛⎜⎞⎟−3256
1024OFFSETIOFFSETOUTFS =××416
IG IT A L IN PU T C O D EF F SET IN A R YU N SI G N ED ) WO ' SO M PL EM EN T SI G N ED ) U T _ PO U T _ N 0000 0000 0000 00001000 0000 0000 00000IOU T FS
0111 1111 1111 11110000 0000 0000 0000IOU T FS /
IOU T FS /
1111 1111 1111 11110111 1111 1111 1111IOU T FS 0
Table3. DAC Output Code Table
