MAX5887EGK+D ,3.3V, 14-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPBase Stations: Single/Multicarrier UMTS, B1P 1 51 B9NB1N 2 50 B9PCDMA, GSM B0P 3 49 B ..
MAX5888AEGK ,3.3V, 16-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPB3P 1 51 B11NBase Stations: Single-/Multicarrier UMTS, B3N 2 50 B11PB2P 3 49 B12NCDMA ..
MAX5888AEGK+ ,3.3V, 16-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputsfeatures an integrated 1.2V bandgap ref-♦ 68-Lead QFN-EP Packageerence and control amplifier to ens ..
MAX5888AEGK+D ,3.3V, 16-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPB3P 1 51 B11NBase Stations: Single-/Multicarrier UMTS, B3N 2 50 B11PB2P 3 49 B12NCDMA ..
MAX5888EGK , 3.3V, 16-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
MAX5888EGK+D ,3.3V, 16-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsELECTRICAL CHARACTERISTICS(AV = DV = VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V = ..
MAZ8051-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8051-L ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8051M ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8051-M ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8056-H ,Silicon planar typeAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8056-L ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAX5887EGK+D
3.3V, 14-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs
General DescriptionThe MAX5887 is an advanced, 14-bit, 500Msps digital-
to-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthe-
sis applications found in wireless base stations and
other communications applications. Operating from a
single 3.3V supply, this DAC offers exceptional dyna-
mic performance such as 76dBc spurious-free dynamic
range (SFDR) at fOUT= 30MHz. The DAC supports
update rates of 500Msps and a power dissipation of
only 230mW.
The MAX5887 utilizes a current-steering architecture,
which supports a full-scale output current range of 2mA
to 20mA, and allows a differential output voltage swing
between 0.1VP-Pand 1VP-P.
The MAX5887 features an integrated 1.2V bandgap ref-
erence and control amplifier to ensure high accuracy
and low noise performance. Additionally, a separate
reference input pin enables the user to apply an exter-
nal reference source for optimum flexibility and to
improve gain accuracy.
The digital and clock inputs of the MAX5887 are
designed for differential low-voltage differential signal
(LVDS)-compatible voltage levels. The MAX5887 is
available in a 68-pin QFN package with an exposed
paddle (EP) and is specified for the extended industrial
temperature range (-40°C to +85°C).
Refer to the MAX5886 and MAX5888 data sheets for
pin-compatible 12- and 16-bit versions of the MAX5887.
ApplicationsBase Stations: Single/Multicarrier UMTS,
CDMA, GSM
Communications: LMDS, MMDS, Point-to-Point
Microwave
Digital Signal Synthesis
Automated Test Equipment (ATE)
Instrumentation
Features500Msps Output Update RateSingle 3.3V Supply OperationExcellent SFDR and IMD Performance
SFDR = 76dBc at fOUT= 30MHz (to Nyquist)
IMD = -85dBc at fOUT= 10MHz
ACLR = 72dB at fOUT= 61MHz2mA to 20mA Full-Scale Output CurrentDifferential, LVDS-Compatible Digital and Clock
InputsOn-Chip 1.2V Bandgap ReferenceLow 130mW Power Dissipation68-Lead QFN-EP Package
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
Ordering Information19-2777; Rev 2; 12/03
PARTTEMP RANGEPIN-PACKAGEMAX5887EGK-40°C to +85°C68 QFN-EP*596061625455565763
VCLK
AGND
B4P
QFNTOP VIEW
DGNDDV
DGNDB5NB5PB6NB6PB7NB7P53
B8NB8P
FSADJ
REFIO
N.C.
DACREF
AGND
IOUTPIOUTN
AGNDAGND
B11N
B11P
B12N
B12P
B13N
B13P
DGND
DVDD
SEL0
N.C.N.C.
N.C.
N.C.
DVDD
DGND
N.C.
N.C.
N.C.
VCLK
CLKGND
CLKN
CLKP
CLKGND
N.C.
B0N
B0P
B1NB10P
B1P
B4N6667
B2PB3NB3P
B2N2221201927262524182928323130
AGND
N.C.33B9P
B10NB9N17
MAX5887
Pin Configuration*EP = Exposed paddle.
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO= 1.25V, differential transformer-coupled
analog output, 50Ωdouble terminated (Figure 7), IOUT= 20mA, TA= TMINto TMAX, unless otherwise noted. ≥+25°C guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9V
AVDD, DVDD, VCLK to DGND...............................-0.3V to +3.9V
AVDD, DVDD, VCLK to CLKGND...........................-0.3V to +3.9V
AGND, CLKGND to DGND....................................-0.3V to +0.3V
DACREF, REFIO, FSADJ to AGND.............-0.3V to AVDD+ 0.3V
IOUTP, IOUTN to AGND................................-1V to AVDD+ 0.3V
CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V
B0P/B0N–B13P/B13N, SEL0,
PD to DGND...........................................-0.3V to DVDD+ 0.3V
Continuous Power Dissipation (TA= +70°C)
68-Pin QFN-EP (derate 41.7mW/°C above +70°C)......3333mW
Thermal Resistance (θJA)..............................................+24°C/W
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC PERFORMANCEResolution14Bits
Integral NonlinearityINLMeasured differentially±0.8LSB
Differential NonlinearityDNLMeasured differentially±0.5LSB
Offset ErrorOS-0.025±0.01+0.025% FS
Offset Drift±50ppm/°C
Full-Scale Gain ErrorGEFSExternal reference, TA ≥ +25°C-3.5+1.5% FS
Internal reference±100Gain DriftExternal reference±50ppm/°C
Full-Scale Output CurrentIOUT(Note 1)220mA
Min Output VoltageSingle ended-0.5V
Max Output VoltageSingle ended1.1V
Output ResistanceROUT1MΩ
Output CapacitanceCOUT5pF
DYNAMIC PERFORMANCEOutput Update RatefCLK1500Msps
fCLK = 100MHzfOUT = 16MHz, -12dB FS-157Noise Spectral DensityfCLK = 200MHzfOUT = 80MHz, -12dB FS-157
dB FS/
fOUT = 1MHz, 0dB FS88
fOUT = 1MHz, -6dB FS89Spurious-Free Dynamic Range to
NyquistSFDRfCLK = 100MHz
fOUT = 1MHz, -12dB FS80
dBc
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO= 1.25V, differential transformer-coupled
analog output, 50Ωdouble terminated (Figure 7), IOUT= 20mA, TA= TMINto TMAX, unless otherwise noted. ≥+25°C guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfOUT = 10MHz, -12dB FS81fCLK = 100MHzfOUT = 30MHz, -12dB FS76
fOUT = 10MHz, -12dB FS71
fOUT = 16MHz, -12dB FS,
TA ≥ +25°C6976
fOUT = 50MHz, -12dB FS72
fCLK = 200MHz
fOUT = 80MHz, -12dB FS64
fOUT = 10MHz, -12dB FS66
fOUT = 30MHz, -12dB FS63
fOUT = 50MHz, -12dB FS65
Spurious-Free Dynamic Range to
NyquistSFDR
fCLK = 500MHz
fOUT = 80MHz, -12dB FS59
dBc
fCLK = 100MHzfOUT1 = 9MHz, -6dB FS,
fOUT2 = 10MHz, -6dB FS-85
2-Tone IMDTTIMD
fCLK = 200MHzfOU T 1 = 79M H z, -6dB FS,
fOU T 2 = 80M H z, -6dB FS-61
dBc
4-Tone IMD, 1MHz Frequency
Spacing, GSM ModelFTIMDfCLK = 300MHzfOUT = 32MHz, -12dB FS-78dBc
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
WCDMA Model
ACLRfCLK =
184.32MHzfOUT = 61.44MHz72dB
Output BandwidthBW-1dB(Note 2)450MHz
REFERENCEInternal Reference Voltage RangeVREFIO1.121.221.32V
Reference Voltage DriftTCOREF±50ppm/°C
Reference Input Compliance
RangeVREFIOCR0.11.25V
Reference Input ResistanceRREFIO10kΩ
ANALOG OUTPUT TIMINGOutput Fall TimetFALL90% to 10% (Note 3)375ps
Output Rise TimetRISE10% to 90% (Note 3)375ps
Output Voltage Settling TimetSETTLEOutput settles to 0.025% FS (Note 3)11ns
Output Propagation DelaytPD(Note 3)1.8ns
Glitch Energy1pV-s
IOUT = 2mA30Output NoiseNOUTIOUT = 20mA30pA/√Hz
TIMING CHARACTERISTICSData to Clock Setup TimetSETUPReferenced to rising edge of clock (Note 4)-0.8ns
Data to Clock Hold TimetHOLDReferenced to rising edge of clock (Note 4)1.8ns
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO= 1.25V, differential transformer-coupled
analog output, 50Ωdouble terminated (Figure 7), IOUT= 20mA, TA= TMINto TMAX, unless otherwise noted. ≥+25°C guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSData Latency3.5Clock
cycles
Minimum Clock Pulse Width HightCHCLKP, CLKN0.9ns
Minimum Clock Pulse Width LowtCLCLKP, CLKN0.9ns
LVDS LOGIC INPUTS (B0N–B13N, B0P–B13P)Differential Input Logic HighVIH100mV
Differential Input Logic LowVIL-100mV
Common-Mode Voltage RangeVCOM1.1251.375V
Differential Input ResistanceRIN85100125Ω
Input CapacitanceCIN5pF
CMOS LOGIC INPUTS (PD, SEL0)Input Logic HighVIH0.7 ✕
DVDDV
Input Logic LowVIL0.3 ✕
DVDDV
Input Leakage CurrentIIN-15+15µA
Input CapacitanceCIN5pF
CLOCK INPUTS (CLKP, CLKN)Sine wave≥1.5Differential Input Voltage SwingVCLKSquare wave≥0.5VP-P
Differential Input Slew RateSRCLK(Note 5)>100V/µs
Common-Mode Voltage RangeVCOM1.5
±20%V
Input ResistanceRCLK5kΩ
Input CapacitanceCCLK5pF
POWER SUPPLIESAnalog Supply Voltage RangeAVDD3.1353.33.465V
Digital Supply Voltage RangeDVDD3.1353.33.465V
Clock Supply Voltage RangeVCLK3.1353.33.465V
fCLK = 100Msps, fOUT = 1MHz27Analog Supply CurrentIAVDDPower-down0.3mA
fCLK = 100Msps, fOUT = 1MHz6.4mADigital Supply CurrentIDVDDPower-down10µA
fCLK = 100Msps, fOUT = 1MHz5.5mAClock Supply CurrentIVCLKPower-down10µA
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
Note 1:Nominal full-scale current IOUT= 32 ✕IREF.
Note 2:This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5887.
Note 3:Parameter measured single ended into a 50Ωtermination resistor.
Note 4:Parameter guaranteed by design.
Note 5:A differential clock input slew rate of >100V/µs is required to achieve the specified dynamic performance.
Note 6:Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfCLK = 100Msps, fOUT = 1MHz130Power DissipationPDISSPower-down1mW
Power-Supply Rejection RatioPSRRAVDD = VCLK = DVDD = 3.3V ±5% (Note 6)-1+1% FS/V
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, VREFIO= 1.25V, differential transformer-coupled
analog output, 50Ωdouble terminated (Figure 7), IOUT= 20mA, TA= TMINto TMAX, unless otherwise noted. ≥+25°C guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)
Typical Operating Characteristics(AVDD= DVDD= VCLK = 3.3V, external reference, VREFIO= 1.25V, RL= 50Ω, IOUT= 20mA, TA= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 100MHz)
MAX5887 toc01
fOUT (MHz)
SFDR (dBc)
0dB FS
-6dB FS
-12dB FS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 200MHz)
MAX5887 toc02
fOUT (MHz)
SFDR (dBc)
0dB FS
-12dB FS
-6dB FS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 500MHz)
MAX5887 toc03
fOUT (MHz)
SFDR (dBc)
-6dB FS
0dB FS
-12dB FS
2-TONE INTERMODULATION DISTORTION
(fCLK = 100MHz)
MAX5887 toc04
fOUT (MHz)
OUTPUT POWER (dBm)
AOUT = -6dB FS
BW = 9MHz
fT1 = 9.0252MHz
fT2 = 10.0417MHz
fT1 fT2
2 x fT1 - fT22 x fT2 - fT1
2-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fCLK = 200MHz)
MAX5887 toc05
fOUT (MHz)
TWO-TONE IMD (dBc)203050608070
-12dB FS
-6dB FS
2-TONE INTERMODULATION DISTORTION
(fCLK = 500MHz)
MAX5887 toc06
fOUT (MHz)
OUTPUT POWER (dBm)
AOUT = -6dB FS
BW = 9MHz
fT1 = 79.095MHz
fT2 = 80.3223MHz
2 x fT1 - fT22 x fT2 - fT1
fT1 fT2
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
Typical Operating Characteristics (continued)(AVDD= DVDD= VCLK = 3.3V, external reference, VREFIO= 1.25V, RL= 50Ω, IOUT= 20mA, TA= +25°C, unless otherwise noted.)
SFDR vs. TEMPERATURE
(fCLK = 300MHz, AOUT = -6dB FS, IOUT = 20mA)MAX5887 toc08
TEMPERATURE (°C)
SFDR (dBc)
fOUT = 120MHz
fOUT = 10MHz
fOUT = 40MHz
fOUT = 80MHz
SFDR vs. OUTPUT FREQUENCY
(fCLK = 300MHz, AOUT = -6dB FS)
MAX5887 toc07
fOUT (MHz)
SFDR (dBc)
IOUT = 20mA
IOUT = 10mAIOUT = 5mA
DIFFERENTIAL NONLINEARTIY
vs. DIGITAL INPUT CODE
MAX5887 toc10
DIGITAL INPUT CODE
DNL (LSB)10000200060001800014000
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5887 toc9
DIGITAL INPUT CODE
INL (LSB)60002000100001800014000
8-TONE MULTITONE POWER RATIO PLOT
(fCLK = 300MHz, fCENTER = 31.9702MHz)
MAX5887 toc11
fOUT (MHz)
OUTPUT POWER (dBm)
fT2 fT6
fT3 fT7
fT4 fT8
fT1 fT5
fT1 = 28.0151MHz
fT2 = 29.0405MHz
fT3 = 30.0659MHz
fT4= 31.0181MHz
fT5 = 33.06881MHz
fT6 = 34.0209MHz
fT7 = 35.0464MHz
fT8= 36.0718MHz
AOUT = -18dB FS
BW = 12MHz
POWER DISSIPATION vs. CLOCK FREQUENCY
(fOUT = 10MHz, AOUT = 0dB FS, IOUT = 20mA)
MAX5887 toc12
fCLK (MHz)
POWER DISSIPATION (mW)
POWER DISSIPATION vs. SUPPLY VOLTAGE
(fCLK = 100MHz, fOUT = 10MHz, IFS = 20mA)
MAX5887 toc13
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
EXTERNAL REFERENCE
INTERNAL REFERENCE
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
Pin Description
PINNAMEFUNCTIONB1PData Bit 1B1NComplementary Data Bit 1B0PData Bit 0B0NComplementary Data Bit 0
5–8, 23,
34–38N.C.No Connection. Do not connect to these pins. Do not tie these pins together.
9, 41, 60, 62DGNDDigital Ground
10, 40, 61DVDDDigital Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest DGND.
11, 16VCLKClock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest CLKGND.
12, 15CLKGNDClock GroundCLKPConverter Clock Input. Positive input terminal for the LVDS-compatible differential converter clock.CLKNComplementary Converter Clock Input. Negative input terminal for the LVDS-compatible differential
converter clock.PDPower-Down Input. PD pulled high enables the DAC’s power-down mode. PD pulled low allows for
normal operation of the DAC. This pin features an internal pulldown resistor.
18, 24, 29,
30, 32AVDDAnalog Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest AGND.
19, 25, 28,
31, 33, EPAGNDAnalog Ground. Exposed paddle (EP) must be connected to AGND.REFIOReference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1µF capacitor
to AGND. Can be driven with an external reference source.FSADJFull-Scale Adjust Input. This input sets the full-scale output current of the DAC. For 20mA full-scale
output current, connect a 2kΩ resistor between FSADJ and DACREF.DACREFReturn Path for the Current Set Resistor. For 20mA full-scale output current, connect a 2kΩ resistor
between FSADJ and DACREF.IOUTNComplementary DAC Output. Negative terminal for differential current output. The full-scale output
current range can be set from 2mA to 20mA.IOUTPDAC Output. Positive terminal for differential current output. The full-scale output current range can
be set from 2mA to 20mA.SEL0
Mode Select Input SEL0. Set high to activate the segment shuffling function. Since this pin features an
internal pulldown resistor, it can be left open or pulled low to disable the segment-shuffling function.
See Segment Shuffling in the Detailed Description section for more information.B13PData Bit 13 (MSB)B13NComplementary Data Bit 13 (MSB)B12PData Bit 12
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
Detailed Description
ArchitectureThe MAX5887 is a high-performance, 14-bit, current-
steering DAC (Figure 1) capable of operating with clock
speeds up to 500MHz. The converter consists of sepa-
rate input and DAC registers, followed by a current-
steering circuit. This circuit is capable of generating
differential full-scale currents in the range of 2mA to
20mA. An internal current-switching network in combi-
nation with external 50Ωtermination resistors convert
the differential output currents into a differential output
voltage with a peak-to-peak output voltage range of
0.1V to 1V. An integrated 1.2V bandgap reference, con-
trol amplifier, and user-selectable external resistor
determine the data converter’s full-scale output range.
Reference Architecture and OperationThe MAX5887 supports operation with the on-chip 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, low-
impedance reference source, and as the output if the
DAC is operating with the internal reference. For stable
operation with the internal reference, REFIO should be
decoupled to AGND with a 0.1µF capacitor. Due to its
limited output drive capability, REFIO must be buffered
with an external amplifier, if heavier loading is required.
The MAX5887’s reference circuit (Figure 2) employs a
control amplifier, designed to regulate the full-scale
current IOUTfor the differential current outputs of the
DAC. Configured as a voltage-to-current amplifier, the
output current can be calculated as follows:
IOUT= 32 ✕IREFIO- 1LSB
IOUT= 32 ✕IREFIO- (IOUT/ 214)
where IREFIOis the reference output current (IREFIO=
VREFIO/RSET) and IOUTis the full-scale output current of
the DAC. Located between FSADJ and DACREF, RSET
is the reference resistor, which determines the amplifi-
er’s output current for the DAC. See Table 1 for a matrix
of different IOUTand RSETselections.
PINNAMEFUNCTIONB12NComplementary Data Bit 12B11PData Bit 11B11NComplementary Data Bit 11B10PData Bit 10B10NComplementary Data Bit 10B9PData Bit 9B9NComplementary Data Bit 9B8PData Bit 8B8NComplementary Data Bit 8B7PData Bit 7B7NComplementary Data Bit 7B6PData Bit 6B6NComplementary Data Bit 6B5PData Bit 5B5NComplementary Data Bit 5B4PData Bit 4B4NComplementary Data Bit 4B3PData Bit 3B3NComplementary Data Bit 3B2PData Bit 2B2NComplementary Data Bit 2
Pin Description (continued)
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
Analog Outputs (IOUTP, IOUTN)The MAX5887 outputs two complementary currents
(IOUTP, IOUTN) that can be operated in a single-
ended or differential configuration. A load resistor can
convert these two output currents into complementary
single-ended output voltages. The differential voltage
existing between IOUTP and IOUTN can also be con-
verted to a single-ended voltage using a transformer or
a differential amplifier configuration. If no transformer is
used, the output should have a 50Ωtermination to the
analog ground and a 50Ωresistor between the outputs.
Although not recommended for single-ended operation,
because of additional noise pickup from the ground
1.2V
REFERENCE
CURRENT-STEERING
DAC
FUNCTION
SELECTION
BLOCK
AGND
SEL0DGNDDVDD
REFIO
FSADJ
CLKN
CLKP
AVDD
IOUTP
IOUTN
SEGMENT SHUFFLING/LATCH
DECODER
LVDS RECEIVER/INPUT LATCH
DIFFERENTIAL DIGITAL INPUTS B0 THROUGH B13
MAX5887
Figure 1. Simplified MAX5887 Block Diagram
RSET (kΩ)FULL-SCALE CURRENT
IOUT (mA)
REFERENCE CURRENT
IREF (µA)CALCULATED1% EIA STD
OUTPUT VOLTAGE
VIOUTP/N* (mVP-P)62.519.219.1100156.257.687.5250312.53.843.83500468.752.562.557506251.921.911000
Table 1. IOUTand RSETSelection Matrix Based on a Typical 1.200V Reference Voltage*Terminated into a 50Ωload.
