MAX5854ETL+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX5854ETL+T ,Dual, 10-Bit, 165Msps, Current-Output DACElectrical Characteristics(AV = DV = CV = 3V, AGND = DGND = CGND = 0, f = 165Msps, differential clo ..
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MAX5878EGK+ ,16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS InputsApplicationsBase Stations: Single/Multicarrier UMTS, CDMA, GSM68 67 66 65 64 63 62 61 60 59 58 57 5 ..
MAX5883EGM ,3.3V, 12-Bit, 200Msps High Dynamic Performance DAC with CMOS InputsApplications1 36N.C. B8Base Stations: Single/Multicarrier UMTS, 2 35 B9N.C.CDMAXOR 3 34 B104 33Comm ..
MAX5883EGM+D ,3.3V, 12-Bit, 200Msps High Dynamic Performance DAC with CMOS InputsApplications1 36N.C. B8Base Stations: Single/Multicarrier UMTS, 2 35 B9N.C.CDMAXOR 3 34 B104 33Comm ..
MAX5884EGM ,3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS InputsApplications1 36N.C. B10Base Stations: Single-/Multicarrier UMTS, N.C. 2 35 B11CDMA, GSM XOR 3 34 B ..
MAZ8047-H ,Silicon planar typeelectrical characteristicsZ Zwithin part numbersReverse current I V ··············· Specified value ..
MAZ8047-L ,Silicon planar typeAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8047M ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8047-M ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8051-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8051-L ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..

MAX5854ETL+T
Dual, 10-Bit, 165Msps, Current-Output DAC
General Description
The MAX5854 dual, 10-bit, 165Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The device inte-
grates two 10-bit DAC cores, and a 1.24V reference. The
MAX5854 supports single-ended and differential modes
of operation. The dynamic performance is maintained
over the entire 2.7V to 3.6V power-supply operating
range. The analog outputs support a -1.0V to +1.25V
compliance voltage.
The MAX5854 can operate in interleaved data mode to
reduce the I/O pin count. This allows the converter to be
updated on a single, 10-bit bus.
The MAX5854 features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on-chip
1.24V bandgap reference includes a control amplifier that
allows external full-scale adjustments of both channels
through a single resistor. The internal reference can be
disabled and an external reference can be applied for
high-accuracy applications.
The MAX5854 features full-scale current outputs of 2mA
to 20mA and operates from a 2.7V to 3.6V single supply.
The DAC supports three modes of power-control opera-
tion: normal, low-power standby, and complete power-
down. In power-down mode, the operating current is reduced to 1μA.
The MAX5854 is packaged in a 40-pin TQFN with
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.
Pin-compatible, lower speed, and lower resolution ver-
sions are also available. Refer to the MAX5853 (10-
bit, 80Msps), the MAX5852 (8-bit, 165Msps), and the
MAX5851 (8-bit, 80Msps) data sheets for more informa-
tion. See Table 4 at the end of the data sheet.
Applications●Communications
SatCom, LMDS, MMDS, HFC, DSL, WLAN,
Point-to-Point Microwave Links●Wireless Base Stations●Quadrature Modulation●Direct Digital Synthesis (DDS)●Instrumentation/ATE
Features●10-Bit, 165Msps Dual DAC●Low Power 190mW with IFS = 20mA at fCLK = 165MHz●2.7V to 3.6V Single Supply●Full Output Swing and Dynamic Performance at
2.7V Supply●Superior Dynamic Performance 73dBc SFDR at fOUT = 40MHz UMTS ACLR = 65.5dB at fOUT = 30.7MHz●Programmable Channel Gain Matching●Integrated 1.24V Low-Noise Bandgap Reference●Single-Resistor Gain Control●Interleaved Data Mode●Single-Ended and Differential Clock Input Modes●Miniature 40-Pin TQFN Package, 6mm x 6mm●EV Kit Available—MAX5854 EV Kit
*EP = Exposed paddle.
PARTTEMP RANGEPIN-PACKAGE
MAX5854ETL-40°C to +85°C40 Thin QFN-EP*363738392016171213141532333435
DA0
DB8
AGND
MAX5854
TQFN
TOP VIEW
OUTPAOUTNAAGNDOUTPBOUTNBAV
REFRREFO
DB9DB6DB7
DB5DB4
DGND
DB2DB3
CVDD
CGND
CLK
CVDD
CLKXN
CLKXP
DCE
DB0
DB1
DA1
DA2/G0
DA3/G1
DA4/G2
DA5/G3
DA6/REN
DA7/IDE
DA8/DACEN
DA9/PD
MAX5854Dual, 10-Bit, 165Msps, Current-Output DAC
Ordering Information
Pin Coniguration
EVALUATION KIT AVAILABLE
AVDD, DVDD, CVDD to AGND, DGND, CGND .......-0.3V to +4V
DA9–DA0, DB9–DB0, CW, DCE to AGND,
DGND, CGND .....................................................-0.3V to +4V
CLKXN, CLKXP to CGND .......................................-0.3V to +4V
OUTP_, OUTN_ to AGND ....................-1.25V to (AVDD + 0.3V)
CLK to DGND .........................................-0.3V to (DVDD + 0.3V)
REFR, REFO to AGND ..........................-0.3V to (AVDD + 0.3V)
AGND to DGND, DGND to CGND,
AGND to CGND................................................-0.3V to +0.3V
Maximum Current into Any Pin
(excluding power supplies) ...........................................±50mA
Continuous Power Dissipation (TA = +70°C)
40-Pin TQFN-EP (derate 23.3mW/°C
above +70°C) ..............................................................1.860W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range ............................-65°C to +150°C
Junction Temperature ......................................................+150°C
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC PERFORMANCE
ResolutionN10Bits
Integral NonlinearityINLRL = 0-1.0±0.25+1.0LSB
Differential NonlinearityDNLGuaranteed monotonic, RL = 0-0.5±0.2+0.5LSB
Offset Error VOS-0.5±0.1+0.5LSB
Gain Error (See Also Gain Error Deinition Section)GEInternal reference (Note1)-11.0±1.5+6.8%FSRExternal reference-6.25±0.7+4.10
Gain-Error Temperature DriftInternal reference±150ppm/°CExternal reference±100
DYNAMIC PERFORMANCE
Spurious-Free Dynamic Range
to NyquistSFDR
fCLK = 165MHz,
AOUT = -1dBFS
fOUT = 10MHz69.478
dBc
fOUT = 20MHz77
fOUT = 40MHz73
fCLK = 100MHz,
AOUT = -1dBFS
fOUT = 10MHz77
fOUT = 20MHz77
fOUT = 30MHz76
fCLK = 25MHz,
AOUT = -1dBFSfOUT = 1MHz79
Spurious-Free Dynamic Range
Within a WindowSFDR
fCLK = 165MHz, fOUT = 10MHz,
AOUT = -1dBFS, span = 10MHz83
dBcfCLK = 100MHz, fOUT = 5MHz,
AOUT = -1dBFS, span = 4MHz84
fCLK = 25MHz, fOUT = 1MHz,
AOUT = -1dBFS, span = 2MHz82
MAX5854Dual, 10-Bit, 165Msps, Current-Output DAC
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Multitone Spurious-Free
Dynamic Range Within a
Window
8 tones at 2.1MHz spacing,
fCLK = 165MHz, fOUT = 28.3MHz to 45.2MHz,
span = 50MHzdBc
Adjacent Channel Power Ratio
with UMTSACLRfOUT = 30.72MHz, RBW = 30kHz,
fCLK = 122.88MHz65.5dB
Total Harmonic Distortion to
Nyquist (2nd- Through 8th-Order
Harmonics Included)
THD
fCLK = 165MHz,
AOUT = -1dBFS
fOUT = 10MHz-76
dBc
fOUT = 20MHz-74
fOUT = 40MHz-71
fCLK = 100MHz,
AOUT = -1dBFS
fOUT = 10MHz-75
fOUT = 20MHz-74
fOUT = 30MHz-73
fCLK = 25MHz,
AOUT = -1dBFSfOUT = 1MHz-76
Output Channel-to-Channel
IsolationfOUT = 10MHz90dB
Channel-to-Channel Gain
MismatchfOUT = 10MHz, G[3:0] = 10000.025dB
Channel-to-Channel Phase
MismatchfOUT = 10MHz0.05Degrees
Signal-to-Noise Ratio to NyquistSNR
fCLK = 165MHz, fOUT = 10MHz, IFS = 20mA60.5
fCLK = 165MHz, fOUT = 10MHz, IFS = 5mA61
fCLK = 65MHz, fOUT = 10MHz, IFS = 20mA62
fCLK = 65MHz, fOUT = 10MHz, IFS = 5mA62
Maximum DAC Conversion RatefDACInterleaved mode disabled, IDE = 0165200MspsInterleaved mode enabled, IDE = 182.5100
Glitch Impulse5pV-s
Output Settling TimetSTo ±0.1% error band (Note 3)12ns
Output Rise Time10% to 90% (Note 3)2.2ns
Output Fall Time90% to 10% (Note 3)2.2ns
ANALOG OUTPUT
Full-Scale Output Current
RangeIFS220mA
Output Voltage Compliance
Range-1.00+1.25V
Output Leakage CurrentShutdown or standby mode-5+5µA
REFERENCE
Internal-Reference Output
MAX5854Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Internal-Reference Supply
RejectionAVDD varied from 2.7V to 3.6V0.5mV/V
Internal-Reference Output-
Voltage Temperature DriftTCVREFOREN = 0 ±50ppm/°C
Internal-Reference Output Drive
CapabilityREN = 0 50µA
External-Reference Input
Voltage RangeREN = 1 0.101.21.32V
Current GainIFS/IREF32mA/mA
LOGIC INPUTS (DA9–DA0, DB9–DB0, CW)
Digital Input-Voltage HighVIH0.65 x
DVDDV
Digital Input-Voltage LowVIL0.3 x
DVDDV
Digital Input CurrentIIN-1+1µA
Digital Input CapacitanceCIN3pF
SINGLE-ENDED CLOCK INPUT/OUTPUT AND DCE INPUT (CLK, DCE)
Digital Input-Voltage HighVIHDCE = 10.65 x
CVDDV
Digital Input-Voltage LowVILDCE = 10.3 x
CVDDV
Digital Input CurrentIINDCE = 1-1+1µA
Digital Input CapacitanceCINDCE = 13pF
Digital Output-Voltage HighVOHDCE = 0, ISOURCE = 0.5mA, Figure 10.9 x
CVDDV
Digital Output-Voltage LowVOLDCE = 0, ISINK = 0.5mA, Figure 10.1 x
CVDDV
DIFFERENTIAL CLOCK INPUTS (CLKXP/CLKXN)
Differential Clock Input Internal
BiasCVDD/2V
Differential Clock Input Swing0.5V
Clock Input ImpedanceMeasured single ended5kΩ
POWER REQUIREMENTS
Analog Power-Supply VoltageAVDD2.733.6V
Digital Power-Supply VoltageDVDD2.733.6V
Clock Power-Supply VoltageCVDD2.733.6V
MAX5854Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Analog Supply CurrentIAVDD
IFS = 20mA (Note 2), single-ended clock mode43.246IFS = 20mA (Note 2), differential clock mode43.2
IFS = 2mA (Note 2), single-ended clock mode5
IFS = 2mA (Note 2), differential clock mode5
Digital Supply CurrentIDVDDIFS = 20mA (Note 2), single-ended clock mode6.27.5mAIFS = 20mA (Note 2), differential clock mode6.2
Clock Supply CurrentICVDDSingle-ended clock mode (DCE = 1) (Note 2)13.716.5mADifferential clock mode (DCE = 0) (Note 2)24
Total Standby CurrentISTANDBYIAVDD + IDVDD+ ICVDD3.13.7mA
Total Shutdown CurrentISHDNIAVDD + IDVDD + ICVDD1µA
Total Power DissipationPTOT
Single-ended clock
mode (DCE = 1)
IFS = 20mA (Note 2)190210
IFS = 2mA (Note 2)75
Differential clock mode
(DCE = 0)
IFS = 20mA (Note 2)220
IFS = 2mA (Note 2)106
Standby9.311.1
Shutdown0.003
TIMING CHARACTERISTICS (Figure 5, Figure 6)
Propagation Delay1Clock
cycles
DAC Data to CLK Rise/Fall
Setup TimetDCSSingle-ended clock mode (DCE = 1) (Note 4)1.2nsDifferential clock mode (DCE = 0) (Note 4)2.7
DAC Data to CLK Rise/Fall Hold
TimetDCHSingle-ended clock mode (DCE = 1) (Note 4)0.8nsDifferential clock mode (DCE = 0) (Note 4)-0.5
Control Word to CW Rise Setup
TimetCS2.5ns
Control Word to CW Rise Hold
TimetCW2.5ns
CW High TimetCWH5ns
CW Low TimetCWL5ns
DACEN = 1 to VOUT Stable
Time (Coming Out of Standby)tSTB3µs
MAX5854Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V,
IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA ≥ +25°C guaranteed by
production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
Note 1: Including the internal reference voltage tolerance and reference amplifier offset.
Note 2: fDAC = 165Msps, fOUT = 10MHz.
Note 3: Measured single-ended with 50Ω load and complementary output connected to AGND.
Note 4: Guaranteed by design, not production tested.
Figure 1. Load Test Circuit for CLK Outputs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PD = 0 to VOUT Stable Time
(Coming Out of Power-Down)tSHDN500µs
Maximum Clock Frequency at
CLKXP/CLKXN InputfCLK165200MHz
Clock High TimetCXHCLKXP or CLKXN input1.5ns
Clock Low TimetCXLCLKXP or CLKXN input1.5ns
CLKXP Rise to CLK Output Rise
DelaytCDHDCE = 02.7ns
CLKXP Fall to CLK Output Fall
DelaytCDLDCE = 02.7ns
TO OUTPUT
PIN
5pF
0.5mA
0.5mA
1.6V
MAX5854Dual, 10-Bit, 165Msps, Current-Output DAC
Electrical Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output,
TA = +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 100MHz)
MAX5854 toc02
fOUT (MHz)
SFDR (dBc)35253010152054550
0dBFS
-6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 25MHz)
MAX5854 toc03
fOUT (MHz)
SFDR (dBc)975313
0dBFS
-6dBFS-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 200MHz)
MAX5854 toc04
fOUT (MHz)
SFDR (dBc)8060702030405010100
0dBFS
-6dBFS-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 165MHz)
MAX5854 toc05
fOUT (MHz)
SFDR (dBc)7050602030401090
IOUT = 20mAIOUT = 5mA
IOUT = 10mA
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 165MHz)
MAX5854 toc06
fOUT (MHz)
SFDR (dBc)7050602030401090
AVDD = DVDD = CVDD = 3.3V
AVDD = DVDD = CVDD = 3.6V
AVDD = DVDD = CVDD = 2.7V
AVDD = DVDD = CVDD = 3V
SFDR vs. TEMPERATURE (fCLK = 165MHz,
fOUT = 10MHz, AOUT = 0dBFS)
MAX5854 toc07
SFDR (dBc)3510-15
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 200MHz)
MAX5854 toc04
fOUT (MHz)
SFDR (dBc)8060702030405010100
0dBFS
-6dBFS-12dBFS
TWO-TONE INTERMODULATION DISTORTION
(fCLK = 165MHz, 1MHz WINDOW)
MAX5854 toc08
AMPLITUDE (dB)
2fOUT2 - fOUT1
fOUT1fOUT2
2fOUT1 - fOUT2
fOUT1 = 4.8541MHz
fOUT2 = 5.0555MHz
MAX5854Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output,
TA = +25°C, unless otherwise noted.)
8-TONE SFDR PLOT
(fCLK = 165MHz, 35MHz WINDOW)
MAX5854 toc09
fOUT (MHz)
AMPLITUDE (dB)
fT4
fT3
fT2
fT1
fT5
fT6
fT7
fT8
fT1 = 17.493MHz
fT2 = 18.997MHz
fT3 = 20.200MHz
fT4 = 21.253MHz
fT5 = 24.035MHz
fT6 = 25.087MHz
fT7 = 26.741MHz
fT8 = 27.869MHz
SINGLE-TONE SFDR
(fCLK = 165MHz, 10MHz WINDOW)
MAX5854 toc10
fOUT (MHz)
AMPLITUDE (dB)756
fOUT1 = 9.1040MHz
AOUT = -1dBFS1311109
SINGLE-TONE SFDR
(fCLK = 100MHz, 4MHz WINDOW)
MAX5854 toc11
fOUT (MHz)
AMPLITUDE (dB)
fOUT1 = 5.0533MHz
AOUT = -1dBFS
SINGLE-TONE SFDR
(fCLK = 25MHz, 2MHz WINDOW)
MAX5854 toc12
fOUT (MHz)
AMPLITUDE (dB)
fOUT = 1.0152MHz
AOUT = -1dBFS
SINGLE-TONE SFDR
(fCLK = 78MHz, 20MHz WINDOW)
MAX5854 toc13
fOUT (MHz)
AMPLITUDE (dB)
fOUT = 11.0333MHz
AOUT = -1dBFS
SINGLE-TONE FFT PLOT (fCLK = 165MHz,
fOUT = 10MHz, AOUT = 0dBFS, NYQUIST WINDOW)
MAX5854 toc14
OUTPUT POWER (dBm)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5854 toc15
INL (LSB)
MAX5854Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output,
TA = +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5854 toc16
DIGITAL INPUT CODE
DNL (LSB)
POWER DISSIPATION vs. CLOCK FREQUENCY
(fOUT = 10MHz, AOUT = 0dBFS)
MAX5854 toc17
fCLK (MHz)
POWER DISSIPATION (mV)
DIFFERENTIAL
CLOCK DRIVE
SINGLE-ENDED
CLOCK DRIVE
POWER DISSIPATION vs. SUPPLY VOLTAGES
(fCLK = 165MHz, fOUT = 10MHz)
MAX5854 toc18
SUPPLY VOLTAGES (V)
POWER DISSIPATION (mW)
DIFFERENTIAL
CLOCK DRIVE
SINGLE-ENDED
CLOCK DRIVE
REFERENCE VOLTAGE vs. SUPPLY VOLTAGES
(fCLK = 165MHz, fOUT = 10MHz)
MAX5854 toc19
SUPPLY VOLTAGES (V)
REFEENCE VOLTAGE (V)
REFERENCE VOLTAGE vs. TEMPERATURE
MAX5854 toc20
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)3510-15
-408510ns/div
DYNAMIC RESPONSE RISE TIME
100mV/div
MAX5854 toc21
10ns/div
DYNAMIC RESPONSE FALL TIME
100mV/div
MAX5854 toc22
ACLR PLOT
(fCLK = 122.88MHz, fOUT = 30.72MHz)
MAX5854 toc23
1.468MHz/div
AMPLITUDE (dB)
ACLR = 65.5dB
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 165MHz)
MAX5854 toc24
SFDR (dBc)7050602030401090
0dBFS
-6dBFS
-12dBFS
SINGLE-ENDED
CLOCK DRIVE
MAX5854Dual, 10-Bit, 165Msps, Current-Output DAC
Typical Operating Characteristics (continued)

Partno	Mfg	Dc	Qty	Available	Descript
MAX5854ETL+T	MAXIM	N/a	7	avai	Dual, 10-Bit, 165Msps, Current-Output DAC