MAX5593EUI+ ,Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACsFeaturesThe MAX5590–MAX5595 octal, 12/10/8-bit, voltage-out-♦ Octal, 12/10/8-Bit Serial DACs in TSS ..
MAX560CAI ,+3.3V Transceiver with Wow EIA/TIA-562 Receivers Active in ShutdownFeatures
. 2 Receivers Active In Shutdown Mode (MAX560)
. Small 28-pin SSOP Package - 40% the A ..
MAX560CAI ,+3.3V Transceiver with Wow EIA/TIA-562 Receivers Active in ShutdownELECTRICAL CHARACTERISTICS
(Vcc = +3.0V to +3.6V, C1 - C4 = IPF, TA = 0'C to +70°C, unless other ..
MAX560CAI ,+3.3V Transceiver with Wow EIA/TIA-562 Receivers Active in ShutdownApplications T
. 4 Drlvers/5 Receivers
. Low-Power Shutdown:
<8PA MAX560
<1PA MAX561
t ..
MAX560CAI+ ,3.3V Transceiver with Two EIA TIA 562 Receivers Active in ShutdownApplications MAX561CAI 0''C to +70°C 28 SSOP
MAX561C/D 0'C to +70°C Dice'
Laptop Computers
Palmt ..
MAX560CWI ,+3.3V Transceiver with Wow EIA/TIA-562 Receivers Active in ShutdownApplications MAX561CAI 0''C to +70°C 28 SSOP
MAX561C/D 0'C to +70°C Dice'
Laptop Computers
Palmt ..
MAZ8024 ,Small-signal deviceelectrical characteristicswithin part numbersReverse current I V Specified value µ AR R*3Temperatur ..
MAZ8027-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8027-L ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8030-H ,Silicon planar typeelectrical characteristicsZ Zwithin part numbersReverse current I V ··············· Specified value ..
MAZ8030-L ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8033-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAX5590BEUG+-MAX5591BEUI+-MAX5592EUG+-MAX5593EUI+
Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs
General DescriptionThe MAX5590–MAX5595 octal, 12/10/8-bit, voltage-out-
put digital-to-analog converters (DACs) offer buffered
outputs and a 3µs maximum settling time at the 12-bit
level. The DACs operate from a +2.7V to +5.25V analog
supply and a separate +1.8V to +5.25V digital supply.
The 20MHz 3-wire serial interface is compatible with
SPI™, QSPI™, MICROWIRE™, and digital signal
processor (DSP) protocol applications. Multiple devices
can share a common serial interface in direct-access or
daisy-chained configuration. The MAX5590–MAX5595
provide two multifunction, user-programmable, digital
I/O ports. The externally selectable power-up states of
the DAC outputs are either zero scale, midscale, or full
scale. Software-selectable FAST and SLOW settling
modes decrease settling time in FAST mode, or reduce
supply current in SLOW mode.
The MAX5590/MAX5591 are 12-bit DACs, the MAX5592/
MAX5593 are 10-bit DACs, and the MAX5594/
MAX5595 are 8-bit DACs. The MAX5590/MAX5592/
MAX5594 provide unity-gain-configured output buffers,
while the MAX5591/MAX5593/MAX5595 provide force-
sense-configured output buffers. The MAX5590–
MAX5595 are specified over the extended -40°C to
+85°C temperature range, and are available in space-
saving 24-pin and 28-pin TSSOP packages.
ApplicationsPortable Instrumentation
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Automatic Tuning
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Controls
Motion Control
Microprocessor (µP)-Controlled Systems
Power Amplifier Control
Fast Parallel-DAC to Serial-DAC Upgrades
FeaturesOctal, 12/10/8-Bit Serial DACs in TSSOP Packages3µs (max) 12-Bit Settling Time to 1/2 LSBIntegral Nonlinearity:
1 LSB (max) MAX5590/MAX5591 A-Grade (12-Bit)
1 LSB (max) MAX5592/MAX5593 (10-Bit)
1/2 LSB (max) MAX5594/MAX5595 (8-Bit)Guaranteed Monotonic, ±1 LSB (max) DNLTwo User-Programmable Digital I/O PortsSingle +2.7V to +5.25V Analog Supply+1.8V to AVDDDigital Supply20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSP-
Compatible Serial InterfaceGlitch-Free Outputs Power Up to Zero Scale,
Midscale, or Full Scale Controlled by PU PinUnity-Gain or Force-Sense-Configured Output
Buffers
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
Ordering Information19-2983; Rev 3; 1/10
*Future product—contact factory for availability. Specifications
are preliminary.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide and Pin Configurations appear at end of data
sheet.
EVALUATION KIT
AVAILABLESPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PARTTEMP RANGEPIN-PACKAGE
MAX5590AEUG+*-40°C to +85°C24 TSSOP
MAX5590BEUG+-40°C to +85°C24 TSSOP
MAX5591AEUI+*-40°C to +85°C28 TSSOP
MAX5591BEUI+-40°C to +85°C28 TSSOP
MAX5592EUG+-40°C to +85°C24 TSSOP
MAX5593EUI+-40°C to +85°C28 TSSOP
MAX5594EUG+-40°C to +85°C24 TSSOP
MAX5595EUI+-40°C to +85°C28 TSSOP
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, VAGND= 0V, VDGND= 0V, VREF= 2.5V (for AVDD= 2.7V to 5.25V), VREF= 4.096V (for
AVDD= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto DVDD........................................................................±6V
AGND to DGND..................................................................±0.3V
AVDDto AGND, DGND.............................................-0.3V to +6V
DVDDto AGND, DGND............................................-0.3V to +6V
FB_, OUT_,
REF to AGND........-0.3V to the lower of (AVDD + 0.3V) or +6V
SCLK, DIN, CS, PU,
DSPto DGND.......-0.3V to the lower of (DVDD + 0.3V) or +6V
UPIO1, UPIO2
to DGND...............-0.3V to the lower of (DVDD + 0.3V) or +6V
Maximum Current into Any Pin.........................................±50mA
Continuous Power Dissipation (TA= +70°C)
24-Pin TSSOP (derate 13.9mW/°C above +70°C).....1111mW
28-Pin TSSOP (derate 14mW/°C above +70°C)........1117mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature.....................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC ACCURACYMAX5590/MAX559112
MAX5592/MAX559310ResolutionN
MAX5594/MAX55958
Bits
MAX5590A/MAX5591A (12-bit)±1
MAX5590B/MAX5591B (12-bit)±2±4
MAX5592/MAX5593 (10-bit)±0.5±1
Integral NonlinearityINL
VREF = 2.5V at
AVDD = 2.7V and
VREF = 4.096V at
AVDD = 5.25V
(Note 2)MAX5594/MAX5595 (8-bit)±0.125±0.5
LSB
Differential NonlinearityDNLGuaranteed monotonic (Note 2)±1LSBAX 5590A/M AX 5591A ( 12- b i t) , d eci m al cod e = 40±5AX 5590B/M AX 5591B ( 12- b i t) , d eci m al cod e = 40±5±25
MAX5592/MAX5593 (10-bit), decimal code = 10±5±25Offset ErrorVOS
MAX5594/MAX5595 (8-bit), decimal code = 3±5±25
Offset-Error Drift5ppm of
FS/°C
MAX5590A/MAX5591A (12-bit)±4
MAX5590B/MAX5590B (12-bit)±20±40
MAX5592/MAX5593 (10-bit)±5±10Gain ErrorGEFull-scale output
MAX5594/MAX5595 (8-bit)±2±3
LSB
Gain-Error Drift1ppm of
FS/°C
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, VAGND= 0V, VDGND= 0V, VREF= 2.5V (for AVDD= 2.7V to 5.25V), VREF= 4.096V (for
AVDD= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSPower-Supply Rejection
RatioPSRRFull-scale output, AVDD = 2.7V to 5.25V200µV/V
REFERENCE INPUTReference Input RangeVREF0.25AVDDV
Reference Input
ResistanceRREFNormal operation (no code dependence)145200kΩ
Reference Leakage
CurrentShutdown mode0.51µA
DAC OUTPUT CHARACTERISTICSUnity gain85SLOW mode, full scaleForce sense67
Unity gain140Output Voltage Noise
FAST mode, full scaleForce sense110
µVRMS
Unity-gain output0AVDDOutput Voltage Range
(Note 3)Force-sense output0AVDD / 2V
DC Output Impedance38Ω
AVDD = 5V, OUT_ to AGND, full scale, FAST mode57Short-Circuit CurrentAVDD = 3V, OUT_ to AGND, full scale, FAST mode45mA
Power-Up TimeFrom VDD applied until interface is functional3060µs
Wake-Up TimeComing out of shutdown, outputs settled40µs
Output OUT_ and FB_
Open-Circuit Leakage
Current
Programmed in shutdown mode, force-sense
outputs only0.01µA
DIGITAL OUTPUTS (UPIO_)Output High VoltageVOHISOURCE = 2mADVDD -
0.5V
Output Low VoltageVOLISINK = 2mA0.4V
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)DVDD ≥ 2.7V2.4
Input High VoltageVIHDVDD < 2.7V0.7 x
DVDD
DVDD > 3.6V0.8
2.7V ≤ DVDD ≤ 3.6V0.6Input Low VoltageVIL
DVDD < 2.7V0.2
Input Leakage CurrentIIN±0.1±1µA
Input CapacitanceCIN10pF
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, VAGND= 0V, VDGND= 0V, VREF= 2.5V (for AVDD= 2.7V to 5.25V), VREF= 4.096V (for
AVDD= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PU INPUTInput High VoltageVIH-PUDVDD -
200mVV
Input Low VoltageVIL-PU200mV
Input Leakage CurrentIIN-PUPU still considered unconnected when connected to
a tri-state bus±200nA
DYNAMIC PERFORMANCEFAST mode3.6Voltage-Output Slew
RateSRSLOW mode1.6V/µsAX 5590/M AX 5591 fr om cod e 322 to
cod e 4095 to 1/2 LS B23AX 5592/M AX 5593 fr om cod e 10 to
cod e 1023 to 1/2 LS B1.53FAST
mode
MAX5594/MAX5595 fr om cod e 3 to
code 255 to 1/2 LSB12AX 5590/M AX 5591 fr om cod e 322 to
cod e 4095 to 1/2 LS B36
MAX5592/MAX5593 fr om cod e 10 to
code 1023 1/2 LSB2.56
Voltage-Output Settling
Time (Note 5)
SLOW
mode
MAX5594/MAX5595 fr om cod e 3 to
code 255 to 1/2 LSB24
FB_ Input Voltage0VREF / 2V
FB_ Input Current0.1µA
Unity gain200Reference -3dB
Bandwidth (Note 6)Force sense150kHz
Digital FeedthroughCS = DVDD, code = zero scale, any digital input
from 0 to DVDD and DVDD to 0, f = 100kHz0.1nV-s
Digital-to-Analog Glitch
ImpulseMajor carry transition2nV-s
DAC-to-DAC Crosstalk(Note 4)15nV-s
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, VAGND= 0V, VDGND= 0V, VREF= 2.5V (for AVDD= 2.7V to 5.25V), VREF= 4.096V (for
AVDD= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTSAnalog Supply Voltage
RangeAVDD2.705.25V
Digital Supply Voltage
RangeDVDD1.8AVDDV
Unity gain1.53.2SLOW mode, all digital inputs
at DGND or DVDD, no load,
VREF = 4.096VForce sense2.44.8
Unity gain2.58
Operating Supply
Current
IAVDD
IDVDDFAST mode, all digital inputs
at DGND or DVDD, no load,
VREF = 4.096VForce sense3.48
Shutdown Supply
Current
IAV D D ( S H D N )
ID V D D ( S H D N )
No clocks, all digital inputs at DGND or DVDD, all
DACs in shutdown mode0.51µA
Note 1:For the force-sense versions, FB_ is connected to its respective OUT_. VOUT (max) = VREF / 2, unless otherwise noted.
Note 2:Linearity guaranteed from decimal code 40 to code 4095 for the MAX5590B/MAX5591B (12-bit, B-grade), code 10 to code
1023 for the MAX5592/MAX5593 (10-bit), and code 3 to code 255 for the MAX5594/MAX5595 (8-bit).
Note 3:Represents the functional range. The linearity is guaranteed at VREF= 2.5V (for AVDDfrom 2.7V to 5.25V), and VREF=
4.096V (for AVDD= 4.5V to 5.25V). See the Typical Operating Characteristicssection for linearity at other voltages.
Note 4:DC crosstalk is measured as follows: outputs of DACA–DACH are set to full scale and the output of DACH is measured.
While keeping DACH unchanged, the outputs of DACA–DACG are transitioned to zero scale and the ∆VOUTof DACH is
measured.
Note 5:Guaranteed by design.
Note 6:The reference -3dB bandwidth is measured with a 0.1VP-Psine wave on VREFand with full-scale input code.
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1)(DVDD= 2.7V to 5.25V, VAGND= 0V, VDGND= 0V, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCLK FrequencyfSCLK2.7V < DVDD < 5.25V20MHz
SCLK Pulse-Width HightCH(Note 7)20ns
SCLK Pulse-Width LowtCL(Note 7)20ns
CS Fall to SCLK Rise Setup TimetCSS10ns
SCLK Rise to CS Rise Hold TimetCSH5ns
SCLK Rise to CS Fall SetuptCS010ns
DIN to SCLK Rise Setup TimetDS12ns
DIN to SCLK Rise Hold TimetDH5ns
SCLK Rise to DOUTDC1 Valid
Propagation DelaytDO1CL = 20pF, UPIO_ = DOUTDC1 mode30ns
SCLK Fall to DOUT_ Valid
Propagation DelaytDO2CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode30ns
CS Rise to SCLK Rise Hold TimetCS1MICROWIRE and SPI modes 0 and 310ns
CS Pulse-Width HightCSW45ns
UPIO_ TIMING CHARACTERISTICSDOUT Tri-State Time when Exiting
DOUTDC0, DOUTDC1, and UPIO
Modes
tDOZCL = 20pF, from end of write cycle to UPIO_
in high impedance100ns
DOUTRB Tri-State Time from CS
RisetDRBZCL = 20pF, from rising edge of CS to UPIO_
in high impedance20ns
DOUTRB Tri-State Enable Time
from 8th SCLK RisetZENCL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state0ns
LDAC Pulse-Width LowtLDLFigure 520ns
LDAC Effective DelaytLDSFigure 6100ns
CLR, MID, SET Pulse-Width LowtCMSFigure 520ns
GPO Output Settling TimetGPFigure 6100ns
GPO Output High-Impedance
TimetGPZ100ns
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)(DVDD= 1.8V to 5.25V, VAGND= 0V, VDGND= 0V, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCLK FrequencyfSCLK1.8V < DVDD < 5.25V10MHz
SCLK Pulse-Width HightCH(Note 7)40ns
SCLK Pulse-Width LowtCL(Note 7)40ns
CS Fall to SCLK Rise Setup TimetCSS20ns
SCLK Rise to CS Rise Hold TimetCSH0ns
SCLK Rise to CS Fall SetuptCS010ns
DIN to SCLK Rise Setup TimetDS20ns
DIN to SCLK Rise Hold TimetDH5ns
SCLK Rise to DOUTDC1 Valid
Propagation DelaytDO1CL = 20pF, UPIO_ = DOUTDC1 mode60ns
SCLK Fall to DOUT_ Valid
Propagation DelaytDO2CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode60ns
CS Rise to SCLK Rise Hold TimetCS1MICROWIRE and SPI modes 0 and 320ns
CS Pulse-Width HightCSW90ns
UPIO_ TIMING CHARACTERISTICSDOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
tDOZCL = 20pF, from end of write cycle to UPIO_
in high impedance200ns
DOUTRB Tri-State Time from CS
RisetDRBZCL = 20pF, from rising edge of CS to UPIO_
in high impedance40ns
DOUTRB Tri-State Enable Time
from 8th SCLK RisetZENCL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state0ns
LDAC Pulse-Width LowtLDLFigure 540ns
LDAC Effective DelaytLDSFigure 6200ns
CLR, MID, SET Pulse-Width LowtCMSFigure 540ns
GPO Output Settling TimetGPFigure 6200ns
GPO Output High-Impedance
TimetGPZ200ns
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2)(DVDD= 2.7V to 5.25V, VAGND= 0V, VDGND= 0V, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCLK FrequencyfSCLK2.7V < DVDD < 5.25V20MHz
SCLK Pulse-Width HightCH(Note 7)20ns
SCLK Pulse-Width LowtCL(Note 7)20ns
CS Fall to SCLK Fall Setup TimetCSS10ns
DSP Fall to SCLK Fall Setup TimetDSS10ns
SCLK Fall to CS Rise Hold TimetCSH5ns
SCLK Fall to CS Fall DelaytCS010ns
SCLK Fall to DSP Fall DelaytDS010ns
DIN to SCLK Fall Setup TimetDS12ns
DIN to SCLK Fall Hold TimetDH5ns
SCLK Rise to DOUT_ Valid
Propagation DelaytDO1CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode30ns
SCLK Fall to DOUT_ Valid
Propagation DelaytDO2CL = 20pF, UPIO_ = DOUTDC0 mode30ns
CS Rise to SCLK Fall Hold TimetCS1MICROWIRE and SPI modes 0 and 310ns
CS Pulse-Width HightCSW45ns
DSP Pulse-Width HightDSW20ns
DSP Pulse-Width LowtDSPWL(Note 8)20ns
UPIO_ TIMING CHARACTERISTICSDOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
tDOZCL = 20pF, from end of write cycle to UPIO_
in high impedance100ns
DOUTRB Tri-State Time from CS
RisetDRBZCL = 20pF, from rising edge of CS to UPIO_
in high impedance20ns
DOUTRB Tri-State Enable Time
from 8th SCLK FalltZENCL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state0ns
LDAC Pulse-Width LowtLDLFigure 520ns
LDAC Effective DelaytLDSFigure 6100ns
CLR, MID, SET Pulse-Width LowtCMSFigure 520ns
GPO Output Settling TimetGPFigure 6100ns
GPO Output High-Impedance
TimetGPZ100ns
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)(DVDD= 1.8V to 5.25V, VAGND= 0V, VDGND= 0V, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCLK FrequencyfSCLK1.8V < DVDD < 5.25V10MHz
SCLK Pulse-Width HightCH(Note 7)40ns
SCLK Pulse-Width LowtCL(Note 7)40ns
CS Fall to SCLK Fall Setup TimetCSS20ns
DSP Fall to SCLK Fall Setup TimetDSS20ns
SCLK Fall to CS Rise Hold TimetCSH0ns
SCLK Fall to CS Fall DelaytCS010ns
SCLK Fall to DSP Fall DelaytDS015ns
DIN to SCLK Fall Setup TimetDS20ns
DIN to SCLK Fall Hold TimetDH5ns
SCLK Rise to DOUT_ Valid
Propagation DelaytDO1CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode60ns
SCLK Fall to DOUT_ Valid
Propagation DelaytDO2CL = 20pF, UPIO_ = DOUTDC0 mode60ns
CS Rise to SCLK Fall Hold TimetCS1MICROWIRE and SPI modes 0 and 320ns
CS Pulse-Width HightCSW90ns
DSP Pulse-Width HightDSW40ns
DSP Pulse-Width LowtDSPWL(Note 8)40ns
UPIO_ TIMING CHARACTERISTICSDOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
tDOZCL = 20pF, from end of write cycle to UPIO_
in high impedance200ns
DOUTRB Tri-State Time from CS
RisetDRBZCL = 20pF, from rising edge of CS to UPIO_
in high impedance40ns
DOUTRB Tri-State Enable Time
from 8th SCLK FalltZENCL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state0ns
LDAC Pulse-Width LowtLDLFigure 540ns
LDAC Effective DelaytLDSFigure 6200ns
CLR, MID, SET Pulse-Width LowtCMSFigure 540ns
GPO Output Settling TimetGPFigure 6200ns
GPO Output High-Impedance
TimetGPZ200ns
Note 7:In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-
lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns
(2.7V) or 50ns (1.8V).
Note 8:The falling edge of DSPstarts a DSP-type bus cycle, provided that CSis also active low to select the device. DSPactive low
and CSactive low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CScan be permanently low in this mode of
operation.
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs1024204830724095
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)MAX5590-95 toc01
DIGITAL INPUT CODE
INL (LSB)
B-GRADE
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
MAX5590-95 toc02
DIGITAL INPUT CODE
INL (LSB)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
MAX5590-95 toc03
DIGITAL INPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
MAX5590-95 toc04
DIGITAL INPUT CODE
DNL (LSB)
B-GRADE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
MAX5590-95 toc05
DIGITAL INPUT CODE
DNL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
MAX5590-95 toc06
DIGITAL INPUT CODE
DNL (LSB)
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE (12-BIT)
MAX5590-95 toc07
VREF (V)
INL (LSB)
B-GRADE
MIDSCALE-0.5
DIFFERENTIAL NONLINEARITY
vs. REFERENCE VOLTAGE (12-BIT)
MAX5590-95 toc08
VREF (V)
DNL (LSB)
B-GRADE
MIDSCALE
INTEGRAL NONLINEARITY
vs. TEMPERATURE (12-BIT)
MAX5590-95 toc09
TEMPERATURE (°C)
INL (LSB)
B-GRADE
MIDSCALE
Typical Operating Characteristics(AVDD= DVDD= 5V, VREF= 4.096V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = unconnected, TA= +25°C, unless otherwise
noted.)
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACsDIFFERENTIAL NONLINEARITY
vs. TEMPERATURE (12-BIT)
MAX5590-95 toc10
TEMPERATURE (°C)
DNL (LSB)
B-GRADE
MIDSCALE1024204830724095
SUPPLY CURRENT
vs. DIGITAL INPUT CODE (FORCE-SENSE)MAX5590-95 toc11
DIGITAL INPUT CODE
SUPPLY CURRENT (mA)
12-BIT
NO LOAD1024204830724095
SUPPLY CURRENT
vs. DIGITAL INPUT CODE (UNITY GAIN)MAX5590-95 toc12
DIGITAL INPUT CODE
SUPPLY CURRENT (mA)
12-BIT
NO LOAD
SUPPLY CURRENT
vs. SUPPLY VOLTAGE (FORCE-SENSE)
MAX5590-95 toc13
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SLOW MODE
FAST MODE
AVDD = DVDD
NO LOAD
SUPPLY CURRENT
vs. SUPPLY VOLTAGE (UNITY GAIN)
MAX5590-95 toc14
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
AVDD = DVDD
NO LOAD
SLOW MODE
FAST MODE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5590-95 toc15
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (nA)
NO LOAD
FORCE SENSE
UNITY GAIN
OFFSET ERROR vs. TEMPERATURE
MAX5590-95 toc16
TEMPERATURE (°C)
OFFSET ERROR (LSB)
CODE = 40
UNITY GAIN: 1 LSB = 1mV
FORCE SENSE: 1 LSB = 0.5mV
UNITY GAIN
FORCE SENSE
GAIN ERROR vs. TEMPERATURE
MAX5590-95 toc17
TEMPERATURE (°C)
GAIN ERROR (LSB)
FORCE SENSE
UNITY GAIN
UNITY GAIN: 1 LSB = 1mV
FORCE SENSE: 1 LSB = 0.5mV0
OUTPUT VOLTAGE
vs. OUTPUT SOURCE/SINK CURRENT
MAX5590-95 toc18
IOUT (mA)
OUTPUT VOLTAGE (V)
UNITY GAIN
VREF = 4.096V
MIDSCALE
Typical Operating Characteristics (continued)(AVDD= DVDD= 5V, VREF= 4.096V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = unconnected, TA= +25°C, unless otherwise
noted.)
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
MAJOR-CARRY TRANSITION GLITCH MAX5590-95 toc19
250ns/div
OUT_
2mV/div
5V/div
SETTLING TIME POSITIVE MAX5590-95 toc20
400ns/div
OUT_
2V/div
5V/div
FULL-SCALE
TRANSITION
SETTLING TIME NEGATIVE MAX5590-95 toc21
400ns/div
OUT_
2V/div
5V/div
FULL-SCALE
TRANSITION
-2510010001010,000
REFERENCE INPUT BANDWIDTHMAX5590-95 toc22
FREQUENCY (kHz)
GAIN (dB)
VREF = 0.1VP-P AT 4.096VDC
UNITY GAIN
REFERENCE FEEDTHROUGH AT 1kHzMAX5590-95 toc23
FREQUENCY (kHz)
SIGNAL AMPLITUDE (dB)
0.55.5200μs/div
DAC-TO-DAC CROSSTALKOUTH
1mV/div
OUTA–OUTG
2V/div
MAX5590-95 toc24
Typical Operating Characteristics (continued)(AVDD= DVDD= 5V, VREF= 4.096V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = unconnected, TA= +25°C, unless otherwise
noted.)
1μs/div
DIGITAL FEEDTHROUGHOUT_
(AC-COUPLED)
2mV/div
SCLK
2V/div
MAX5590-95 toc25
400μs/div
POWER-UP GLITCHOUT_
2V/div
AVDD
2V/div
MAX5590-95 toc26
PU = DVDD
10μs/div
EXITING SHUTDOWN TO MIDSCALEOUT_
2V/div
2V/div
MAX5590-95 toc27
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
Pin Description
PIN
MAX5590
MAX5592
MAX5594
MAX5591
MAX5593
MAX5595
NAMEFUNCTIONAVDDAnalog Supply2AGNDAnalog Ground3OUTADACA Output
4, 8, 17, 21—N.C.No Connection. Not internally connected.6OUTBDACB Output7OUTCDACC Output10OUTDDACD Output
911CSActive-Low Chip-Select Input12SCLKSerial Clock Input13DINSerial Data Input14DSP
Clock Enable. Connect DSP to DVDD at power-up to transfer data on the rising edge
of SCLK. Connect DSP to GND to transfer data on the falling edge of SCLK.
Connect DSP to DGND at power-up to transfer data on the falling edge of SCLK.15DVDDDigital Supply16DGNDDigital Ground17UPIO1User-Programmable Input/Output 118UPIO2User-Programmable Input/Output 219OUTEDACE Output22OUTFDACF Output23OUTGDACG Output26OUTHDACH Output27PU
Power-Up State Select Input. Connect PU to DVDD to set OUTA–OUTH to full scale
upon power-up. Connect PU to DGND to set OUTA–OUTH to zero upon power-up.
Leave PU unconnected at power-up to set OUTA–OUTH to midscale.28REFReference Input4FBAFeedback for DACA5FBBFeedback for DACB8FBCFeedback for DACC9FBDFeedback for DACD20FBEFeedback for DACE21FBFFeedback for DACF24FBGFeedback for DACG25FBHFeedback for DACH
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
Functional DiagramsMAX5590
MAX5592
MAX5594
DOUT
REGISTER
16-BIT SHIFT
REGISTER
SCLK
DIN
DSP
SERIAL
INTERFACE
CONTROL
MUX
AVDD
UPIO1
UPIO2
REF
UPIO1 AND
UPIO2
LOGICPOWER-DOWN
LOGIC AND
REGISTER
DECODE
CONTROL
INPUT
REGISTER
DAC
REGISTER
DACA
OUTA
INPUT
REGISTER
DACH
OUTH
DAC
REGISTER
DVDDAGNDDGND
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
Functional Diagrams (continued)MAX5591
MAX5593
MAX5595
DOUT
REGISTER
16-BIT SHIFT
REGISTER
SCLK
DIN
DSP
SERIAL
INTERFACE
CONTROL
MUX
AVDD
UPIO1
UPIO2
REF
UPIO1 AND
UPIO2
LOGICPOWER-DOWN
LOGIC AND
REGISTER
DECODE
CONTROL
INPUT
REGISTER
DAC
REGISTER
DACA
OUTA
FBA
FBH
INPUT
REGISTER
DACH
OUTH
DAC
REGISTER
DVDDAGNDDGND
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
Detailed DescriptionThe MAX5590–MAX5595 octal, 12/10/8-bit, voltage-out-
put DACs offer buffered outputs and a 3µs maximum
settling time at the 12-bit level. The DACs operate from a
single 2.7V to 5.25V analog supply and a separate 1.8V
to AVDDdigital supply. The MAX5590–MAX5595 include
an input register and DAC register for each channel and
a 16-bit data-in/data-out shift register. The 3-wire serial
interface is compatible with SPI, QSPI, MICROWIRE, and
DSP applications. The MAX5590– MAX5595 provide two
user-programmable digital I/O ports, which are pro-
grammed through the serial interface. The externally
selectable power-up states of the DAC outputs are either
zero scale, midscale, or full scale.
Reference InputThe reference input, REF, accepts both AC and DC val-
ues with a voltage range extending from analog ground
(AGND) to AVDD. The voltage at REF sets the full-scale
output of the DACs. Determine the output voltage using
the following equations:
Unity-gain versions:
VOUT_= (VREFx CODE) / 2N
Force-sense versions (FB_ connected to OUT_):
VOUT= 0.5 x (VREFx CODE) / 2N
where CODE is the numeric value of the DAC’s binary
input code and N is the bits of resolution. For the
MAX5590/MAX5591, N = 12 and CODE ranges from 0
to 4095. For the MAX5592/MAX5593, N = 10 and
CODE ranges from 0 to 1023. For the MAX5594/
MAX5595, N = 8 and CODE ranges from 0 to 255.
Output BuffersThe DACA and DACH output-buffer amplifiers of the
MAX5590–MAX5595 are unity-gain stable with rail-to-
rail output voltage swings and a typical slew rate
of 3.6V/µs (FAST mode). The MAX5590/MAX5592/
MAX5594 provide unity-gain outputs, while the
MAX5591/MAX5593/MAX5595 provide force-sense out-
puts. For the MAX5591/MAX5593/MAX5595, access to
the output amplifier’s inverting input provides flexibility
in output gain setting and signal conditioning (see the
Applications Informationsection).
The MAX5590–MAX5595 offer FASTand SLOWsettling-
time modes. In the SLOW mode, the settling time is 6µs
(max), and the supply current is 3.2mA (max). In the
FAST mode, the settling time is 3µs (max), and the sup-
ply current is 8mA (max). See the Digital Interfacesection
for settling-time mode programming details.
Use the serial interface to set the shutdown output
impedance of the amplifiers to 1kΩor 100kΩfor the
MAX5590/MAX5592/MAX5594 and 1kΩor high imped-
ance for the MAX5591/MAX5593/MAX5595. The DAC
outputs can drive a 10kΩ(typ) load and are stable with
up to 500pF (typ) of capacitive load.
Power-On ResetAt power-up, all DAC outputs power up to full scale,
midscale, or zero scale, depending on the configuration
of the PU input. Connect PU to DVDDto set OUT_ to full
scale upon power-up. Connect PU to digital ground
(DGND) at power-up to set OUT_ to zero scale. Leave
PU unconnected to set OUT_ to midscale.
Digital InterfaceThe MAX5590–MAX5595 use a 3-wire serial interface
that is compatible with SPI, QSPI, MICROWIRE, and DSP
protocol applications (Figures 1 and 2). Connect DSPto
DVDDbefore power-up to clock data in on the rising
edge of SCLK. Connect DSPto DGND before power-up
to clock data in on the falling edge of SCLK. After power-
up, the device enters DSP frame-sync mode on the first
rising edge of DSP. Refer to the MAX5590–MAX5595
Programmer’s Handbookfor details.
The MAX5590–MAX5595 include a 16-bit input shift
register. The data is loaded into the input shift register
through the serial interface. The 16 bits can be sent in
two serial 8-bit packets or one 16-bit word (CSmust
remain low until all 16 bits are transferred). The data is
loaded MSB first. For the MAX5590/MAX5591, the 16
bits consist of 4 control bits (C3–C0) and 12 data bits
(D11–D0) (see Table 1). For the 10-bit MAX5592/
MAX5593 devices, D11–D2 are the data bits and D1
and D0 are sub-bits. For the 8-bit MAX5594/
MAX5595 devices, D11–D4 are the data bits and
D3–D0 are sub-bits. Set all sub-bits to zero for optimum
performance.
Each DAC channel includes two registers: an input reg-
ister and the DAC register. At power-up, the DAC out-
put is set according to the state of PU. The DACs are
double-buffered, which allows any of the following for
each channel:Loading the input register without updating the DAC
registerUpdating the DAC register from the input registerUpdating the input and DAC registers simultaneously
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
Table 1. Serial Write Data Format
MSB 16 BITS OF SERIAL DATALSB
CONTROL BITSDATA BITSC2C1C0D11D10D9D8D7D6D5D4D3D2D1D0
Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)
Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled)
SCLK
DIN
DOUTDC1*
DOUTDC0
DOUTRB*
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.
tCH
tDS
tCS0tDHtCSH
tDO1
tDO2
tCL
tCSWtCS1
DOUT VALID
DOUT VALID
tCSSD0C2C3
SCLK
DIN
DSP
DOUTDC0*
DOUTDC1
DOUTRB*
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
SEE THE DATA OUTPUT (DOUTRB, DOUTDC0, DOUTDC1) SECTION FOR DETAILS.
tCL
tDS
tCCS
tDSWtDSPWLtD02
tD01
tDH
tCS0
tCHC2C1D0
tCSH
tCSWtDSStCS1
tDS0
DOUT VALID
DOUT VALID
