MAX5582EUP+T ,Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACsapplications. Multiple ♦ +1.8V to AV Digital SupplyDDdevices can share a common serial interface in ..
MAX5583EUP ,+2.7 to +5.25 V, buffered, fast-settling, quad, 10-bit, voltage-output DACApplicationsINLOUTPUT BUFFER RESOLUTIONPortable InstrumentationPART (LSBCONFIGURATION (BITS)Automat ..
MAX5584EUP ,+2.7 to +5.25 V, buffered, fast-settling, quad, 8-bit, voltage-output DACapplications. Multiple♦ +1.8V to AV Digital SupplyDDdevices can share a common serial interface in ..
MAX5585EUP ,+2.7 to +5.25 V, buffered, fast-settling, quad, 8-bit, voltage-output DACELECTRICAL CHARACTERISTICS(AV = 2.7V to 5.25V, DV = 1.8V to AV , AGND = 0, DGND = 0, V = 2.5V (for ..
MAX5590BEUG ,Buffered / Fast-Settling / Octal / 12/10/8-Bit / Voltage-Output DACsELECTRICAL CHARACTERISTICS(AV = 2.7V to 5.25V, DV = 1.8V to AV , AGND = 0, DGND = 0, V = 2.5V (for ..
MAX5590BEUG+ ,Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACsApplicationsOrdering InformationPortable InstrumentationPART TEMP RANGE PIN-PACKAGEAutomatic Test E ..
MAZ3200 ,Small-signal deviceElectrical characteristics within part numbers T = 25°Ca• V = 2.0 V to 8.2 V (I = 5 mA)Z ZTemperat ..
MAZ3200-M ,Silicon planar typeZener DiodesMAZ3000 SeriesSilicon planar typeUnit : mm+ 0.22.8 − 0.3For stabilization of power supp ..
MAZ8024 ,Small-signal deviceelectrical characteristicswithin part numbersReverse current I V Specified value µ AR R*3Temperatur ..
MAZ8027-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8027-L ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8030-H ,Silicon planar typeelectrical characteristicsZ Zwithin part numbersReverse current I V ··············· Specified value ..
MAX5580BEUP+-MAX5582EUP+T
Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
General DescriptionThe MAX5580–MAX5585 quad, 12-/10-/8-bit, voltage-
output, digital-to-analog converters (DACs) offer
buffered outputs and a 3µs maximum settling time at the
12-bit level. The DACs operate from a +2.7V to +5.25V
analog supply and a separate +1.8V to +5.25V digital
supply. The 20MHz, 3-wire, serial interface is compati-
ble with SPI™, QSPI™, MICROWIRE™, and digital sig-
nal processor (DSP) protocol applications. Multiple
devices can share a common serial interface in direct-
access or daisy-chained configuration. The MAX5580–
MAX5585 provide two multifunctional, user-programma-
ble, digital I/O ports. The externally selectable power-up
states of the DAC outputs are either zero scale, mid-
scale, or full scale. Software-selectable FAST and SLOW
settling modes decrease settling time in FAST mode, or
reduce supply current in SLOW mode.
The MAX5580/MAX5581 are 12-bit DACs, the
MAX5582/MAX5583 are 10-bit DACs, and the
MAX5584/MAX5585 are 8-bit DACs. The MAX5580/
MAX5582/MAX5584 provide unity-gain-configured out-
put buffers, while the MAX5581/MAX5583/MAX5585
provide force-sense-configured output buffers. The
MAX5580–MAX5585 operate over the extended -40°C
to +85°C temperature range and are available in a
space-saving, 6.5mm x 4.4mm, 20-pin, TSSOP package.
Features3µs (max) 12-Bit Settling Time to 0.5 LSBQuad, 12-/10-/8-Bit Serial DACs in TSSOP
Package±1 LSB (max)INL and DNL at 12-Bit ResolutionTwo User-Programmable Digital I/O PortsSingle +2.7V to +5.25V Analog Supply+1.8V to AVDDDigital Supply20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSP-
Compatible Serial InterfaceGlitch-Free Outputs Power Up to Zero Scale,
Midscale, or Full Scale Controlled by PU PinUnity-Gain or Force-Sense-Configured
Output Buffers
ApplicationsPortable Instrumentation
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Automatic Tuning
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Controls
Motion Control
Microprocessor (µP)-Controlled Systems
Power Amplifier Control
Fast Parallel-DAC to Serial-DAC Upgrades
MAX5580–MAX5585
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs19-3164; Rev 4; 7/08
Pin Configuration appears at end of data sheet.
EVALUATION KIT
AVAILABLESPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PARTRESOLUTION
(BITS)
INL
(LSB max)
OUTPUT BUFFER
CONFIGURATIONPIN-PACKAGE
MAX5580AEUP+12±1Unity gain20 TSSOP-EP*
MAX5580BEUP+12±4Unity gain20 TSSOP-EP*
MAX5581AEUP+12±1Force sense20 TSSOP-EP*
MAX5581BEUP+12±4Force sense20 TSSOP-EP*
MAX5582EUP+10±1Unity gain20 TSSOP-EP*
MAX5583EUP+10±1Force sense20 TSSOP-EP*
MAX5584EUP+8±0.5Unity gain20 TSSOP-EP*
MAX5585EUP+8±0.5Force sense20 TSSOP-EP*
Ordering Information/Selector Guide+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed paddle.
Note:All devices are specified over the -40°C to +85°C operating temperature range.
MAX5580–MAX5585
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, VAGND= 0, VDGND= 0, VREF= 2.5V (for AVDD= 2.7V to 5.25V), VREF= 4.096V (for
AVDD= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto DVDD........................................................................±6V
AGND to DGND..................................................................±0.3V
AVDDto AGND, DGND.............................................-0.3V to +6V
DVDDto AGND, DGND............................................-0.3V to +6V
FB_, OUT_,
REF to AGND........-0.3V to the lower of (AVDD + 0.3V) or +6V
SCLK, DIN, CS, PU,
DSPto DGND.......-0.3V to the lower of (DVDD + 0.3V) or +6V
UPIO1, UPIO2
to DGND...............-0.3V to the lower of (DVDD + 0.3V) or +6V
Maximum Current into Any Pin.........................................±50mA
Continuous Power Dissipation (TA= +70°C)
20-Pin TSSOP (derate 21.7mW/°C above +70°C)........1739mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC ACCURACYMAX5580/MAX558112
MAX5582/MAX558310ResolutionN
MAX5584/MAX55858
Bits
MAX5580A/MAX5581A (12 bit)±1
MAX5580B/MAX5581B (12 bit)±2±4
MAX5582/MAX5583 (10 bit)±0.5±1
Integral NonlinearityINL
VREF = 2.5V at
AVDD = 2.7V and
VREF = 4.096V at
AVDD = 5.25V
(Note 2)MAX5584/MAX5585 (8 bit)±0.125±0.5
LSB
Differential NonlinearityDNLGuaranteed monotonic (Note 2)±1LSBAX 5580A/M AX 5581A ( 12 b i t) , d eci m al cod e = 250±5AX 5580B/M AX 5581B ( 12 b i t) , d eci m al cod e = 40±5±25
MAX5582/MAX5583 (10 bit), decimal code = 20±5±25Offset ErrorVOS
MAX5584/MAX5585 (8 bit), decimal code = 5±5±25
Offset-Error Drift5ppm of
FS/°C
MAX5580A, VREF = 4.096V±1±5
MAX5580A, VREF = 2.5V±1.5±7
MAX5581A, VREF = 4.096V±0.5±4
MAX5581A, VREF = 2.5V±1±5
MAX5580B/MAX5581B (12 bit)±20±40
MAX5582/MAX5583 (10 bit)±5±10
Gain ErrorGEFull-scale output
MAX5584/MAX5585 (8 bit)±2±3
LSB
Gain-Error Drift1ppm of
FS/°C
MAX5580–MAX5585
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, VAGND= 0, VDGND= 0, VREF= 2.5V (for AVDD= 2.7V to 5.25V), VREF= 4.096V (for
AVDD= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSPower-Supply Rejection
RatioPSRRFull-scale output, AVDD = 2.7V to 5.25V200µV/V
REFERENCE INPUTReference-Input RangeVREF0.25AVDDV
Reference-Input
ResistanceRREFNormal operation (no code dependence)145200kΩ
Reference Leakage
CurrentShutdown mode0.51µA
DAC OUTPUT CHARACTERISTICSUnity gain85SLOW mode, full scaleForce sense67
Unity gain140Output-Voltage Noise
FAST mode, full scaleForce sense110
µVRMS
Unity-gain output0AVDDOutput-Voltage Range
(Note 3)Force-sense output0AVDD / 2V
DC Output Impedance38Ω
AVDD = 5V, OUT_ to AGND, full scale, FAST mode57Short-Circuit CurrentAVDD = 3V, OUT_ to AGND, full scale, FAST mode45mA
Power-Up TimeFrom DVDD, applied until interface is functional3060µs
Wake-Up TimeComing out of shutdown, outputs settled40µs
Output OUT_ and FB_
Open-Circuit Leakage
Current
Programmed in shutdown mode, force-sense
outputs only0.01µA
DIGITAL OUTPUTS (UPIO_)Output High VoltageVOHISOURCE = 0.5mADVDD -
0.5V
Output Low VoltageVOLISINK = 2mA0.4V
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)DVDD ≥ 2.7V2.4
Input High VoltageVIHDVDD < 2.7V0.7 x
DVDD
DVDD > 3.6V0.8
2.7V ≤ DVDD ≤ 3.6V0.6Input Low VoltageVIL
DVDD < 2.7V0.2
Input Leakage CurrentIIN±0.1±1µA
Input CapacitanceCIN10pF
MAX5580–MAX5585
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, VAGND= 0, VDGND= 0, VREF= 2.5V (for AVDD= 2.7V to 5.25V), VREF= 4.096V (for
AVDD= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PU INPUTInput High VoltageVIH-PUDVDD -
200mVV
Input Low VoltageVIL-PU200mV
Input Leakage CurrentIIN-PUPU still considered floating when connected to a
tri-state bus±200nA
DYNAMIC PERFORMANCEFAST mode3.6Voltage-Output Slew
RateSRSLOW mode1.6V/µsAX 5580/M AX 5581 fr om cod e 322 to
cod e 4095 to 0.5 LS B23AX 5582/M AX 5583 fr om cod e 10 to
cod e 1023 to 0.5 LS B1.53FAST
mode
MAX5584/MAX5585 fr om cod e 3 to
code 255 to 0.5 LS B12AX 5580/M AX 5581 fr om cod e 322 to
cod e 4095 to 0.5 LS B36
MAX5582/MAX5583 fr om cod e 10 to
code 1023 0.5 LS B2.56
Voltage-Output Settling
Time (Note 4), Figure 5tS
SLOW
mode
MAX5584/MAX5585 fr om cod e 3 to
code 255 to 0.5 LS B24
FB_ Input Voltage0VREF / 2V
FB_ Input Current0.1µA
Unity gain200Reference -3dB
Bandwidth (Note 5)Force sense150kHz
Digital FeedthroughCS = DVDD, code = zero scale, any digital input
from 0 to DVDD and DVDD to 0, f = 100kHz0.1nV-s
Digital-to-Analog Glitch
ImpulseMajor carry transition2nV-s
DAC-to-DAC Crosstalk(Note 6)15nV-s
MAX5580–MAX5585
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, VAGND= 0, VDGND= 0, VREF= 2.5V (for AVDD= 2.7V to 5.25V), VREF= 4.096V (for
AVDD= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTSAnalog Supply Voltage
RangeAVDD2.705.25V
Digital Supply Voltage
RangeDVDD1.8AVDDV
Unity gain0.91.6SLOW mode, all digital inputs
at DGND or DVDD, no load,
VREF = 4.096VForce sense1.62.4
Unity gain1.64
Operating Supply
Current
IAVDD
IDVDDFAST mode, all digital inputs
at DGND or DVDD, no load,
VREF = 4.096VForce sense2.34
Shutdown Supply
Current
IAV D D ( S H D N )
ID V D D ( S H D N )
No clocks, all digital inputs at DGND or DVDD, all
DACs in shutdown mode0.51µA
Note 1:For the force-sense versions, FB_ is connected to its respective OUT_, and VOUT (max) = VREF / 2, unless otherwise noted.
Note 2:Linearity guaranteed from decimal code 250 to code 4095 for the MAX5580A/MAX5581A (12 bit, A grade), code 40 to code
4095 for the MAX5580B/MAX5581B (12 bit, B grade), code 20 to code 1023 for the MAX5582/MAX5583 (10 bit), and code 5
to code 255 for the MAX5584/MAX5585 (8 bit).
Note 3:Represents the functional range. The linearity is guaranteed at VREF= 2.5V (for AVDDfrom 2.7V to 5.25V), and VREF=
4.096V (for AVDD= 4.5V to 5.25V). See the Typical Operating Characteristicssection for linearity at other voltages.
Note 4:Guaranteed by design.
Note 5:The reference -3dB bandwidth is measured with a 0.1VP-Psine wave on VREFand with full-scale input code.
Note 6:DC crosstalk is measured as follows: outputs of DACA–DACD are set to full scale and the output of DACD is measured.
While keeping DACD unchanged, the outputs of DACA–DACC are transitioned to zero scale and the ∆VOUTof DACD
is measured.
