MAX5556ESA-MAX5556ESA+ Fast Delivery |IC PHOENIX CO.,LIMITED

MAX5556ESA ,Low-Cost Stereo Audio DACApplications● Digital Video Recorders and Media Servers● Set-Top Boxes● Video-Game HardwareTypical ..
MAX5556ESA+ ,Low-Cost Stereo Audio DACElectrical Characteristics(V = +4.75V to +5.5V, V = 0V, R _ = 10kΩ, C _ = 10pF, 0dBFS sine-wave sig ..
MAX555CQK ,300Msps, 12-Bit DAC with Complementary Voltage OutputsELECTRICAL CHARACTERISTICS(AV = DV = -5.2V, V = 1.000V, T to T = 0°C to +70°C, unless otherwise not ..
MAX5580AEUP ,Buffered / Fast-Settling / Quad / 12-/10-/8-Bit / Voltage-Output DACsApplicationsINLOUTPUT BUFFER RESOLUTIONPortable InstrumentationPART (LSBCONFIGURATION (BITS)Automat ..
MAX5580BEUP ,+2.7 to +5.25 V, buffered, fast-settling, quad, 12-bit, voltage-output DACFeaturesThe MAX5580–MAX5585 quad, 12-/10-/8-bit, voltage- ♦ 3µs (max) 12-Bit Settling Time to 0.5 L ..
MAX5580BEUP+ ,Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACsELECTRICAL CHARACTERISTICS(AV = 2.7V to 5.25V, DV = 1.8V to AV , V = 0, V = 0, V = 2.5V (for AV = 2 ..
MAZ3200 ,Small-signal deviceElectrical characteristics within part numbers T = 25°Ca• V = 2.0 V to 8.2 V (I = 5 mA)Z ZTemperat ..
MAZ3200-M ,Silicon planar typeZener DiodesMAZ3000 SeriesSilicon planar typeUnit : mm+ 0.22.8 − 0.3For stabilization of power supp ..
MAZ8024 ,Small-signal deviceelectrical characteristicswithin part numbersReverse current I V Specified value µ AR R*3Temperatur ..
MAZ8027-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8027-L ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8030-H ,Silicon planar typeelectrical characteristicsZ Zwithin part numbersReverse current I V ··············· Specified value ..

MAX5556ESA-MAX5556ESA+
Low-Cost Stereo Audio DAC
General Description
The MAX5556 stereo audio sigma-delta digital-to-analog
converter (DAC) offers a simple and complete stereo dig-
ital-to-analog solution for media servers, set-top boxes,
video-game hardware, and other general consumer audio
applications. This DAC features built-in digital interpo-
lation/filtering, sigma-delta digital-to-analog conversion,
and analog output filtering. Control logic and mute cir-
cuitry minimize audible pops and clicks during power-up,
power-down, clock changes, or when invalid clock condi-
tions occur.
The MAX5556 receives input data over a 3-wire
I2S-compatible interface with left-justified audio data.
Data can be clocked by either an external or internal
serial clock. The internal serial clock frequency is pro-
grammable by selection of a master clock (MCLK) and
sample clock (LRCLK) ratio. Sampling rates from 2kHz to
50kHz are supported.
The MAX5556 operates from a single +4.75V to +5.5V
analog supply with total harmonic distortion plus noise
below -87dB. This device is available in an 8-pin SO pack-
age and is specified over the -40°C to +85°C industrial
temperature range.
Applications●Digital Video Recorders and Media Servers●Set-Top Boxes●Video-Game Hardware
Features●Simple and Complete Stereo Audio DAC Solutions,
No Controls to Set●Sigma-Delta Stereo DACs with Built-In Interpolation
and Analog Output Filters●I2S-Compatible Digital Audio Interface●Clickless/Popless Operation●3.5VP-P Output Voltage Swing ●-87dB THD+N●+87dB Dynamic Range●Sample Frequencies (fS) from 2kHz to 50kHz●Master Clock (MCLK) up to 25MHz●Automatic Detection of Clock Ratio (MCLK/ LRCLK)
+Denotes a lead(Pb)-free/RoHS-compliant package. For leaded
version, contact factory.
*Contact factory for availability.
PARTTEMP
RANGE
PIN-
PACKAGEDATA FORMAT
MAX5556ESA+-40°C to
+85°C8 SOLeft-justified I2S
data
GND
OUTRMCLK
OUTL
VDDSCLK
LRCLK
SDATA
TOP VIEW
MAX5556
MCLK
LRCLK
SCLK
SDATA
GND
VDD
OUTR
OUTL
CLOCK
FILTER
FILTERDAC
DAC
+5V
LEFT
OUTPUT
RIGHT
OUTPUT
LINE-LEVEL
BUFFER
LINE-LEVEL
BUFFER
AUDIO
DECOMPRESSION
MAX5556
SERIAL
INTERFACE
MAX5556Low-Cost Stereo Audio DAC
Pin Coniguration
Ordering Information
Typical Operating Circuit
EVALUATION KIT AVAILABLE
VDD to GND .........................................................-0.3V to +6.0V
OUTL, OUTR, SDATA to GND ................ -0.3V to (VDD + 0.3V)
Current Any Pin (excluding VDD and GND) .....................±10mA
OUTL, OUTR Shorted to GND ..............................Continuous
SCLK, LRCLK, MCLK to GND .............................-0.3V to +6.0V
Continuous Power Dissipation (TA = +70°C)8-Pin SO (derate 5.88mW/°C above +70°C) ...............471mW
Package Thermal Resistance (θJA) ..............................170°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
(VDD = +4.75V to +5.5V, VGND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, 0dBFS sine-wave signal at 997Hz, fLRCLK (fS) = 48kHz, fMCLK
= 12.288MHz, measurement bandwidth 10Hz to 20kHz, TA = -40°C to +85°C, outputs are unloaded, unless otherwise noted. Typical
values at VDD = +5V, TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLY
Supply VoltageVDD4.755.05.50V
Supply CurrentIDDUp to 48ksps1315mAStatic digital68.5
Power DissipationUp to 48ksps6582.5mWStatic digital3044
DYNAMIC PERFORMANCE (Note 2)
Dynamic Range, 16-BitUnweighted 8486dBA-weighted8690
Dynamic Range, 18-Bit to 24-BitUnweighted87dBA-weighted91
Total Harmonic Distortion Plus
Noise, 16-BitTHD+N
0dBFS-86-81-20dBFS-67
-60dBFS-26-24
Total Harmonic Distortion Plus
Noise, 18-Bit to 24-BitTHD+N
0dBFS-87-20dBFS-68
-60dBFS-27
Interchannel Isolation1kHz full-scale output (crosstalk)94dB
COMBINED DIGITAL AND INTEGRATED ANALOG FILTER FREQUENCY RESPONSE (Note 3)
Passband
-0.5dB corner0.46-3dB corner 0.49
-6dB corner 0.50
Frequency Response/Passband
Ripple
10Hz to 20kHz (fS = 48kHz)-0.025+0.0810Hz to 20kHz (fS = 44.1kHz)-0.025+0.08
10Hz to 16kHz (fS = 32kHz)-6.000+0.073
Stopband0.5465fS
Stopband Attenuation52dB
Group Delaytgd20/fSs
MAX5556Low-Cost Stereo Audio DAC
Electrical Characteristics
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
(VDD = +4.75V to +5.5V, VGND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, 0dBFS sine-wave signal at 997Hz, fLRCLK (fS) = 48kHz, fMCLK
= 12.288MHz, measurement bandwidth 10Hz to 20kHz, TA = -40°C to +85°C, outputs are unloaded, unless otherwise noted. Typical
values at VDD = +5V, TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC CHARACTERISTICS
Interchannel Gain Mismatch0.10.4dB
Gain Error-5+5%
Gain Drift100ppm/°C
ANALOG OUTPUTS
Full-Scale Output VoltageVOUTR, VOUTL
VOUTL3.253.53.75VP-P
DC Quiescent Output VoltageVQInput code = 02.4V
Minimum Load ResistanceRL3kΩ
Maximum Load CapacitanceCL100pF
Power-Supply Rejection RatioPSRRVRIPPLE = 100mVP-P, frequency = 1kHz
(Note 4)66dB
POP AND CLICK SUPPRESSION
Mute Attenuation100dB
Power-Up Until Bias EstablishedFigure 11360ms
Valid Clock to Normal OperationSoft-start ramp time, Figure 12 (Note 5)20ms
DIGITAL AUDIO INTERFACE (SCLK, SDATA, MCLK, LRCLK)
Input-Voltage HighVIH2.0V
Input-Voltage LowVIL0.8V
Input Leakage CurrentIIN-10+10µA
Input Capacitance8pF
TIMING CHARACTERISTICS
Input Sample RatefS250kHz
MCLK Pulse-Width LowtMCLKL
MCLK/LRCLK = 51210MCLK/LRCLK = 38420
MCLK/LRCLK = 25620
MCLK Pulse-Width HightMCLKH
MCLK/LRCLK = 51210MCLK/LRCLK = 38420
MCLK/LRCLK = 25620
EXTERNAL SCLK MODE
LRCLK Duty Cycle(Note 6)2575%
SCLK Pulse-Width LowtSCLKL20ns
SCLK Pulse-Width HightSCLKH20ns
SCLK PeriodtSCLK1/(128
x fS)ns
LRCLK Edge to SCLK Rising
Setup TimetSLRS20ns
LRCLK Edge to SCLK Rising
Hold TimetSLRH20ns
SDATA Valid to SCLK Rising
Setup TimetSDS20ns
MAX5556Low-Cost Stereo Audio DAC
Electrical Characteristics (continued)
Note 1: 100% production tested at TA = +85°C. Limits to -40°C are guaranteed by design.
Note 2: 0.5 LSB of triangular PDF dither added to data.
Note 3: Guaranteed by design, not production tested.
Note 4: PSRR test block diagram shown in Figure 1 denotes the test setup used to measure PSRR.
Note 5: Volume ramping interval starts from establishment of a valid MCLK to LRCLK ratio. Total time is proportional to the sample
rate (fS). 20ms based on 48ksps operation.
Note 6: In external SCLK mode, LRCLK duty cycles are not limited, provided all data formatting requirements are met. See Figure 4.
Note 7: The LRCLK duty cycle must be 50% ±1/2 MCLK period in internal SCLK mode.
Note 8: The SCLK/LRCLK ratio can be set to 32, 48, or 64, depending on the MCLK/LRCLK ratio selected. See Figure 4.
(VDD = +4.75V to +5.5V, VGND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, 0dBFS sine-wave signal at 997Hz, fLRCLK (fS) = 48kHz, fMCLK
= 12.288MHz, measurement bandwidth 10Hz to 20kHz, TA = -40°C to +85°C, outputs are unloaded, unless otherwise noted. Typical
values at VDD = +5V, TA = +25°C.) (Note 1)
Figure 1. PSRR Test Block Diagram
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERNAL SCLK MODE
LRCLK Duty Cycle(Note 7)50%
Internal SCLK PeriodtISCLK(Note 8)1/fSCLKns
LRCLK Edge to Internal SCLK
Rising Delay TimetISCLKRtISCLK/2ns
SDATA Valid to Internal SCLK
Rising Setup Time
tISDSMCLK period = tMCLKtMCLK + 10ns
tISDHtMCLK
MCLK
SDATA
LRCLK
SCLK
ACTIVE CLOCKS
GND
VDD
SPECTRUM
ANALYZER
LOUT, ROUTZGAUDIO SIGNAL
GENERATOR
(100mVP-P AT 1kHz)
DC POWER SUPPLY
(5VDC)
MAX5556
MAX5556Low-Cost Stereo Audio DAC
Electrical Characteristics (continued)
(VDD = +5V, VGND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, TA = +25°C, unless otherwise noted.)
THD+N vs. AMPLITUDE
MAX5556 toc09
AMPLITUDE (dBFS)
THD+N (dBr)
UNWEIGHTED
A-WEIGHTED
INPUT = 1kHz 18-BIT SIGNAL
INTEGRATION BANDWIDTH = 20Hz TO 20kHz
FREQUENCY (kHz)
AMPLITUDE (dBr)
TWIN-TONE IMD FFT
MAX5556 toc08
16,000-SAMPLE FFT
WITH 13kHz AND
14kHz INPUT SIGNALS
FREQUENCY (kHz)
AMPLITUDE (dBr)
IDLE-CHANNEL NOISE FFT
MAX5556 toc07
16,000-SAMPLE FFT WITH NO INPUT
FREQUENCY (kHz)
AMPLITUDE (dBr)
-60dBFS FFT
MAX5556 toc06
16,000-SAMPLE FFT USING 1kHz INPUT
FREQUENCY (kHz)
AMPLITUDE (dBr)
0dBFS FFT
MAX5556 toc05
16,000-SAMPLE FFT USING 1kHz INPUT
PASSBAND RIPPLE
MAX5556 toc04
FREQUENCY (NORMALIZED TO fS)
AMPLITUDE (dB)
TRANSITION BAND DETAIL
MAX5556 toc03
FREQUENCY (NORMALIZED TO fS)
AMPLITUDE (dB)
TRANSITION BAND
MAX5556 toc02
FREQUENCY (NORMALIZED TO fS)
AMPLITUDE (dB)
STOPBAND REJECTION
MAX5556 toc01
FREQUENCY (NORMALIZED TO fS)
AMPLITUDE (dB)
MAX5556Low-Cost Stereo Audio DAC
Typical Operating Characteristics
(VDD = +5V, VGND = 0V, ROUT_ = 10kΩ, COUT_ = 10pF, TA = +25°C, unless otherwise noted.)
100ms/div
POWER-UP RESPONSE
VOUT
1V/div
MAX5556 toc15
5ms/div
CLOCK-LOSS MUTE RECOVERY
VOUT
1V/div2.4V
MAX5556 toc14
CLOCK
RESTORED
LOSS
OF CLOCK1.01.50.52.02.53.03.54.04.55.05.5
SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE (VDIG)
MAX5556 toc13
DIGITAL INPUT VOLTAGE (VDIG) (V)
SUPPLY CURRENT (mA)
VIH
VDIG < VIH
MUTE
ENGAGED
VDD = +5.5V
DC OUTPUT
VDIG < VIH
NORMAL OPERATION
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5556 toc12
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
INPUT = 1kHz, 0dBFS SIGNAL
NORMAL OPERATION
STATIC DIGITAL INPUT
MUTE OPERATION2010304050
POWER DISSIPATION
vs. SAMPLE FREQUENCY
MAX5556 toc11
SAMPLE FREQUENCY (kHz)
POWER DISSIPATION (mW)
VDD = +5V
INPUT = 1kHz, 0dBFS SIGNAL-110
UNWEIGHTED THD+N
vs. FREQUENCY
MAX5556 toc10
FREQUENCY (kHz)
THD+N (dBr)
INPUT = 1kHz 18-BIT SIGNAL,
INTEGRATION BANDWIDTH = 20Hz TO 20kHz
MAX5556Low-Cost Stereo Audio DAC
Typical Operating Characteristics
Detailed Description
The MAX5556 stereo audio sigma-delta DAC offers a
complete stereo digital-to-analog system for consumer
audio applications. The MAX5556 features built-in digital
interpolation/filtering, sigma-delta digital-to-analog con-
version and analog output filters (Figure 2). Control logic
and mute circuitry minimize audible pops and clicks dur-
ing power-up, power-down, and whenever invalid clock
conditions occur.
This stereo audio DAC receives input data over a 3-wire
I2S-compatible interface. The MAX5556 accepts left-
justified I2S data of 16 or 24 bits. This DAC also sup-
ports a wide range of sample rates from 2kHz to 50kHz.
Direct analog output data is routed to the right or left
output by driving LRCLK high or low. See the Clock and
Data Interface section.
The MAX5556 supports MCLK/LRCLK ratios of 256,
384, or 512. This device allows a change to the clock
speed ratio without causing glitches on the analog out-
puts by internally muting the audio during invalid clock
conditions. The internal mute function ramps down the
audio amplitude and forces the analog outputs to a
2.4V quiescent voltage immediately upon clock loss or
change of ratio. A soft-start routine is then engaged
when a valid clock ratio is re-established, producing
clickless and popless continuous operation.
The MAX5556 operates from a +4.75V to +5.5V analog
supply and features +87dB dynamic range with total har-
monic distortion typically below -87dB.
Interpolator
The digital interpolation filter eliminates images of the
baseband audio signal that exist at multiples of the input
sample rate (fS). The resulting upsampled frequency
spectrum has images of the input signal at multiples of 8
x fS. An additional upsampling sinc filter further reduces
upsampling images up to 64 x fS. These images are ulti-
mately removed through the internal analog lowpass filter
and the external analog output filter.
Sigma-Delta Modulator/DAC
The MAX5556 uses a multibit sigma-delta DAC with an
oversampling ratio (OSR) of 64 to achieve a wide dynamic
range. The sigma-delta modulator accepts a 3-bit data
stream from the interpolation filter at a rate of 64 x fS (fS =
LRCLK frequency) and provides an analog voltage repre-
sentation of that data stream.
PINNAMEFUNCTIONSDATA
Serial Audio Data Input. Data is clocked into the MAX5556 on the rising edge of the internal or external SCLK. Data is input in two’s complement format, MSB irst. The state of LRCLK determines
whether data is directed to OUTL or OUTR.SCLKExternal Serial-Clock Input. Data is strobed on the rising edge of SCLK.LRCLKLeft-/Right-Channel Select Clock. Drive LRCLK low to direct data to OUTL or LRCLK high to direct
data to OUTR.MCLKMaster Clock Input. The MCLK/LRCLK ratio must equal to 256, 384, or 512.OUTRRight-Channel Analog OutputGNDGroundVDDPower-Supply Input. Bypass VDD to GND with a 0.1µF capacitor in parallel with a 4.7µF capacitor as
close to VDD as possible. Place the 0.1µF capacitor closest to VDD.OUTLLeft-Channel Analog Output
MAX5556Low-Cost Stereo Audio DAC
Pin Description
Integrated Analog Lowpass Filter
The DAC output of the sigma-delta modulator is followed by
an analog smoothing filter that attenuates high-frequency
quantization noise. The corner frequency of the filter is
Integrated Analog Output Buffer
Following the analog lowpass filter, the analog signal is
routed through internal buffers to OUTR and OUTL. The
buffer can directly drive load resistances larger than 3kΩ
Figure 3. Load-Impedance Operating Region
Figure 2. Functional Diagram
LOAD RESISTANCE RL (k)101520
SAFE OPERATING REGION
LOAD CAP
ACIT
ANCE C
L (pF)
INTERPOLATORSIGMA-DELTA
MODULATOR
SIGMA-DELTA
MODULATOR
ANALOG
LOWPASS
FILTER
ANALOG
LOWPASS
FILTER
SDATA
MCLK
LRCLK
SCLK
OUTL
OUTR
VDD
GND
DAC
DAC
BUFFER
INTERNAL
REFERENCE
INTERPOLATOR
BUFFER
MAX5556
SERIAL
INTERFACE
MAX5556Low-Cost Stereo Audio DAC
Clock and Data Interface
The MAX5556 strobes serial data (SDATA) in on the ris-
ing edge of SCLK. LRCLK routes data to the left or right
outputs and, along with SCLK, defines the number of bits
per sample transferred. The digital interpolators filter data
at internal clock rates derived from the MCLK frequency.
Each device supports both internal and external serial
clock (SCLK) modes.
SDATA Input
The serial interface strobes data (SDATA) in on the rising
edge of SCLK, MSB first. The MAX5556 supports four
different data formats, as detailed in Figure 4.
Serial Clock (SCLK)
SCLK strobes the individual data bits at SDATA into
the DAC. The MAX5556 operates in one of two modes:
internal serial clock mode or external serial clock mode.
External SCLK Mode
The MAX5556 operates in external serial clock mode
when SCLK activity is detected. The device returns to
internal serial clock mode if no SCLK signal is detected
for one LRCLK period. Figure 5 details the external serial
clock mode timing parameters.
Figure 5. External SCLK Serial Timing Diagram
Figure 4. MAX5556 Data Format Timing
tSLRH
tSLRS
tSDH
SDATA
SCLK
LRCLK
tSDS
tSCLKLtSCLKH
tSCLK
MSBMSBLSBLSB-2-3-4-5+5+4+3+2+1-1-2-3-4+5+4+3+2+1
LRCLK
SCLK
SDATA
DATA DIRECTED TO OUTL
INTERNAL SERIAL CLOCK MODEEXTERNAL SERIAL CLOCK MODE
• I2S, 16-BIT DATA AND INTERNAL SCLK =
32 x fS IF MCLK/ LRCLK = 256 OR 512
• I2S, UP TO 24 BITS OF DATA AND INTERNAL
SCLK = 48 X fS IF MCLK/ LRCLK = 384
• I2S, UP TO 24 BITS OF DATA
• DATA VALID ON RISING EDGE OF SCLK
DATA DIRECTED TO OUTR
MAX5556Low-Cost Stereo Audio DAC

Partno	Mfg	Dc	Qty	Available	Descript
MAX5556ESA	MAXIM	N/a	2	avai	Low-Cost Stereo Audio DAC
MAX5556ESA+ \|MAX5556ESA	MAXIM	N/a	2	avai	Low-Cost Stereo Audio DAC