MAX547ACMH ,Octal, 13-Bit Voltage-Output DAC with Parallel InterfaceApplicationsMAX547ACMH 0°C to +70°C 44 Plastic FP ±2Automatic Test EquipmentMAX547BCMH 0°C to +70°C ..
MAX547ACMH+D ,Octal, 13-Bit Voltage-Output DAC with Parallel InterfaceELECTRICAL CHARACTERISTICS(V = +5V, V = -5V, REF_ = 4.096V, AGND_ = GND = 0V, R = 10kΩ, C = 50pF, T ..
MAX547ACMH+D ,Octal, 13-Bit Voltage-Output DAC with Parallel InterfaceApplicationsMAX547ACMH 0°C to +70°C 44 Plastic FP ±2Automatic Test EquipmentMAX547BCMH 0°C to +70°C ..
MAX547ACQH ,Octal, 13-Bit Voltage-Output DAC with Parallel InterfaceGeneral Description _________
MAX547ACQH ,Octal, 13-Bit Voltage-Output DAC with Parallel Interfacefeatures double-buffered interface logic with a1' Fast Output Settling (5µs to ± ⁄ LSB)213-bit para ..
MAX547ACQH+D ,Octal, 13-Bit Voltage-Output DAC with Parallel InterfaceGeneral Description _________
MAXQ610J-0000+ ,16-Bit Microcontroller with Infrared ModuleFeatures†MAXQ610J-0000+ 0°C to +70°C 44 TQFN-EP♦ High-Performance, Low-Power 16-Bit RISC CoreMAXQ61 ..
MAXQ610J-2519+ ,16-Bit Microcontroller with Infrared Moduleapplications toexecute on the MAXQ610, while limiting access to onlyModulationdata and code allowed ..
MAXQ610J-2519+T ,16-Bit Microcontroller with Infrared ModuleTABLE OF CONTENTSAbsolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MAXQ610J-2903+T ,16-Bit Microcontroller with Infrared Moduleapplications includ-♦ Secure MMU for Application Partitioning and IPing universal remote controls, ..
MAXQ610J-UEI+ ,16-Bit Microcontroller with Infrared ModulePin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MAXQ7665BATM+ ,16-Bit RISC Microcontroller-Based Smart Data-Acquisition SystemsFeaturesPower-Supply Supervisor/Brownout Detection for ● High-Performance, Low-Power, 16-Bit RISC ..
MAX547ACMH-MAX547ACQH-MAX547AEMH-MAX547BCQH-MAX547BEQH
Octal, 13-Bit Voltage-Output DAC with Parallel Interface
MAX547
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface19-0257; Rev 3; 12/95
_________________General DescriptionThe MAX547 contains eight 13-bit, voltage-output digital-to-
analog converters (DACs). On-chip precision output ampli-
fiers provide the voltage outputs. The MAX547 operates
from a ±5V supply. Bipolar output voltages with up to ±4.5V
voltage swing can be achieved with no external compo-
nents. The MAX547 has four separate reference inputs;
each is connected to two DACs, providing different full-
scale output voltages for every DAC pair.
The MAX547 features double-buffered interface logic with a
13-bit parallel data bus. Each DAC has an input latch and a
DAC latch. Data in the DAC latch sets the output voltage. The
eight input latches are addressed with three address lines.
Data is loaded to the input latch with a single write instruction.
An asynchronous load (–L—D—_–)input transfers data from the
input latch to the DAC latch. The four –L—D—_–inputs each control
two DACs, and all DAC latches can be updated simultane-
ously by asserting all –L—D—_–pins. An asynchronous clear (–C—L—R–)
input resets the output of all eight DACs to AGND_. Asserting–C—L—R–resets both the DAC and the input latch to bipolar zero
(1000hex). On power-up, reset circuitry performs the same
function as –C—L—R–.All logic inputs are TTL/CMOS compatible.
The MAX547 is available in 44-pin plastic quad flat pack
and 44-pin PLCC packages.
________________________ApplicationsAutomatic Test Equipment
Minimum Component-Count Analog Systems
Digital Offset/Gain Adjustment
Arbitrary Function Generators
Industrial Process Controls
Avionics Equipment
_____________________________FeaturesFull 13-Bit Performance without Adjustments8 DACs in One PackageBuffered Voltage OutputsCalibrated LinearityGuaranteed Monotonic to 13 Bits±5V Supply OperationUnipolar or Bipolar Outputs Swing to ±4.5VFast Output Settling (5µs to ±1⁄2LSB)Double-Buffered Digital InputsAsynchronous Load Inputs Load Pairs of DAC LatchesAsynchronous–C—L—R–Input Resets DACs to Analog
GroundPower-On Reset Circuit Resets DACs to Analog GroundMicroprocessor and TTL/CMOS Compatible
________________Ordering Information
Ordering Information continued at end of data sheet.*Contact factory for dice specifications.
_______________________________________________________________Pin Configurations
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +5V, VSS= -5V, REF_ = 4.096V, AGND_ = GND = 0V, RL= 10kΩ, CL= 50pF, TA= TMINto TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rat-
ings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
VSSto GND...............................................................-6V to +0.3V
Digital Input Voltage to GND......................-0.3V to (VDD+ 0.3V)
REF_ ..........................................(AGND_ - 0.3V) to (VDD+ 0.3V)
AGND_ .............................................(VSS- 0.3V) to (VDD+ 0.3V)
VOUT_ ........................................................................VDDto VSS
Maximum Current into REF_ Pin.......................................±10mA
Maximum Current into Any Other Signal Pin....................±50mA
Continuous Power Dissipation (TA= +70°C)
PLCC (derate 13.33mW/°C above +70°C)...................1067mW
Plastic FP (derate 11.11mW/°C above +70°C )..............889mW
Operating Temperature Ranges
MAX547–C–H.........................................................0°C to +70°C
MAX547–E–H......................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
Note 1:PSRR is tested by changing the respective supply voltage by ±5%.
Note 2:For best performance, REF_ should be greater than AGND_ + 2V and less than VDD- 0.6V. The device operates with
reference inputs outside this range, but performance may degrade. For further information on the reference, see the
Reference and Analog-Ground Inputssection in the Detailed Description.
Note 3:Reference input resistance is code dependent. See Reference and Analog-Ground Inputssection in the Detailed
Description.
Note 4:Typical settling time with 1000pF capacitive load is 10µs.
Note 5:Guaranteed by design. Not production tested.
Note 6:Guaranteed by supply-rejection test.
TIMING CHARACTERISTICSDD= +5V, VSS= -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA= TMINto TMAX, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)(VDD= +5V, VSS= -5V, REF_ = 4.096V, AGND_ = GND = 0V, RL= 10kΩ, CL= 50pF, TA= TMINto TMAX, unless otherwise noted.
Typical values are at TA= +25°C.)
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
__________________________________________Typical Operating CharacteristicsDD= 5V, VSS= -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA= +25°C, unless otherwise noted.)
0.1110100100010,000
REFERENCE INPUT SMALL-SIGNAL
FREQUENCY RESPONSEMAX547-Fg TOC-1
FREQUENCY (kHz)
RELATIVE OUTPUT (dB)
SUPPLY CURRENT
vs. TEMPERATURE
MAX547-Fg TOC-2
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
TOTAL HARMONIC DISTORTION
+ NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
MAX547-Fg TOC-3
FREQUENCY (kHz)
THD + NOISE (%)
TOTAL HARMONIC DISTORTION
+ NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
MAX547-Fg TOC-4
FREQUENCY (kHz)
THD + NOISE (%)
REFERENCE FEEDTHROUGH
MAX547-Fg TOC-7
FREQUENCY (kHz)
RELATIVE OUTPUT (dB)
0.1110100100010,000
REFERENCE INPUT LARGE-SIGNAL
FREQUENCY RESPONSEMAX547-Fg TOC-6
FREQUENCY (kHz)
RELATIVE OUTPUT (dB)
SETTLING TIME
vs. LOAD CAPACITANCE
MAX547-Fg TOC-9
LOAD CAPACITANCE (nF)
SETTLING TIME (2345
RELATIVE ACCURACY vs.
REFERENCE VOLTAGEMAX547-Fg TOC-11
REFERENCE VOLTAGE (V)
RELATIVE ACCURACY (LSB)
FULL-SCALE ERROR
vs. LOAD RESISTANCE
MAX547-Fg TOC-8
LOAD RESISTANCE (kΩ)
ERROR (LSB)
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
____________________________Typical Operating Characteristics (continued)DD= 5V, VSS= -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA= +25°C, unless otherwise noted.)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX547-Fg TOC-10
FREQUENCY (kHz)
PSRR (dB)
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
______________________________________________________________Pin Description
____________________________Typical Operating Characteristics (continued)DD= 5V, VSS= -5V, REF_ = 4.096V, AGND_ = GND = 0V, TA= +25°C, unless otherwise noted.)
_______________Detailed Description
Analog SectionThe MAX547 contains eight 13-bit, voltage-output
DACs. These DACs are “inverted” R-2R ladder net-
works that convert 13-bit digital inputs into equivalent
analog output voltages, in proportion to the applied ref-
erence voltages. The MAX547 has one reference input
(REF_) and one analog-ground input (AGND_) for each
pair of DACs. The four REF_ inputs allow different full-
scale output voltages for each DAC pair, and the four
AGND_ inputs allow different offset voltages for each
DAC pair.
The DAC ladder outputs are buffered with op amps that
operate with a gain of two. The inverting node of the
amplifier is connected to the respective reference
input, resulting in bipolar output voltages from -REF_ to
4095/4096 REF_. Figure 1 shows the simplified DAC
circuit.
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel Interface
_________________________________________________Pin Description (continued)
Reference and Analog-Ground InputsThe REF_ inputs can range between AGND_ and VDD.
However, the DAC outputs will operate to VDD- 0.6V
and VSS+ 0.6V, due to the output amplifiers’ voltage-
swing limitations. The AGND_ inputs can be offset by
any voltage within the supply rails. The offset-voltage
potential must be lower than the reference-voltage
potential. For more information, refer to the Digital Code
and Analog Output Voltagesection in the Applications
Information.
The input impedance of the REF_ inputs is code depen-
dent. It is at its lowest value (5kΩmin) when the input
code of the referring DAC pair is 0 1010 1010 1010
(0AAAhex). Its maximum value, typically 50kΩ, occurs
when the code is 0000hex. When all reference inputs are
driven from the same source, the minimum load imped-
ance is 1.25kΩ. Since the input impedance at REF_ is
code dependent, load regulation of the reference used is
important. For more information, see Reference
Selectionin the Applications Information section.
The input capacitance at REF_ is also code dependent,
and typically varies from 125pF to 300pF. Its minimum
value occurs when the code of the referring DAC pair is
set to all 0s. It is at its maximum value with all 1s on both
DACs.
Output Buffer AmplifiersThe MAX547’s voltage outputs are internally buffered
by precision gain-of-two amplifiers with a typical slew
rate of 3V/µs. With a full-scale transition at its output,
the typical settling time to ±1⁄2LSB is 5µs when loaded
with 10kΩin parallel with 50pF, or 6µs when loaded
with 10kΩin parallel with 100pF.
Digital Inputs and Interface LogicAll digital inputs are compatible with both TTL and
CMOS logic. The MAX547 interfaces with microproces-
sors using a data bus at least 13 bits wide. The inter-
face is double buffered, allowing simultaneous update
of all DACs. There are two latches for each DAC (see
Functional Diagram): an input latch that receives data
from the data bus, and a DAC latch that receives data
from the input latch. Address lines A0, A1, and A2
select which DAC’s input latch receives data from the
data bus, as shown in Table 1. Transfer data from the
input latches to the DAC latches by asserting the asyn-
chronous LD_signal. Each DAC’s analog output
reflects the data held in its DAC latch. All control inputs
are level triggered.
Data can be latched or transferred directly to the DAC.and WRcontrol the input latch and LD_transfers
information from the input latch to the DAC latch. The
input latch is transparent when CSand WRare low, and
the DAC latch is transparent when LD_is low. The
address lines (A0, A1, A2) must be valid throughout the
time CSand WRare low (Figure 3). Otherwise, the data
can be inadvertently written to the wrong DAC. Data is
latched within the input latch when either CSor WRis
high. Taking LD_high latches data into the DAC latches.
If LD_is brought low when WRand CSare low, it must
be held low for t3or longer after WRand CSare high
(Figure 3).
Pulling the asynchronous CLRinput low sets all DAC
outputs to a nominal 0V, regardless of the state of CS,
WR, andLD_.Taking CLRhigh latches 1000hex into
all input latches and DAC latches.
MAX547
Octal, 13-Bit Voltage-Output
DAC with Parallel InterfaceFigure 2. Input Control Logic
