MAX532BCWE+T ,Dual, Serial Input, Voltage-Output, Multiplying, 12-Bit DACApplications______________Ordering InformationAutomatic Test EquipmentArbitrary Waveform Generators ..
MAX532BEPE ,Dual, Serial-Input, Voltage-Output, 12-Bit MDACMAX53219-0046; Rev. 1; 3/94Dual, Serial-Input,Voltage-Output, 12-Bit MDAC_______________
MAX532BEPE+ ,Dual, Serial Input, Voltage-Output, Multiplying, 12-Bit DACApplications______________Ordering InformationAutomatic Test EquipmentArbitrary Waveform Generators ..
MAX532BEWE ,Dual, Serial-Input, Voltage-Output, 12-Bit MDACELECTRICAL CHARACTERISTICS(V = 11.4V to 16.5V, V = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VRE ..
MAX532BEWE+ ,Dual, Serial Input, Voltage-Output, Multiplying, 12-Bit DACMAX53219-0046; Rev. 1; 3/94Dual, Serial-Input,Voltage-Output, 12-Bit MDAC_______________
MAX533ACEE ,2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
MAX9789CETJ+T ,Windows Vista-Compliant, Stereo Class AB Speaker Amplifiers and DirectDrive Headphone Amplifiersfeatures Maxim’s DirectDrivearchitecture that produces a ground-referenced output♦ High +90dB PSRR, ..
MAX978EEE ,Single/Dual/Quad / SOT23 / Single-Supply / High-Speed / Low-Power ComparatorsFeaturesThe MAX976/MAX978/MAX998 dual/quad/single, high-' Single-Supply Operation Down to 2.7Vspeed ..
MAX978EEE+ ,Single/Dual/Quad, SOT23, Single-Supply, High-Speed, Low-Power Comparatorsfeatures a♦ 1nA Shutdown Supply Currentlow-power shutdown mode that places the output in a♦ Rail-to ..
MAX978ESE ,Single/Dual/Quad / SOT23 / Single-Supply / High-Speed / Low-Power Comparatorsapplications. They achieve a20ns propagation delay while consuming only 225µA' 225µA Supply Current ..
MAX978ESE+ ,Single/Dual/Quad, SOT23, Single-Supply, High-Speed, Low-Power ComparatorsGeneral Description ________
MAX9790AETJ+ ,Windows Vista-Compliant, Stereo Class AB Speaker Amplifiers and DirectDrive Headphone AmplifiersFeaturesThe MAX9789/MAX9790 combine a stereo, 2W Class AB♦ Microsoft Windows Vista Compliantspeaker ..
MAX532ACPE+-MAX532ACWE+-MAX532AEPE+-MAX532AEWE+-MAX532BCPE+-MAX532BCWE+-MAX532BCWE+T-MAX532BEPE+-MAX532BEWE+
Dual, Serial Input, Voltage-Output, Multiplying, 12-Bit DAC
_______________General DescriptionThe MAX532 is a complete, dual, serial-input, 12-bit
multiplying digital-to-analog converter (MDAC) with out-
put amplifiers. No external user trims are required to
achieve full specified performance. The MAX532’s 3-
wire serial interface minimizes the number of package
pins, so it uses less board space than parallel-interface
parts. The interface is SPI™, QSPI™ and Microwire™
compatible. A serial output, DOUT, allows cascading
of two or more MAX532s and read-back of the data
written to the device.
The device’s serial interface minimizes digital-noise
feedthrough from its logic pins to its analog outputs.
Serial interfacing also simplifies opto-coupler-isolated
or transformer-isolated applications.
The MAX532 is specified with ±12V to ±15V power sup-
plies. All logic inputs are TTL and CMOS compatible. It
comes in space-saving 16-pin DIP and wide SOpackages.
________________________ApplicationsAutomatic Test Equipment
Arbitrary Waveform Generators
Programmable-Gain Amplifiers
Motion Control Systems
Servo Controls
____________________________FeaturesTwo 12-Bit MDACs with Output AmplifiersFast, 6MHz 3-Wire InterfaceSPI, QSPI, and Microwire Compatible±12V Output Swing±10mA Output Current2.5μs Settling Time to ±1/2LSBGuaranteed Monotonic Over TemperatureLow Integral Nonlinearity: ±1/2LSB MaxLow Gain Tempco: 2ppm/°COperates from ±12V to ±15V SuppliesPower-On ResetAvailable in 16-Pin DIP and Wide SO Packages
______________Ordering Information
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
________________________________________________________________Maxim Integrated Products1VDD
LDAC
DINAGNDA
VOUTA
VREFA
RFBA
TOP VIEW
DOUT
SCLK
DGND
VSSRFBB
VREFB
VOUTB
AGNDB
DIP/Wide SOMAX532
__________________Pin ConfigurationDACA
LATCH
24-BIT SHIFT
REGISTER
DACB
LATCH
DACA
RFBA
VOUTA
DOUT
RFBB
VOUTB
AGNDB
AGNDA
VREFA
DIN
SCLK
LDAC
VREFB
DACB
VDD
VSSDGND
MAX532
________________Functional Diagram
Call toll free 1-800-998-8800 for free samples or literature.19-0046; Rev. 1; 3/94
PARTTEMP. RANGEPIN-PACKAGEMAX532ACPE0°C to +70°C16 Plastic DIP
MAX532BCPE0°C to +70°C16 Plastic DIP
MAX532ACWE0°C to +70°C16 Wide SO
MAX532BCWE0°C to +70°C16 Wide SO
MAX532BC/D0°C to +70°CDice*
™Microwire is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola, Inc.
±1/2
±1/2
ERROR
(LSBs)
Ordering Information continued on last page.* Contact factory for dice specifications.
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC_______________________________________________________________________________________Pin Voltages
VDDto DGND, AGNDA, AGNDB........................-0.3V to +17V
VSSto DGND, AGNDA, AGNDB (Note 1)..........+0.3V to -17V
VREFA, VREFB.............................(VSS- 0.3V) to (VDD+ 0.3V)
AGNDA, AGNDB.....................(DGND - 0.3V) to (VDD+ 0.3V)
VOUTA, VOUTB...........................(VSS- 0.3V) to (VDD+ 0.3V)
RFBA, RFBB.................................(VSS- 0.3V) to (VDD+ 0.3V)
SCLK, DIN, DOUT, LDAC, CS..(DGND - 0.3V) to (VDD+ 0.3V)
DOUT Sink Current.............................................................20mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C)..........842mW
Wide SO (derate 9.52mW/°C above +70°C)................762mW
CERDIP (derate 10.00mW/°C above +70°C)...............800mW
Operating Temperature Ranges:
MAX532_C__......................................................0°C to +70°C
MAX532_E__....................................................-40°C to +85°C
MAX532_MJE................................................-55°C to +125°C
Junction Temperatures:
MAX532_C__, E__........................................................+150°C
MAX532_MJE...............................................................+175°C
Storage Temperature Range...........................-65°C to +160°C
Lead Temperature (soldering, 10sec)...........................+300°C
ELECTRICAL CHARACTERISTICS(VDD= 11.4V to 16.5V, VSS= -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL= 2kΩ, = 100pF, VOUT_ connected to RFB_, TA= TMINto TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
PARAMETERCONDITIONSMINTYPMAXUNITSSYMBOLResolution
INLBits
Relative Accuracy±1LSB
Differential NonlinearityGuaranteed monotonic±1LSB
±1/2MAX532A
MAX532BTA= +25°C, MAX532_Zero-Code Offset ErrorDAC latch loaded
with all 0s
TA= TMINto TMAX, MAX532BμV/°CDAC latch loaded with all 0sMAX532ATA= +25°C, DAC latch
loaded with all 1s±5MAX532B
±0.5±3.0%1013kΩppm/°C
of FSR
Gain Error= TMINto TMAX, DAC
latch loaded with all 1s±7
LSB
MAX532BMAX532A
TA= TMINto TMAX, MAX532A
Zero-Code Offset
Temperature Coefficient
Gain-Error Temperature
Coefficient
VREFA, VREFB Input
Resistance
VREFA, VREFB Input
Resistance Matching
STATIC PERFORMANCE(Note 1)
REFERENCE INPUTS (VREFA, VREFB)
Note 1:If VSSis open-circuited with VDDand either AGND applied, the VSSpin will float positive, exceeding the Absolute Maximum Ratings.
A Schottky diode connected between VSSand GND ensures the maximum ratings will not be exceeded.
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
_______________________________________________________________________________________3
ELECTRICAL CHARACTERISTICS (continued)(VDD= 11.4V to 16.5V, VSS= -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL= 2kΩ, CL= 100pF,
VOUT_ connected to RFB_, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERCONDITIONSMINTYPMAXUNITSSYMBOLVINL
VOL
Input Low Voltage0.8V
ISINK= 5mA0.080.4Output Voltage LowISINK= 16mA0.2V
VINHInput High Voltage2.4V
Input CurrentDigital inputs at 0V or VDD±1μApFInput Capacitance (Note 2)
ILKGOutput High LeakageVDOUT= 0V to VDD±10μA
COUT15pF
DC Output Impedance0.2Ω
Short-Circuit CurrentVOUTA, VOUTB connected to AGNDA, AGNDB20mA
Output Voltage SwingV
VDDPositive Supply Voltage11.416.5V
VSSNegative Supply Voltage-11.4-16.5V
±0.035
PSRPower-Supply Rejection
±0.035
LSB/%
IDDPositive Supply CurrentOutput unloaded510mA
ISSNegative Supply CurrentOutput unloaded46mA
Settling time to within 1/2 LSB of final DAC value; DAC
latch alternately loaded with all 0s and all 1s2.5μs
Slew Rate8V/μs
DAC latch alternately loaded with 011...11 and 100...0060nV-s
Output High Capacitance
(Note 2)Full scale/DVDD, VDD= 11.4V to 16.5V, VREF = -8.9V,
DAC latches loaded with all 1sFull scale/DVSS, VSS= -11.4V to -16.5V, VREF = 8.9V,
DAC latches loaded with all 1s
VREFA to VOUTB-100
Channel-to-Channel
Isolation
VREFB to VOUTA-100
Voltage-Output
Settling Time
Digital-to-Analog
Glitch Impulse
VREFA = 20Vp-p10kHz
sine wave; DAC latches
loaded with all 0s
VREFB = 20Vp-p10kHz
sine wave; DAC latches
loaded with all 0s
(VDD- 2.5)
(VSS+ 2.5)
DIGITAL INPUTS (SCLK, DIN, LDAC, CS)
DIGITAL OUTPUT (DOUT) (Note 3)
ANALOG OUTPUTS (VOUTA, VOUTB)
POWER REQUIREMENTS
AC CHARACTERISTICS
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)(VDD= 11.4V to 16.5V, VSS= -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL= 2kΩ, CL= 100pF,
VOUT_ connected to RFB_, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERCONDITIONSMINTYPMAXUNITSSYMBOLVREF = 100mVp-psine wave;
DAC latch loaded with all 1s1.0MHz
VREF = 20Vp-p10kHz sine wave;
DAC latch loaded with all 0s-77dB
Full-Power Bandwidth125kHz
THDTotal Harmonic Distortion-90dB
Output Noise Voltage0.1Hz to 10Hz2μVRMS
Digital CrosstalkDACA code all 1s, DACB code transition from all 0s to all 1s10nV-s
Digital FeedthroughCS= 1; transitions on SCLK, LDAC, DIN1.1nV-s
PARAMETERtCL
CONDITIONSMINTYPMAXSCLK Pulse Width Low
UNITSSYMBOLfCLK
tCHns
tDS50ns
tCSS1CSRise to SCLK Rise Setup Time
SCLK Clock Frequencyns
tCSS0CSFall to SCLK Rise Setup Time
6.25MHzns
tDHDIN to SCLK Rise Hold Time0ns
SCLK Pulse Width High80ns
Multiplying Feedthrough
Error
Unity-Gain Small-Signal
Bandwidth
VREF = 20Vp-psine wave;
DAC latch loaded with all 1s
VREF = 6VRMS, 1kHz sine wave;
DAC latch loaded with all 1s
Note 1:Static performance tested at VDD= +15V, VSS= -15V. Performance over supplies guaranteed by PSR test.
Note 2:Guaranteed by design. Not subject to production testing.
Note 3:Open-drain output.
TIMING CHARACTERISTICS(VDD= 11.4V to 16.5V, VSS= -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V) (Notes 4, 5)
tCSH0SCLK Fall to CSFall Hold Time5ns
tCSH1SCLK Rise to CSRise Hold Time80ns
tCSWCSPulse Width High120ns
tDOSCLK Fall to DOUT Valid (Note 6)CL= 20pF, RPULL-UP= 1kΩto 5V0200ns
tDVCSFall to DOUT Enable (Note 7)CL= 20pF, RPULL-UP= 1kΩto 5V100ns
tTRCSRise to DOUT Disable (Note 7)CL= 20pF, RPULL-UP= 1kΩto 5V60ns
tLDACLDACPulse Width Low60ns
tLDACSCSRise to LDACFall Setup Time100ns
DIN to SCLK Rise Setup Time
Note 4:All input signals are specified with tR= tF£5ns. Logic input swing is 0V to 5V.
Note 5:See Figure 1.
Note 6:Timing is for SCLK fall to DOUT fall to 0.8V, or for SCLK fall to DOUT rise to 2.4V. Additional time must be added for any
larger passive RC pull-up delay.
Note 7:DOUT enable: DOUT falls to 4.5V from 5.0V. DOUT disable: DOUT rises to 0.5V from 0V.
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
_________________________________________________________________________________________________51k10k
OUTPUT VOLTAGE SWING
vs. RESISTIVE LOADLOAD RESISTANCE (W)
(V
p-p
VREF = 20Vp-p at 1kHz100k
NOISE SPECTRAL DENSITYFREQUENCY (Hz)
(nV
H
1001k10k
VREF = 0V
DAC CODE = 11...111
GAIN = -1
10010k10M
LARGE-SIGNAL FREQUENCY RESPONSEFREQUENCY (Hz)
(dB
-30100k1M
VREF = 20Vp-p
DAC CODE = 11...111
GAIN = -1-20
10010k10M
SMALL-SIGNAL FREQUENCY RESPONSEFREQUENCY (Hz)
(d-5
-20100k1M
VREF = 100mVp-p
DAC CODE = 11...111
-85100k
MULTIPLYING FEEDTHROUGH ERRORFREQUENCY (Hz)
(d
10k1M
VREFA = 20Vp-p
VREFB = AGNDB
DAC CODE = 00...00
1001k10k
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH = 80kHz)FREQUENCY (Hz)
(d
VREF = 6VRMS
DAC CODE = 111...111
10010k100k
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (BANDWIDTH > 500kHz)FREQUENCY (Hz)
(d
VREF = 6VRMS
DAC CODE = 111...111
__________________________________________Typical Operating Characteristics(VDD= 15V, VSS= -15V, RL= 2kΩ, CL= 100pF, unless otherwise noted.)
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC_______________________________________________________________________________________
______________________________________________________________Pin DescriptionAGNDA
A = VOUTA, 5V/div
TIMEBASE = 2ms/div
VREFA = ±10V SQUARE WAVE
LARGE-SIGNAL PULSE RESPONSE
____________________________Typical Operating Characteristics (continued)(VDD= 15V, VSS= -15V, RL= 2kΩ, CL= 100pF, unless otherwise noted.)
PINNAMEFUNCTIONRFBAFeedback Resistor for DACAVREFAReference Input for DACAVOUTAVoltage Output for DACAAGNDAAnalog Ground for DACAAGNDBAnalog Ground for DACBVOUTBVoltage Output for DACBVREFBReference Input for DACBRFBBFeedback Resistor for DACBVSSNegative Supply VoltageDGNDDigital GroundSCLKSerial Clock InputDOUT
Serial Data Output. Open-drain N-channel MOSFET output: requires external pull-up resis-
tor. Data on DOUT changes on the falling edge of SCLK. Serial output data is delayed 24
clock cycles from DIN.DINSerial Data Input. CMOS- and TTL-compatible input. Data is clocked into DIN on the rising
edge of SCLK. CSmust be low for data to be clocked in.VDDPositive Supply VoltageLDACAsynchronous Load DAC Input, active low. DAC latches are updated when CSis high and
LDACis low.CSChip-Select Input, active low. Data is shifted in and out when CSis low. DAC latches are
updated when CSis high and LDACis low.AGNDA
A = VOUTA, 50mV/div
TIMEBASE = 2ms/div
VREFA = ±100mV SQUARE WAVE
SMALL-SIGNAL PULSE RESPONSE
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
_______________________________________________________________________________________7Figure 1. Timing Diagram-----
tCSHOtCHtCSSOtCL
tDHtDS
tDVtD0
tCSH1
tCSS1
tCSW
tLDACS
tTR
tLDAC
SCLK
DIN
DOUT
LDACD1Q1
D23
Q23D0
DACS
UPDATED
____________________________________________________________Timing Diagrams
Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC_______________________________________________________________________________________Figure 2. 3-Wire Interface Timing Diagram (LDAC= DGND)---
SCLK
DIN
DOUT
D1 D0 ............................................
MSB DACB
MSB DACB FROM
PREVIOUS WRITE
MSB DACALSB DACBLSB DACA
MSB DACA FROM
PREVIOUS WRITE
D23D16D15D14D13D12D11..........
.....................................Q22Q16Q15Q14Q13Q12Q11..........Q1 Q0 D23D23Q23
DACS
UPDATED
Figure 3. 4-Wire Inferface Timing Diagam--
SCLK
DIN
DOUT
LDAC
D1 D0 ............................................
MSB DACB
MSB DACB FROM
PREVIOUS WRITE
MSB DACALSB DACBLSB DACA
MSB DACA FROM
PREVIOUS WRITE
D23D16D15D14D13D12D11..........
...................................Q22Q16Q15Q14Q13Q12Q11..........Q1 Q0 D23D23Q23
DACS
UPDATED
_______________________________________________Timing Diagrams (continued)
