MAX5307EUE ,PLASTIC ENCAPSULATED DEVICES MAX5307EUE Rev. A RELIABILITY REPORT FOR MAX5307EUE PLASTIC ENCA ..
MAX5307EUE+ ,Low-Power, Low-Glitch, Octal 12-Bit Voltage-Output DACs with Serial InterfaceMAX5306/MAX530719-2132; Rev 0; 8/01Low-Power, Low-Glitch, Octal 12-Bit Voltage-Output DACs with Ser ..
MAX5309EUE ,PLASTIC ENCAPSULATED DEVICES MAX5309EUE Rev. A RELIABILITY REPORT FOR MAX5309EUE PLASTIC ENCA ..
MAX5309EUE+T ,Low-Power, Low-Glitch, Octal 10-Bit Voltage-Output DACs with Serial Interfaceapplications. The low 2nV-s glitch energy1.7mA (max) with V = V = +5.5VREF DDof the MAX5308/MAX5309 ..
MAX5309EUE-T ,Low-Power, Low-Glitch, Octal 10-Bit Voltage-Output DACs with Serial InterfaceApplicationsGain and Offset AdjustmentPin ConfigurationPower Amplifier ControlProcess Control I/O B ..
MAX530ACAG ,+5V, Low-Power, Parallel-Input, Voltage-Output, 12-Bit DACfeatures but with a serial data interface, referto the MAX531/MAX538/MAX539 data sheet.ERRORPART TE ..
MAX9755ETI ,2.6W Stereo Audio Power Amplifiers and DirectDrive Headphone AmplifiersBlock DiagramsPIN- M A XIMU M PART TEMP RANGEPACKAGE G A I N ( d B ) †MAX9750AETI* -40°C to +85°C ..
MAX9755ETI+ ,2.6W Stereo Audio Power Amplifiers and DirectDrive® Headphone AmplifiersELECTRICAL CHARACTERISTICS(V = PV = CPV = HPV = 5V, V = V = V = 0V, SHDN = V , C = 1µF, C1 = C2 = 1 ..
MAX9755ETI+ ,2.6W Stereo Audio Power Amplifiers and DirectDrive® Headphone Amplifiersfeatures an analog volume control, and a♦ High 90dB PSRRBEEP input. The MAX9751
MAX9755ETI+T ,2.6W Stereo Audio Power Amplifiers and DirectDrive® Headphone Amplifiersfeatures a 2:1 input multiplexer,allowing multiple audio sources to be selected. All devices♦ Low-P ..
MAX9759ETE+T ,3.2W, High-Efficiency, Low-EMI, Filterless, Class D Audio AmplifierFeaturesThe MAX9759 mono Class D, audio power amplifier♦ 3.2W into 4Ω Load (THD+N = 10%)provides Cl ..
MAX975ESA ,Single/Dual / +3V/+5V Dual-Speed Comparators with Auto-StandbyApplicationsMAX975IN+Battery-Powered Systems LPRF ID TagsHIGH SPEEDOUTKeyless EntryENABLEThreshold ..
MAX5307EUE
PLASTIC ENCAPSULATED DEVICES
MAX5307EUE Rev. A RELIABILITY REPORT
FOR
MAX5307EUE PLASTIC ENCAPSULATED DEVICES
May 11, 2003
MAXIM INTEGRATED PRODUCTS 120 SAN GABRIEL DR.
SUNNYVALE, CA 94086
Written by Reviewed by
Jim Pedicord Bryan J. Preeshl
Quality Assurance Quality Assurance
Reliability Lab Manager Executive Director
Conclusion The MAX5307 successfully meets the quality and reliability standards required of all Maxim products. In addition,
Maxim’s continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim’s quality
and reliability standards.
Table of Contents
I. ........Device Description V. ........Quality Assurance Information
II. ........Manufacturing Information VI. .......Reliability Evaluation
III. .......Packaging Information IV. .......Die Information .....Attachments
I. Device Description A. General
The MAX5307 is a 12-bit, eight channel, low-power, voltage-output, digital-to-analog converter (DAC) in a space-saving 16-pin
TSSOP package. The wide +2.7V to +5.5V supply voltage range and less than 215µA (max) supply current per DAC are
excellent for low-power and low-voltage applications. The low 2nV/s glitch energy of the MAX5306/MAX5307 makes it ideal
for digital control of fast-response, closed-loop systems.
The MAX5307 has a hardware reset input (CLR-bar) which clears all registers and DACs to zero. The MAX5307 has a
software shutdown feature that reduces the supply current to 1µA. The MAX5307 features a load DAC (LDAC-bar) function
that updates the output of all eight DACs simultaneously.
The 3-wire SPI™, QSPI™, MICROWIRE™ and DSP-compatible serial interface allows the input and DAC registers to be
updated independently or simultaneously with a single software command. This devices uses a double-buffered design to
minimize the digital-noise feedthrough from the digital inputs to the outputs. The MAX5307 operating temperature range is
from -40°C to +85°C. B. Absolute Maximum Ratings
VDD to GND -0.3V to +6V
All Other Pins to GND -0.3V to (VDD + 0.3V)
Maximum Current Into Any Pin ±50mA
Operating Temperature Range -40°C to +85°C
Junction Temperature +150°C
Storage Temperature Range -65°C to +150°C
Lead Temperature (soldering, 10s) .+300°C
Continuous Power Dissipation (TA = +70°C)
16-Pin TSSOP 775mW
Derates above +70°C
16-Pin TSSOP 9.4mW/°C
II. Manufacturing Information A. Description/Function: Low-Power, Low-Glitch, Octal 12-Bit Voltage-Output DACs with Serial Interface B. Process: S6 (Standard 0.6 micron silicon gate CMOS) C. Number of Device Transistors: 19,000
D. Fabrication Location: California, USA
E. Assembly Location: Malaysia or Thailand F. Date of Initial Production: July, 2001
III. Packaging Information A. Package Type:
16-Pin TSSOP B. Lead Frame: Copper C. Lead Finish: Solder Plate D. Die Attach: Silver-Filled Epoxy E. Bondwire: Gold (1 mil dia.) F. Mold Material: Epoxy with silica filler
G. Assembly Diagram: #05-3901-0002
H. Flammability Rating: Class UL94-V0
I. Classification of Moisture Sensitivity
per JEDEC standard JESD22-112: Level 1
IV. Die Information A. Dimensions: 102 x 141 mils B. Passivation: Si3N4/SiO2 (Silicon nitride/ Silicon dioxide) C. Interconnect: Aluminum/Si (Si = 1%) D. Backside Metallization: None E. Minimum Metal Width: 0.6 microns (as drawn) F. Minimum Metal Spacing: 0.6 microns (as drawn) G. Bondpad Dimensions: 5 mil. Sq. H. Isolation Dielectric: SiO2 I. Die Separation Method: Wafer Saw
V. Quality Assurance Information A. Quality Assurance Contacts: Jim Pedicord (Manager, Rel Operations) Bryan Preeshl (Executive Director) Kenneth Huening (Vice President) B. Outgoing Inspection Level: 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% For all Visual Defects. C. Observed Outgoing Defect Rate: < 50 ppm D. Sampling Plan: Mil-Std-105D
VI. Reliability Evaluation A. Accelerated Life Test
The results of the 135°C biased (static) life test are shown in
Table 1. Using these results, the Failure Rate (l) is calculated as follows:
l = 1 = 4.04 (Chi square value for MTTF upper limit)
MTTF 192 x 4389 x 79 x 2 Temperature Acceleration factor assuming an activation energy of 0.8eV l = 30.35 x 10-9 l = 30.35 F.I.T. (60% confidence level @ 25°C)
This low failure rate represents data collected from Maxim’s reliability monitor program. In addition to
routine production Burn-In, Maxim pulls a sample from every fabrication process three times per week and subjects
it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be
shipped as standard product is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece
sample. Maxim performs failure analysis on any lot that exceeds this reliability control level. Attached Burn-In
Schematic (Spec. # 06-5814) shows the static Burn-In circuit. Maxim also performs quarterly 1000 hour life test
monitors. This data is published in the Product Reliability Report (RR-1M). B. Moisture Resistance Tests
Maxim pulls pressure pot samples from every assembly process three times per week. Each lot sample
must meet an LTPD = 20 or less before shipment as standard product. Additionally, the industry standard
85°C/85%RH testing is done per generic device/package family once a quarter.
C. E.S.D. and Latch-Up Testing The DB06 die type has been found to have all pins able to withstand a transient pulse of ±1500V per Mil-
Std-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device
withstands a current of ±250mA.
Table 1 Reliability Evaluation Test Results
MAX5307EUE
TEST ITEM TEST CONDITION FAILURE SAMPLE NUMBER OF IDENTIFICATION PACKAGE SIZE FAILURES
Static Life Test (Note 1) Ta = 135°C DC Parameters 160 0 Biased & functionality Time = 192 hrs.
Moisture Testing (Note 2) Pressure Pot Ta = 121°C DC Parameters TSSOP 77 0 P = 15 psi. & functionality RH= 100% Time = 168hrs. 85/85 Ta = 85°C DC Parameters 77 0 RH = 85% & functionality Biased Time = 1000hrs.
Mechanical Stress (Note 2) Temperature -65°C/150°C DC Parameters 77 0 Cycle 1000 Cycles & functionality Method 1010
Note 1: Life Test Data may represent plastic DIP qualification lots.
Note 2: Generic Package/Process data
Attachment #1 TABLE II. Pin combination to be tested. 1/ 2/ 1/ Table II is restated in narrative form in 3.4 below. 2/ No connects are not to be tested. 3/ Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc). 3.4 Pin combinations to be tested. a. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. b. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins (e.g., VSS1, or VSS2 or VSS3 or VCC1, or VCC2) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. c. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open.
TERMINAL B
TERMINAL A
CURRENT
PROBE
(NOTE 6)
R = 1.5kW
C = 100pf
SHORT
R2
S2 R1
