MAX5293EUE+ Fast Delivery |IC PHOENIX CO.,LIMITED

MAX5293EUE+ ,Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACsApplicationsPART TEMP RANGE PIN-PACKAGEPortable InstrumentationMAX5290AEUD -40°C to +85°C 14 TSSOPA ..
MAX5294EUD ,Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACsApplicationsPART TEMP RANGE PIN-PACKAGEPortable InstrumentationMAX5290AEUD* -40°C to +85°C 14 TSSOP ..
MAX529CAG ,Octal, 8-Bit, Serial DACs with Output BufferFeatures ' Now Available in Space-Saving SSOP ' 8 Buffered Noninverting Outputs ' Buffer D ..
MAX529CPP ,Octal, 8-Bit, Serial DACs with Output BufferGeneral Description The MAX528/MAX529 are monolithic devices combining an octal 8-bit, digital- ..
MAX529CWG ,Octal, 8-Bit, Serial DACs with Output BufferELECTRICAL CHARACTERISTICS - MAX528 (Unbuffered Mode: VDD = +12V, Vss = OV; Full-Buffered Mode: ..
MAX529CWG ,Octal, 8-Bit, Serial DACs with Output BufferELECTRICAL CHARACTERISTICS - MAX528 (Unbuffered Mode: VDD = +12V, Vss = OV; Full-Buffered Mode: ..
MAX974CSE ,Ultra-Low-Power / Open-Drain / Single/Dual-Supply Comparatorsapplications, thesedevices operate from a single +2.5V to +11V supply (or' Internal 1.182V ±1% Band ..
MAX974CSE ,Ultra-Low-Power / Open-Drain / Single/Dual-Supply ComparatorsGeneral Description ________
MAX974CSE+ ,Ultra-Low-Power, Open-Drain, Single/Dual-Supply ComparatorsELECTRICAL CHARACTERISTICS—5V OPERATION (continued)(V+ = 5V, V- = GND = 0V, T = T to T , unless oth ..
MAX974ESE ,Ultra-Low-Power / Open-Drain / Single/Dual-Supply ComparatorsApplicationsfor adding hysteresis without feedback or complicatedBattery-Powered Systems Level Tran ..
MAX974ESE ,Ultra-Low-Power / Open-Drain / Single/Dual-Supply ComparatorsMAX971–MAX974/MAX981–MAX98419-0450; Rev 0; 11/95Ultra-Low-Power, Open-Drain,Single/Dual-Supply Comp ..
MAX9750AETI ,2.6W Stereo Audio Power Amplifiers and DirectDrive Headphone AmplifiersFeaturesThe MAX9750/MAX9751/MAX9755 combine a stereo,♦ No DC-Blocking Capacitors Required—Provides2 ..

MAX5293EUE+
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
General Description
The MAX5290–MAX5295 dual, 12-/10-/8-bit, voltage-
output digital-to-analog converters (DACs) offer
buffered outputs and a 3µs maximum settling time at
the 12-bit level. The DACs operate from a 2.7V to 5.25V
analog supply and a separate 1.8V to 3.6V digital sup-
ply. The 20MHz 3-wire serial interface is compatible
with SPI™, QSPI™, MICROWIRE™, and digital signal
processor (DSP) protocol applications. Multiple devices
can share a common serial interface in direct access or
daisy-chained configuration. The MAX5290–MAX5295
provide two multifunctional, user-programmable, digital
I/O ports. The externally selectable power-up states of
the DAC outputs are either zero scale, midscale, or full
scale. Software-selectable FAST and SLOW settling
modes decrease settling time in FAST mode, or reduce
supply current in SLOW mode.
The MAX5290/MAX5291 are 12-bit DACs, the MAX5292/
MAX5293 are 10-bit DACs, and the MAX5294/MAX5295
are 8-bit DACs. The MAX5290/ MAX5292/MAX5294 pro-
vide unity-gain-configured output buffers, while the
MAX5291/MAX5293/MAX5295 provide force-sense-con-
figured output buffers. The MAX5290– MAX5295 are
specified over the extended -40°C to +85°C temperature
range, and are available in space-saving 4mm x 4mm,
16-pin thin QFN and 6.5mm x 5mm, 14-pin and 16-pin
TSSOP packages.
Applications
Portable Instrumentation
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Automatic Tuning
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Controls
Motion Control
Microprocessor (µP)-Controlled Systems
Power Amplifier Control
Fast Parallel-DAC to Serial-DAC Upgrades
FeaturesDual, 12-/10-/8-Bit Serial DACs in 4mm x 4mm
Thin QFN and TSSOP Packages3µs (max) 12-Bit Settling Time to 1/2 LSBIntegral Nonlinearity
1 LSB (max) MAX5290/MAX5291 A-Grade (12-Bit)
1 LSB (max) MAX5292/MAX5293 (10-Bit)
1/2 LSB (max) MAX5294/MAX5295 (8-Bit)Guaranteed Monotonic, ±1 LSB (max) DNLTwo User-Programmable Digital I/O PortsSingle +2.7V to +5.25V Analog Supply+1.8V to AVDDDigital Supply20MHz 3-Wire SPI-/QSPI-/MICROWIRE- and
DSP-Compatible Serial InterfaceGlitch-Free Outputs Power Up to Zero Scale,
Midscale or Full ScaleUnity-Gain- or Force-Sense-Configured Output
Buffers
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Ordering Information
19-3005; Rev 3; 7/07
*Future product—contact factory for availability. Specifications
are preliminary.
**EP = Exposed paddle.
Selector Guide and Pin Configurations appear at end of data
sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PARTTEMP RANGEPIN-PACKAGE
MAX5290AEUD-40°C to +85°C14 TSSOP
MAX5290BEUD-40°C to +85°C14 TSSOP
MAX5290AETE*-40°C to +85°C16 Thin QFN-EP**
MAX5290BETE*-40°C to +85°C16 Thin QFN-EP**
MAX5291AEUE-40°C to +85°C16 TSSOP
MAX5291BEUE-40°C to +85°C16 TSSOP
MAX5291AETE*-40°C to +85°C16 Thin QFN-EP**
MAX5291BETE*-40°C to +85°C16 Thin QFN-EP**
MAX5292EUD-40°C to +85°C14 TSSOP
MAX5292ETE*-40°C to +85°C16 Thin QFN-EP**
MAX5293EUE-40°C to +85°C16 TSSOP
MAX5293ETE*-40°C to +85°C16 Thin QFN-EP**
MAX5294EUD-40°C to +85°C14 TSSOP
MAX5294ETE*-40°C to +85°C16 Thin QFN-EP**
MAX5295EUE-40°C to +85°C16 TSSOP
MAX5295ETE*-40°C to +85°C16 Thin QFN-EP**
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, VREF= 2.5V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto DVDD........................................................................±6V
AGND to DGND..................................................................±0.3V
AVDDto AGND, DGND.............................................-0.3V to +6V
DVDDto AGND, DGND............................................-0.3V to +6V
FB_, OUT_,
REF to AGND........-0.3V to the lower of (AVDD + 0.3V) or +6V
SCLK, DIN, CS, PU,
DSPto DGND.......-0.3V to the lower of (DVDD + 0.3V) or +6V
UPIO1, UPIO2
to DGND...............-0.3V to the lower of (DVDD + 0.3V) or +6V
Maximum Current into Any Pin.........................................±50mA
Continuous Power Dissipation (TA= +70°C)
14-Pin TSSOP (derate 9.1mW/°C above +70°C).........727mW
16-Pin TSSOP (derate 9.4mW/°C above +70°C).........755mW
16-Pin Thin QFN (derate 16.9mW/°C above +70°C).1349mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature.....................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC ACCURACY
MAX5290/MAX529112
MAX5292/MAX529310ResolutionN
MAX5294/MAX52958
Bits
MAX5290A/MAX5291A (12-bit)±1
MAX5290B/MAX5291B (12-bit)±2±4
MAX5292/MAX5293 (10-bit)±0.5±1
Integral NonlinearityINL
VREF = 2.5V at
AVDD = 2.7V,
VREF = 4.096V
at AVDD = 5.25V
(Note 2)MAX5294/MAX5295 (8-bit)±0.125±0.5
LSB
Differential NonlinearityDNLGuaranteed monotonic (Note 2)±1LSB
MAX5290A/MAX5291A (12-bit), decimal code = 40±5
MAX5290B/MAX5291B (12-bit), decimal code = 82±5±25
MAX5292/MAX5293 (10-bit), decimal code = 21±5±25Offset ErrorVOS
MAX5294/MAX5295 (8-bit), decimal code = 5±5±25
Offset-Error Drift5ppm of
FS/°C
MAX5290A/MAX5291A (12-bit)±4
MAX5290B/MAX5291B (12-bit)±10±20
MAX5292/MAX5293 (10-bit)±3±5Gain ErrorGEFull-scale output
MAX5294/MAX5295 (8-bit)±0.5±2
LSB
Gain-Error Drift1ppm of
FS/°C
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, VREF= 2.5V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Power-Supply Rejection
RatioPSRRFull-scale output, AVDD = 2.7V to 3.6V200µV/V
REFERENCE INPUT
Reference Input RangeVREF0.25AVDDV
Reference Input
ResistanceRREFNormal operation (no code dependence)145200kΩ
Reference Leakage
CurrentIREFShutdown mode0.51µA
DAC OUTPUT CHARACTERISTICS
Unity gain85SLOW mode,
full scaleForce sense67
Unity gain140Output Voltage Noise
FAST mode,
full scaleForce sense110
µVRMS
Unity-gain output0AVDDOutput Voltage Range
(Note 4)Force-sense output0AVDD / 2V
DC Output Impedance38Ω
Short-Circuit CurrentAVDD = 3V, OUT_ to AGND, full scale, FAST mode45mA
Power-Up TimeFrom DVDD applied, interface is functional3060µs
Wake-Up TimeComing out of shutdown, outputs settled40µs
Output OUT_ and FB_
Open-Circuit Leakage
Current
Programmed in shutdown mode, force-sense
outputs only0.01µA
DIGITAL OUTPUTS (UPIO_)
Output High VoltageVOHISOURCE = 2mADVDD -
0.5V
Output Low VoltageVOLISINK = 2mA0.4V
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)
DVDD ≥ 2.7V2.4
Input High VoltageVIHDVDD < 2.7V0.7 x
DVDD
DVDD > 3.6V0.8
2.7V ≤ DVDD ≤ 3.6V0.6Input Low VoltageVIL
DVDD < 2.7V0.2
Input Leakage CurrentIIN±0.1±1µA
Input CapacitanceCIN10pF
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, VREF= 2.5V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PU INPUT
Input High VoltageVIH-PUDVDD -
200mVV
Input Low VoltageVIL-PU200mV
Input Leakage CurrentIIN-PUPU still considered floating when connected to a
tri-state bus±200nA
DYNAMIC PERFORMANCE
Fast mode3.6Voltage-Output Slew
RateSRSlow mode1.6V/µsAX 5290/M AX 5291 fr om cod e 322 to
cod e 4095 to 1/2 LS B23AX 5292/M AX 5293 fr om cod e 82 to
cod e 1023 to 1/2 LS B1.53FAST mode
MAX5294/MAX5295 from code 21 to
code 255 to 1/2 LSB12AX 5290/M AX 5291 fr om cod e 322 to
cod e 4095 to 1/2 LS B36
MAX5292/MAX5293 from code 82 to
code 1023 to 1/2 LSB2.56
Voltage-Output Settling
Time (Note 5)
SLOW mode
MAX5294/MAX5295 from code 21 to
code 255 to 1/2 LSB24
FB_ Input Voltage0VREF / 2V
FB_ Input Current0.1µA
Unity gain200Reference -3dB
Bandwidth (Note 6)Force sense150kHz
Digital FeedthroughCS = DVDD, code = zero scale, any digital input
from 0 to DVDD and DVDD to 0, f = 100kHz0.1nV-s
Digital-to-Analog Glitch
ImpulseMajor carry transition2nV-s
DAC-to-DAC Crosstalk(Note 3)15nV-s
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, VREF= 2.5V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTS
Analog Supply Voltage
RangeAVDD2.705.25V
Digital Supply Voltage
RangeDVDD1.8AVDDV
Unity gain0.550.8mASLOW mode, all digital inputs
at DGND or DVDD, no load,
VREF = 2.5VForce sense0.91.2mA
Unity gain0.852
Operating Supply
Current
IAVDD +
IDVDD
FAST mode, all digital inputs
at DGND or DVDD, no load,
VREF = 2.5VForce sense1.22
Shutdown Supply
Current
IAV D D ( S H D N )
ID V D D ( S H D N )
No clocks, all digital inputs at DGND or DVDD, all
DACs in shutdown mode0.51.0µA
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V Logic) (Figure 1)
(DVDD= 2.7V to 5.25V, DGND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SCLK FrequencyfSCLK2.7V < DVDD < 5.25V20MHz
SCLK Pulse-Width HightCH(Note 7)20ns
SCLK Pulse-Width LowtCL(Note 7)20ns
CS Fall to SCLK Rise Setup TimetCSS10ns
SCLK Rise to CS Rise Hold TimetCSH5ns
SCLK Rise to CS Fall Setup TimetCS010ns
DIN to SCLK Rise Setup TimetDS12ns
DIN to SCLK Rise Hold TimetDH5ns
SCLK Rise to DOUTDC1 Valid
Propagation DelaytDO1CL = 20pF, UPIO_ = DOUTDC1 mode30ns
SCLK Fall to DOUT_ Valid
Propagation DelaytDO2CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode30ns
CS Rise to SCLK Rise Hold TimetCS1MICROWIRE and SPI modes 0 and 310ns
CS Pulse-Width HightCSW45ns
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V Logic) (Figure 1) (continued)
(DVDD= 2.7V to 5.25V, DGND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
UPIO TIMING CHARACTERISTICS
DOUT Tri-State Time when Exiting
DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
tDOZCL = 20pF, from end of write cycle to UPIO_
in high impedance100ns
DOUTRB Tri-State Time from CS
RisetDRBZCL = 20pF, from rising edge of CS to UPIO_
in high impedance20ns
DOUTRB Tri-State Enable Time
from 8th SCLK RisetZENCL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state0ns
LDAC Pulse-Width LowtLDLFigure 520ns
LDAC Effective DelaytLDSFigure 6100ns
CLR, MID, SET Pulse-Width LowtCMSFigure 520ns
GPO Output Settling TimetGPFigure 6100ns
GPO Output High-Impedance
TimetGPZ100ns
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)
(DVDD= 1.8V to 5.25V, DGND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SCLK FrequencyfSCLK1.8V < DVDD < 5.25V10MHz
SCLK Pulse-Width HightCH(Note 7)40ns
SCLK Pulse-Width LowtCL(Note 7)40ns
CS Fall to SCLK Rise Setup TimetCSS20ns
SCLK Rise to CS Rise Hold TimetCSH0ns
SCLK Rise to CS Fall Setup TimetCS010ns
DIN to SCLK Rise Setup TimetDS20ns
DIN to SCLK Rise Hold TimetDH5ns
SCLK Rise to DOUTDC1 Valid
Propagation DelaytDO1CL = 20pF, UPIO_ = DOUTDC1 mode60ns
SCLK Fall to DOUT_ Valid
Propagation DelaytDO2CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode60ns
CS Rise to SCLK Rise Hold TimetCS1MICROWIRE and SPI modes 0 and 320ns
CS Pulse-Width HightCSW90ns
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1) (continued)
(DVDD= 1.8V to 5.25V, DGND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
tDOZCL = 20pF, from end of write cycle to UPIO_
in high impedance200ns
DOUTRB Tri-State Time from CS
RisetDRBZCL = 20pF, from rising edge of CS to UPIO_
in high impedance40ns
DOUTRB Tri-State Enable Time
from 8th SCLK RisetZENCL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state0ns
LDAC Pulse-Width LowtLDLFigure 540ns
LDAC Effective DelaytLDSFigure 6200ns
CLR, MID, SET Pulse-Width LowtCMSFigure 540ns
GPO Output Settling TimetGPFigure 6200ns
GPO Output High-Impedance
TimetGPZ200ns
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V Logic) (Figure 2)
(DVDD= 2.7V to 5.25V, DGND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SCLK FrequencyfSCLK2.7V < DVDD < 5.25V20MHz
SCLK Pulse-Width HightCH(Note 7)20ns
SCLK Pulse-Width LowtCL(Note 7)20ns
CS Fall to SCLK Fall Setup TimetCSS10ns
DSP Fall to SCLK Fall Setup TimetDSS10ns
SCLK Fall to CS Rise Hold TimetCSH5ns
SCLK Fall to CS Fall DelaytCS010ns
SCLK Fall to DSP Fall DelaytDS010ns
DIN to SCLK Fall Setup TimetDS12ns
DIN to SCLK Fall Hold TimetDH5ns
SCLK Rise to DOUT_ Valid
Propagation DelaytDO1CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode30ns
SCLK Fall to DOUTDC0 Valid
Propagation DelaytDO2CL = 20pF, UPIO_ = DOUTDC0 mode30ns
CS Rise to SCLK Fall Hold TimetCS1MICROWIRE and SPI modes 0 and 310ns
CS Pulse-Width HightCSW45ns
DSP Pulse-Width HightDSW20ns
DSP Pulse-Width LowtDSPWL(Note 8)20ns
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V Logic) (Figure 2) (continued)
(DVDD= 2.7V to 5.25V, DGND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
tDOZCL = 20pF, from end of write cycle to UPIO_
in high impedance100ns
DOUTRB Tri-State Time from CS
RisetDRBZCL = 20pF, from rising edge of CS to UPIO_
in high impedance20ns
DOUTRB Tri-State Enable Time
from 8th SCLK FalltZENCL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state0ns
LDAC Pulse-Width LowtLDLFigure 520ns
LDAC Effective DelaytLDSFigure 6100ns
CLR, MID, SET Pulse-Width LowtCMSFigure 520ns
GPO Output Settling TimetGPFigure 6100ns
GPO Output High-Impedance
TimetGPZ100ns
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)
(DVDD= 1.8V to 5.25V, DGND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SCLK FrequencyfSCLK1.8V < DVDD < 5.25V10MHz
SCLK Pulse-Width HightCH(Note 7)40ns
SCLK Pulse-Width LowtCL(Note 7)40ns
CS Fall to SCLK Fall Setup TimetCSS20ns
DSP Fall to SCLK Fall Setup TimetDSS20ns
SCLK Fall to CS Rise Hold TimetCSH0ns
SCLK Fall to CS Fall DelaytCS010ns
SCLK Fall to DSP Fall DelaytDS015ns
DIN to SCLK Fall Setup TimetDS20ns
DIN to SCLK Fall Hold TimetDH5ns
SCLK Rise to DOUT_ Valid
Propagation DelaytDO1CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode60ns
SCLK Fall to DOUTDC0 Valid
Propagation DelaytDO2CL = 20pF, UPIO_ = DOUTDC0 mode60ns
CS Rise to SCLK Fall Hold TimetCS1MICROWIRE and SPI modes 0 and 320ns
CS Pulse-Width HightCSW90ns
DSP Pulse-Width HightDSW40ns
DSP Pulse-Width LowtDSPWL(Note 8)40ns
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2) (continued)
(DVDD= 1.8V to 5.25V, DGND = 0, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO_ Modes
tDOZCL = 20pF, from end of write cycle to UPIO_
in high impedance200ns
DOUTRB Tri-State Time from CS
RisetDRBZCL = 20pF, from rising edge of CS to UPIO_
in high impedance40ns
DOUTRB Tri-State Enable Time
from 8th SCLK FalltZENCL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state0ns
LDAC Pulse-Width LowtLDLFigure 540ns
LDAC Effective DelaytLDSFigure 6200ns
CLR, MID, SET Pulse-Width LowtCMSFigure 540ns
GPO Output Settling TimetGPFigure 6200ns
GPO Output High-Impedance
TimetGPZ200ns
Note 1:For the force-sense versions, FB_ is connected to its respective OUT_. VOUT(max) = VREF / 2, unless otherwise noted.
Note 2:Linearity guaranteed from decimal code 40 to 4095 for the MAX5290A/MAX5291A (12-bit, A-grade), code 82 to 4095 for the
MAX5290B/MAX5291B (12-bit, B-grade), code 21 to 1023 for the MAX5292/MAX5293 (10-bit), and code 5 to 255 for the
MAX5294/MAX5295 (8-bit).
Note 3:DAC-to-DAC crosstalk is measured as follows: outputs of DACA and DACB are set to full scale and the output of DACB is
measured. While keeping DACB unchanged, the output of DACA is transitioned to zero scale and the ∆VOUTof DACB is
measured. The procedure is repeated with DACA and DACB interchanged. DAC-to-DAC crosstalk is the maximum ∆VOUT
measured.
Note 4:Represents the functional range. The linearity is guaranteed at VREF= 2.5V. See the Typical Operating Characteristicssec-
tion for linearity at other voltages.
Note 5:Guaranteed by design.
Note 6:The reference -3dB bandwidth is measured with a 0.1VP-Psine wave on VREFand with the input code at full scale.
Note 7:In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-
lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns
(2.7V) or 50ns (1.8V).
Note 8:The falling edge of DSPstarts a DSP-type bus cycle, provided that CSis also active low to select the device. DSPactive low
and CSactive low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CScan be permanently low in this mode of
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Typical Operating Characteristics
(AVDD= DVDD= 3V, VREF= 2.5V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = floating, TA= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (MAX5290A)
MAX5290 toc01
INPUT CODE
INL (LSB)
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (MAX5291A)
MAX5290 toc02
INPUT CODE
INL (LSB)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
MAX5290 toc03
DIGITAL INPUT CODE
INL (LSB)
UNITY GAIN
B-GRADE
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
MAX5290 toc04
DIGITAL INPUT CODE
INL (LSB)
UNITY GAIN
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
MAX5290 toc05
DIGITAL INPUT CODE
INL (LSB)
UNITY GAIN
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
MAX5290 toc06
DIGITAL INPUT CODE
DNL (LSB)
UNITY GAIN
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
MAX5290 toc07
DIGITAL INPUT CODE
DNL (LSB)
UNITY GAIN
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
MAX5290 toc08
DIGITAL INPUT CODE
DNL (LSB)
UNITY GAIN
INTEGRAL NONLINEARITY
vs. TEMPERATURE (A-GRADE)
MAX5290 toc09
TEMPERATURE (°C)
INL (LSB)
UNITY GAIN
FORCE
SENSE
MIDSCALE
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACsypical Operating Characteristics (continued)
(AVDD= DVDD= 3V, VREF= 2.5V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = floating, TA= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. TEMPERATURE (12-BIT)
MAX5290 toc10
TEMPERATURE (°C)
INL (LSB)3510-15
UNITY GAIN
B-GRADE
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE (12-BIT)
MAX5290 toc11
TEMPERATURE (°C)
DNL (LSB)3510-15
UNITY GAIN
MAX5290 toc12
VREF (V)
INL (LSB)
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE (MAX5290A)
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE (MAX5291A)
MAX5290 toc13
VREF (V)
INL (LSB)
OFFSET ERROR vs. TEMPERATURE
(A-GRADE)
MAX5290 toc14
TEMPERATURE (°C)
OFFSET ERROR (mV)
UNITY GAIN
FORCE
SENSE
CODE = 40
UNITY GAIN: 1 LSB = 0.6mV
FORCE SENSE: 1 LSB = 0.3mV
OFFSET ERROR vs. TEMPERATURE
MAX5290 toc15
TEMPERATURE (°C)
OFFSET ERROR (LSB)3510-15
FORCE SENSE
UNITY GAIN
UNITY GAIN: 1 LSB = 0.6mV
FORCE SENSE: 1 LSB = 0.3mV
GAIN ERROR vs. TEMPERATURE
(A-GRADE)
MAX5290 toc16
TEMPERATURE (°C)
GAIN ERROR (LSB)
UNITY GAIN
FORCE
SENSE
UNITY GAIN: 1 LSB = 0.6mV
FORCE SENSE: 1 LSB = 0.3mV
GAIN ERROR vs. TEMPERATURE
MAX5290 toc17
TEMPERATURE (°C)
GAIN ERROR (LSB)3510-15
FORCE SENSE
UNITY GAIN
UNITY GAIN: 1 LSB = 0.6mV
FORCE SENSE: 1 LSB = 0.3mV
REFERENCE INPUT BANDWIDTH
MAX5290 toc18
FREQUENCY (Hz)
GAIN (dB)100k10k1k
010M
VREF = 0.1VP-P AT 2.5VDC
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. DIGITAL
INPUT CODE (FORCE SENSE)
MAX5290 toc19
DIGITAL INPUT CODE
SUPPLY CURRENT (mA)
SLOW MODE
12-BIT
NO LOAD
SUPPLY CURRENT vs. DIGITAL
INPUT CODE (UNITY GAIN)
MAX5290 toc20
DIGITAL INPUT CODE
SUPPLY CURRENT (mA)
SLOW MODE
12-BIT
NO LOAD
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (FORCE SENSE)
MAX5290 toc21
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
FAST MODE
I = IAVDD + IDVDD
AVDD = DVDD
NO LOAD
SLOW MODE
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (UNITY GAIN)
MAX5290 toc22
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
FAST MODE
I = IAVDD + IDVDD
AVDD = DVDD
NO LOAD
SLOW MODE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5290 toc23
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (nA)
FORCE SENSE
AVDD = DVDD
I = IAVDD + IDVDD
NO LOAD
UNITY GAIN
OFFSET ERROR vs. TEMPERATURE
MAX5290 toc24
TEMPERATURE (°C)
OFFSET ERROR (LSB)FORCE SENSE
B-GRADE
UNITY GAIN: 1 LSB = 1mV
FORCE SENSE: 1 LSB = 0.5mV
UNITY GAIN
GAIN ERROR vs. TEMPERATURE
MAX5290 toc25
TEMPERATURE (°C)
GAIN ERROR (LSB)
FORCE SENSE
B-GRADE
UNITY GAIN: 1 LSB = 1mV
FORCE SENSE: 1 LSB = 0.5mV
UNITY GAIN
OUTPUT VOLTAGE vs. OUTPUT
SOURCE/SINK CURRENT
MAX5290 toc26
IOUT (mA)
OUTPUT VOLTAGE (V)
MIDSCALE
UNITY GAIN
VREF = 4.096V
200ns/div
MAJOR-CARRY TRANSITION GLITCH
OUT_
(AC-COUPLED)
10mV/div
MAX5290 toc27
2V/div
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
400ns/div
SETTLING TIME POSITIVE
OUT_
2V/div
MAX5290 toc28
2V/div
FULL-SCALE TRANSITION
400ns/div
SETTLING TIME NEGATIVE
OUT_
2V/div
MAX5290 toc29
2V/div
FULL-SCALE TRANSITION
REFERENCE INPUT BANDWIDTH
MAX5290 toc30
FREQUENCY (kHz)
GAIN (dB)
-2510,000
VREF = 0.1VP-P AT 4.096VDC
UNITY GAIN
REFERENCE FEEDTHROUGH AT 1kHz
MAX5290 toc31
FREQUENCY (kHz)
0.55.5100μs/div
DAC-TO-DAC CROSSTALK
OUTB
1mV/div
MAX5290 toc32
OUTA
2V/div
1μs/div
DIGITAL FEEDTHROUGH
OUT_
(AC-COUPLED)
10mV/div
MAX5290 toc33
SCLK
2V/div
20μs/div
POWER-UP GLITCH
AVDD
2V/div
MAX5290 toc34
OUT_
1V/div
PU = FLOATING
10μs/div
EXITING SHUTDOWN TO MIDSCALE
OUT_
1V/div
MAX5290 toc35
UPIO_
2V/div
PU = FLOATING
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Pin Description
PIN
MAX5290
MAX5292
MAX5294
MAX5291
MAX5293
MAX5295
THIN QFNTSSOPTHIN QFNTSSOP
NAMEFUNCTION13DSP
Clock Enable. Connect DSP to DVDD at power-up to transfer
data on the rising edge of SCLK. Connect DSP to DGND at
power-up to transfer data on the falling edge of SCLK.324DINSerial Data Input35CSActive-Low Chip-Select Input546SCLKSerial Clock Input57DVDDDigital Supply768DGNDDigital Ground879AGNDAnalog Ground810AVDDAnalog Supply10911OUTBDACB Output—1012FBBFeedback for DACB Output Buffer111113REFReference Input—1214FBAFeedback for DACA Output Buffer
11, 13———N.C.No Connection. Not internally connected.121315OUTADACA Output131416PU
Power-Up State Select Input. Connect PU to DVDD to set OUTA
and OUTB to full scale upon power-up. Connect PU to DGND to
set OUTA and OUTB to zero upon power-up. Leave PU floating
to set OUTA and OUTB to midscale upon power-up.14151UPIO2User-Programmable Input/Output 21162UPIO1User-Programmable Input/Output 1——EPExposed Paddle (QFN Only). Not internally connected. Do not
connect to circuitry.
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Functional Diagrams
MAX5290
MAX5292
MAX5294
DOUT
REGISTER
16-BIT SHIFT
REGISTER
SCLK
DIN
DSP
SERIAL
INTERFACE
CONTROL
MUX
AVDD
UPIO1
UPIO2
REF
UPIO1 AND
UPIO2
LOGICPOWER-DOWN
LOGIC AND
REGISTER
DECODE
CONTROL
INPUT
REGISTER
DAC
REGISTERDAC A
OUTA
INPUT
REGISTERDAC B
OUTB
DAC
REGISTER
DVDDAGNDDGND
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Functional Diagrams (continued)
MAX5291
MAX5293
MAX5295
DOUT
REGISTER
16-BIT SHIFT
REGISTER
SCLK
DIN
DSP
SERIAL
INTERFACE
CONTROL
MUX
AVDD
UPIO1
UPIO2
REF
UPIO1 AND
UPIO2
LOGICPOWER-DOWN
LOGIC AND
REGISTER
DECODE
CONTROL
INPUT
REGISTER
DAC
REGISTERDAC A
OUTA
FBA
INPUT
REGISTERDAC B
OUTB
FBB
DAC
REGISTER
DVDDAGNDDGND
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Detailed Description
The MAX5290–MAX5295 dual, 12-/10-/8-bit, voltage-
output digital-to-analog converters (DACs) offer
buffered outputs and a 3µs maximum settling time at
the 12-bit level. The DACs operate from a single 2.7V to
5.25V analog supply and a separate 1.8V to AVDDdigi-
tal supply. The MAX5290–MAX5295 include an input
register and DAC register for each channel and a
16-bit data-in/data-out shift register. The 3-wire serial
interface is compatible with SPI, QSPI, MICROWIRE,
and DSP applications. The MAX5290–MAX5295 pro-
vide two user-programmable digital I/O ports, which
are programmed through the serial interface. The exter-
nally selectable power-up states of the DAC outputs
are either zero scale, midscale, or full scale.
Reference Input
The reference input, REF, accepts both AC and DC val-
ues with a voltage range extending from 0.25V to
AVDD. The voltage at REF (VREF) sets the full-scale out-
put of the DACs. Determine the output voltage using
the following equation:
Unity-gain versions:
VOUT_= (VREFx CODE) / 2N
Force-sense versions (FB_ connected to OUT_):
VOUT= 0.5 x (VREFx CODE) / 2N
where CODE is the numeric value of the DAC’s binary
input code and N is the bits of resolution. For the
MAX5290/MAX5291, N = 12 and CODE ranges from 0
to 4095. For the MAX5292/MAX5293, N = 10 and
CODE ranges from 0 to 1023. For the MAX5294/
MAX5295, N = 8 and CODE ranges from 0 to 255.
Output Buffers
The DACA and DACB output-buffer amplifiers of the
MAX5290–MAX5295 are unity-gain stable with rail-to-
rail output voltage swings and a typical slew rate of
5.7V/µs. The MAX5290/MAX5292/MAX5294 provide
unity-gain outputs, while the MAX5291/MAX5293/
MAX5295 provide force-sense outputs. For the
MAX5291/MAX5293/MAX5295, access to the output
amplifier’s inverting input provides flexibility in output
gain setting and signal conditioning (see the
Applications Informationsection).
The MAX5290–MAX5295 offer FAST and SLOW-settling
time modes. In the FAST mode, the settling time is 3µs
(max), and the supply current is 2mA (max). In the SLOW
mode, the settling time is 6µs (max), and the supply cur-
rent drops to 0.8mA (max). See the Digital Interfacesec-
tion for settling-time mode programming details.
Use the serial interface to set the shutdown output
impedance of the amplifiers to 1kΩor 100kΩfor the
MAX5290/MAX5292/MAX5294 and 1kΩor high imped-
ance for the MAX5291/MAX5293/MAX5295. The DAC
outputs can drive a 2kΩ(typ) load and are stable with
up to 500pF (typ) of capacitive load.
Power-On Reset
At power-up, all DAC outputs power up to full scale,
midscale, or zero scale, depending on the configuration
of the PU input. Connect PU to DVDDto set OUT_ to full
scale upon power-up. Connect PU to DGND to set
OUT_ to zero scale upon power-up. Leave PU floating
to set OUT_ to midscale.
Digital Interface
The MAX5290–MAX5295 use a 3-wire serial interface
that is compatible with SPI, QSPI, MICROWIRE, and
DSPs (Figures 1 and 2). Connect DSPto DVDDbefore
power-up to clock data in on the rising edge of SCLK.
Connect DSPto DGND before power-up to clock data in
on the falling edge of SCLK. After power-up, the device
enters DSP frame sync mode on the first rising edge of
DSP. Refer to theProgrammer’s Handbookfor details.
Each MAX5290–MAX5295 includes a 16-bit input shift
register. The data is loaded into the input shift register
through the serial interface. The 16 bits can be sent in
two serial 8-bit packets or one 16-bit word (CSmust
remain low until all 16 bits are transferred). The data is
loaded MSB first. For the MAX5290/MAX5291, the 16
bits consist of 4 control bits (C3–C0) and 12 data bits
(D11–D0) (see Table 1). For the 10-bit MAX5292/
MAX5293 devices, D11–D2 are the data bits and D1
and D0 are sub-bits. For the 8-bit MAX5294/
MAX5295 devices, D11–D4 are the data bits and
D3–D0 are sub-bits. Set all sub-bits to zero for optimum
performance.
Each DAC channel includes two registers: an input reg-
ister and the DAC register. At power-up, the DAC out-
put is set according to the state of PU. The DACs are
double-buffered, which allows any of the following for
each channel:Loading the input register without updating the DAC
registerLoading the DAC register without updating the input
registerUpdating the DAC register from the input registerUpdating the input and DAC registers simultaneously
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Table 1. Serial Write Data Format
MSB 16 BITS OF SERIAL DATALSB
CONTROL BITSDATA BITSC2C1C0D11D10D9D8D7D6D5D4D3D2D1D0
Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)
Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled)
SCLK
DIN
DOUTDC1*
DOUTDC0
DOUTRB*
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
SEE THE DATA OUTPUT SECTION FOR DETAILS.
tCH
tDS
tCS0tDHtCSH
tDO1
tDO2
tCLC3C1D0
tCSWtCS1
DOUT VALID
DOUT VALID
tCSS
SCLK
DIN
DOUTDC0*
DOUTDC1
DOUTRB*
DSP
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
SEE THE DATA OUTPUT SECTION FOR DETAILS.
tCL
tDS
tCSS
tDSWtDSPWLtD02
tD01
tDHtCS0
tCHC2C1D0
tCSH
tCSW
tDSStCS1
tDS0
DOUT VALID
DOUT VALID

Partno	Mfg	Dc	Qty	Available	Descript
MAX5293EUE+	MAXIM	N/a	10	avai	Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs