MAX525ACAP ,Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial InterfaceELECTRICAL CHARACTERISTICS(V = +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, R = 5kΩ, C = 100pF ..
MAX525ACAP+ ,Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial InterfaceMAX52519-1098; Rev 2; 10/02Low-Power, Quad, 12-Bit Voltage-Output DACwith Serial Interface_________ ..
MAX525ACAP+ ,Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial InterfaceELECTRICAL CHARACTERISTICS(V = +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, R = 5kΩ, C = 100pF ..
MAX525ACPP ,Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial InterfaceGeneral Description __________
MAX525ACPP+ ,Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial InterfaceMAX52519-1098; Rev 2; 10/02Low-Power, Quad, 12-Bit Voltage-Output DACwith Serial Interface_________ ..
MAX525AEAP , Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial Interface
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MAX9723DETE+TCJ6 ,Stereo DirectDrive® Headphone Amplifier with BassMax, Volume Control, and I²CFeatures®● 62mW, DirectDrive Headphone Amplifier Eliminates The MAX9723 stereo DirectDrive headphon ..
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MAX525ACAP-MAX525ACPP-MAX525BCAP-MAX525BCPP-MAX525BEAP
Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial Interface
__________________General DescriptionThe MAX525 combines four low-power, voltage-output,
12-bit digital-to-analog converters (DACs) and four pre-
cision output amplifiers in a space-saving, 20-pin pack-
age. In addition to the four voltage outputs, each
amplifier’s negative input is also available to the user.
This facilitates specific gain configurations, remote
sensing, and high output drive capacity, making the
MAX525 ideal for industrial-process-control applica-
tions. Other features include software shutdown, hard-
ware shutdown lockout, an active-low reset which clears
all registers and DACs to zero, a user-programmable
logic output, and a serial-data output.
Each DAC has a double-buffered input organized as an
input register followed by a DAC register. A 16-bit serial
word loads data into each input/DAC register. The serial
interface is compatible with SPI™/QSPI™ and
Microwire™. It allows the input and DAC registers to be
updated independently or simultaneously with a single
software command. The DAC registers can be simulta-
neously updated via the 3-wire serial interface. All logic
inputs are TTL/CMOS-logic compatible.
________________________ApplicationsIndustrial Process Controls
Automatic Test Equipment
Digital Offset and Gain Adjustment
Motion Control
Remote Industrial Controls
Microprocessor-Controlled Systems
______________________________FeaturesFour 12-Bit DACs with Configurable
Output Amplifiers+5V Single-Supply OperationLow Supply Current: 0.85mA Normal Operation
10µA Shutdown ModeAvailable in 20-Pin SSOPPower-On Reset Clears all Registers and
DACs to ZeroCapable of Recalling Last State Prior to ShutdownSPI/QSPI and Microwire CompatibleSimultaneous or Independent Control of DACs
via 3-Wire Serial InterfaceUser-Programmable Digital Output
MAX525
Low-Power, Quad, 12-Bit Voltage-Output DAC
with Serial Interface19-1098; Rev 1; 12/96
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
MAX525
Low-Power, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, RL= 5kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise
noted. Typical values are at TA= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND............................................................-0.3V to +6V
VDDto DGND...........................................................-0.3V to +6V
AGND to DGND..................................................................±0.3V
REFAB, REFCD to AGND...........................-0.3V to (VDD+ 0.3V)
OUT_, FB_ to AGND...................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND.............................................-0.3V to +6V
DOUT, UPO to DGND................................-0.3V to (VDD+ 0.3V)
Continuous Current into Any Pin.......................................±20mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 8.00mW/°C above +70°C).................640mW
SSOP (derate 8.00mW/°C above +70°C)......................640mW
CERDIP (derate 11.11mW/°C above +70°C).................889mW
Operating Temperature Ranges
MAX525_C_P........................................................0°C to +70°C
MAX525_E_P.....................................................-40°C to +85°C
MAX525_MJP..................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX525
Low-Power, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, RL= 5kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise
noted. Typical values are at TA= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
Note 1:Guaranteed from code 11 to code 4095 in unity-gain configuration.
Note 2:Accuracy is better than 1.0LSB for VOUT= 6mV to VDD- 60mV, guaranteed by PSR test on end points.
Note 3:RL= ¥, digital inputs at DGND or VDD.
__________________________________________Typical Operating Characteristics(VDD = +5V, TA = +25°C, unless otherwise noted.)
MAX525
Low-Power, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, RL= 5kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise
noted. Typical values are at TA= +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
MAX525
Low-Power, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
____________________________Typical Operating Characteristics (continued)(VDD = +5V, TA = +25°C, unless otherwise noted.)
MAX525
Low-Power, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
____________________________Typical Operating Characteristics (continued)(VDD = +5V, TA = +25°C, unless otherwise noted.)
MAX525
Low-Power, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
______________________________________________________________Pin Description
MAX525
Low-Power, Quad, 12-Bit Voltage-Output DAC
with Serial Interface
_______________Detailed DescriptionThe MAX525 contains four 12-bit, voltage-output digi-
tal-to-analog converters (DACs) that are easily
addressed using a simple 3-wire serial interface. It
includes a 16-bit data-in/data-out shift register, and
each DAC has a doubled-buffered input composed of
an input register and a DAC register (see Functional
Diagram). In addition to the four voltage outputs, each
amplifier’s negative input is available to the user.
The DACs are inverted R-2R ladder networks that con-
vert 12-bit digital inputs into equivalent analog output
voltages in proportion to the applied reference voltage
inputs. DACs A and B share the REFAB reference input,
while DACs C and D share the REFCD reference input.
The two reference inputs allow different full-scale output
voltage ranges for each pair of DACs. Figure 1 shows a
simplified circuit diagram of one of the four DACs.
Reference InputsThe two reference inputs accept positive DC and AC
signals. The voltage at each reference input sets the
full-scale output voltage for its two corresponding
DACs. The reference input voltage range is 0V to (VDD
- 1.4V). The output voltages (VOUT_)are represented by
a digitally programmable voltage source as:
VOUT_= (VREFx NB / 4096) x Gain
where NB is the numeric value of the DAC’s binary
input code (0 to 4095), VREFis the reference voltage,
and Gain is the externally set voltage gain.
The impedance at each reference input is code-depen-
dent, ranging from a low value of 10kΩwhen both
DACs connected to the reference have an input code
of 555 hex, to a high value exceeding several gigohms
(leakage currents) with an input code of 000 hex.
Because the input impedance at the reference pins is
code-dependent, load regulation of the reference
source is important.
The REFAB and REFCD reference inputs have a 10kΩ
guaranteed minimum input impedance. When the two
reference inputs are driven from the same source, the
effective minimum impedance is 5kΩ. A voltage refer-
ence with a load regulation of 6ppm/mA, such as the
MAX873, would typically deviate by 0.025LSB
(0.061LSB worst case) when driving both MAX525 ref-
erence inputs simultaneously at 2.5V. Driving the
REFAB and REFCD pins separately improves reference
accuracy.
In shutdown mode, the MAX525’s REFAB and REFCD
inputs enter a high-impedance state with a typical input
leakage current of 0.01µA.
The reference input capacitance is also code depen-
dent and typically ranges from 20pF with an input code
of all 0s to 100pF with an input code of all 1s.
Output AmplifiersAll MAX525 DAC outputs are internally buffered by preci-
sion amplifiers with a typical slew rate of 0.6V/µs. Access
to the inverting input of each output amplifier provides
the user greater flexibility in output gain setting/
signal conditioning (see the Applications Information sec-
tion).
With a full-scale transition at the MAX525 output, the
typical settling time to ±1/2LSB is 12µs when loaded
with 5kΩin parallel with 100pF (loads less than 2kΩ
degrade performance).
The MAX525 output amplifier’s output dynamic respons-
es and settling performances are shown in the Typical
Operating Characteristics.
Power-Down ModeThe MAX525 features a software-programmable shut-
down that reduces supply current to a typical value of
10µA. The power-down lockout (PDL) pin must be high to
enable the shutdown mode. Writing 1100XXXXXXXXXXXX
as the input-control word puts the MAX525 in power-
down mode (Table 1).
