MAX5259EEE-T ,+3V/+5V, Low-Power, 8-Bit Octal DACs with Rail-to-Rail Output BuffersApplicationsDigital Gain and Offset AdjustmentSUPP LY VOLT A G EPART TEMP. RANGE PIN-P ACKAG EProg ..
MAX525ACAP ,Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial InterfaceELECTRICAL CHARACTERISTICS(V = +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, R = 5kΩ, C = 100pF ..
MAX525ACAP+ ,Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial InterfaceMAX52519-1098; Rev 2; 10/02Low-Power, Quad, 12-Bit Voltage-Output DACwith Serial Interface_________ ..
MAX525ACAP+ ,Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial InterfaceELECTRICAL CHARACTERISTICS(V = +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, R = 5kΩ, C = 100pF ..
MAX525ACPP ,Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial InterfaceGeneral Description __________
MAX525ACPP+ ,Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial InterfaceMAX52519-1098; Rev 2; 10/02Low-Power, Quad, 12-Bit Voltage-Output DACwith Serial Interface_________ ..
MAX9723AETE+ ,Stereo DirectDrive® Headphone Amplifier with BassMax, Volume Control, and I²Capplications where space is at a premium and ● 1.8V to 3.6V Single-Supply Operationperformance is e ..
MAX9723DEBE+T ,Stereo DirectDrive® Headphone Amplifier with BassMax, Volume Control, and I²Cfeatures 32 discrete volume levels, eliminating the need Ordering Informationfor an external potent ..
MAX9723DETE+ ,Stereo DirectDrive® Headphone Amplifier with BassMax, Volume Control, and I²CBlock Diagram● PDA Audio ● MP3-Enabled Cellular1.8V TO 3.6V SUPPLY ● Portable CD Players ● Phones● ..
MAX9723DETE+T ,Stereo DirectDrive® Headphone Amplifier with BassMax, Volume Control, and I²Cfeatures Maxim’s industry-leading 2● I C/SMBus-Compatible Interfaceclick-and-pop suppression.● Avai ..
MAX9723DETE+TCJ6 ,Stereo DirectDrive® Headphone Amplifier with BassMax, Volume Control, and I²CFeatures®● 62mW, DirectDrive Headphone Amplifier Eliminates The MAX9723 stereo DirectDrive headphon ..
MAX9724AEBC+T ,60mW, DirectDrive, Stereo Headphone Amplifier with Low RF Susceptibility and ShutdownFeaturesThe MAX9724A/MAX9724B stereo headphone ampli- ♦ Improved RF Noise Rejection (Up to 67dB Ove ..
MAX5259EEE+-MAX5259EEE+T-MAX5259EEE-T
+3V/+5V, Low-Power, 8-Bit Octal DACs with Rail-to-Rail Output Buffers
General DescriptionThe MAX5258/MAX5259 are +3V/+5V single-supply,
digital serial-input, voltage-output, 8-bit octal digital-to-
analog converters (DACs). Internal precision buffers
swing Rail-to-Rail®, and the reference input range
extends from ground to the positive supply. The +5V
(MAX5258) and the +3V (MAX5259) feature a 10µA
(max) shutdown mode.
The serial interface is double-buffered. A 16-bit input
shift register is followed by eight 8-bit input registers
and eight 8-bit DAC registers. The 16-bit serial word
consists of two “don’t care” bits, three address bits,
three control bits, and eight data bits. The input and
DAC registers can both be updated independently or
simultaneously with a single software command. The
asynchronous control input (LDAC) provides simultane-
ous updating of all eight DAC registers.
The interface is compatible with SPI™, QSPI™ (CPOL =
CPHA = 0 or CPOL = CPHA = 1), and MICROWIRE™.
A buffered digital data output allows daisy-chaining of
serial devices.
The MAX5258/MAX5259 are available in a 16-pin QSOP
package.
________________________ApplicationsDigital Gain and Offset Adjustment
Programmable Attenuators
Programmable Current Sources
Portable Instruments
Features+2.7V to +5.5V Single-Supply OperationLow Supply Current: 1.3mALow-Power Shutdown Mode
0.54mA (MAX5259)
0.80mA (MAX5258)±1LSB DNL (max)±1LSB INL (max)Ground to VDD Reference Input RangeOutput Buffer Amplifiers Swing Rail-to-Rail10MHz Serial Interface, SPI, QSPI (CPOL = CPHA
= 0 or CPOL = CPHA = 1), and MICROWIRE-
CompatibleDouble-Buffered Registers for Synchronous
UpdatingSerial Data Output for Daisy-ChainingUltra-Small 16-Pin QSOP Package
+3V/+5V, Low-Power, 8-Bit Octal DACs
with Rail-to-Rail Output Buffers
Pin Configuration19-1844; Rev 1; 4/01
Ordering InformationSPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
MAX5258/MAX5259Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (MAX5258)(VDD= +4.5V to +5.5V, VREF= +4.096V, GND = 0, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
DIN, DOUT, CS, SCLK, LDACto GND.....................-0.3V to +6V
REF to GND................................................-0.3V to (VDD+ 0.3V)
OUT_ to GND...........................................................-0.3V to VDD
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
16-Pin Plastic QSOP (derate 8.3mW/°C about +70°C)...667mW
Operating Temperature Range ..........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
ELECTRICAL CHARACTERISTICS (MAX5258) (continued)(VDD= +4.5V to +5.5V, VREF= +4.096V, GND = 0, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical
values are at VDD= +5V and TA= +25°C.)
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
ELECTRICAL CHARACTERISTICS (MAX5259)(VDD= +2.7V to +3.3V, VREF= +2.5V, GND = 0, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values
are at VDD= +3V, and TA= +25°C.)
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
ELECTRICAL CHARACTERISTICS (MAX5259) (continued)(VDD= +2.7V to +3.3V, VREF= +2.5V, GND = 0, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values
are at VDD= +3V, and TA= +25°C.)
TIMING CHARACTERISTICS (MAX5258)(VREF= +4.096V, GND = 0, CDOUT= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at VDD = +5V and= +25°C.)
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
TIMING CHARACTERISTICS (MAX5259)(VREF= +2.5V, GND = 0, CDOUT= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at VDD= +3V and = +25°C.)
equal to the maximum offset specification to code FF hex (full scale). (See DAC Linearity and Voltage Offset section.)
Note 2:Output settling time is measured from the 50% point of the rising edge of CSto 1/2LSB of the final value of VOUT.
Note 3:Guaranteed by design, not production tested.
Note 4:If LDACis activated prior to the rising edge of CS, it must remain low for tLDACor longer after CSgoes high.
Note 5:When DOUT is not used. If DOUT is used, fCLK(max) is 4MHz due to SCLK to DOUT propagation delay.
Note 6:Serial data is clocked-out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of VDD).
Note 7:Serial data is clocked-out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of VDD).
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
Typical Operating Characteristics (continued)(TA = +25°C, unless otherwise noted.)
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
Typical Operating Characteristics (continued)(TA = +25°C, unless otherwise noted.)
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
Detailed Description
Serial InterfaceAt power-on, the serial interface and all DACs are
cleared and set to code zero. The serial data output
(DOUT) is set to transition on SCLK’s falling edge.
The MAX5258/MAX5259 communicate with micro-
processors (µPs) through a synchronous, 3-wire inter-
face (Figure 1). Data is sent MSB first and can be
transmitted in two 4-bit and one 8-bit (byte) packets, or
one 16-bit word. The first two bits are ignored. A 4-wire
interface adds a line for LDAC, allowing asynchronous
updating. Data is transmitted and received simultane-
ously.
Figure 2 shows the detailed serial-interface timing. Note
that the clock should be low if it is stopped between
updates. DOUT does not go into a high-impedance state
if the clock idles or CSis high.
Serial data is clocked into the data registers in MSB-first
format, with the address and configuration information
preceding the actual DAC data. Data is clocked in on
SCLK’s rising edge while CSis low. Data at DOUT is
clocked out 16 clock cycles later, either at SCLK’s falling
edge (default or mode 0) or rising edge (mode 1).must be low to enable the device. If CSis high, the
interface is disabled and DOUT remains unchanged.must go low at least 40ns before the first rising edge
of the clock pulse to properly clock in the first bit. Withlow, data is clocked into the MAX5258/MAX5259’s
internal shift register on the rising edge of the external
serial clock. Always clock in the full 16 bits.
Serial Input Data Format and Control CodesThe 16-bit serial input format, shown in Figure 3, com-
prises two “don’t care” bits, three DAC address bits (A2,
A1, A0), three control bits (C2, C1, C0), and eight data
bits (D7…D0). The 6-bit address/control code configures
the DAC as shown in Table 1.
Pin Description
