MAX5153AEEE+ ,Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable OutputsMAX5152/MAX515319-1304; Rev 0; 10/97Low -Pow er, Dual, 13-Bit Voltage-Output DACsw ith Configurable ..
MAX5153BCPE ,Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable OutputsApplications MAX5152ACEE 0°C to +70°C 16 QSOP ±1/2MAX5152BCEE 0°C to +70°C 16 QSOP ±1Industrial Pro ..
MAX5154ACEE ,Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial InterfaceELECTRICAL CHARACTERISTICS—MAX5154(V = +5V ±10%, V = V = 2.048V, R = 10kΩ, C = 100pF, T = T to T , ..
MAX5154AEEE ,Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial InterfaceApplicationsMAX5154BCEE 0°C to +70°C 16 QSOP ±1Industrial Process Control Remote Industrial Control ..
MAX5154AEEE+ ,Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial InterfaceMAX5154/MAX515519-1316; Rev 1; 12/97Low -Pow er, Dual, 12-Bit Voltage-Output DACsw ith Serial Inter ..
MAX5154BCEE ,Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial InterfaceFeatures' 12-Bit Dual DAC with Internal Gain of +2V/VThe MAX5154/MAX5155 low-power, serial, voltage ..
MAX964ESE ,Single/Dual/Quad / Ultra-High-Speed / +3V/+5V /Beyond-the-Rails ComparatorsGeneral Description ________
MAX964ESE ,Single/Dual/Quad / Ultra-High-Speed / +3V/+5V /Beyond-the-Rails ComparatorsFeaturesThe MAX961–MAX964/MAX997/MAX999 are low-power,' Ultra-Fast, 4.5ns Propagation Delay ultra-h ..
MAX964ESE+T ,Single/Dual/Quad, Ultra-High-Speed, +3V/+5V, Beyond-the-Rails ComparatorsElectrical Characteristics(V = +2.7V to +5.5V, V = 0V, C = 5pF, V = 0V, V = 0V, unless otherwise no ..
MAX9650ATA+ ,High-Current VCOM Drive Op Amps for TFT LCDsELECTRICAL CHARACTERISTICS (continued)(V = 19V, V = 0V, V = V = V /2, T = T to T , unless otherwise ..
MAX9650ATA+T ,High-Current VCOM Drive Op Amps for TFT LCDsELECTRICAL CHARACTERISTICS(V = 19V, V = 0V, V = V = V /2, T = T to T , unless otherwise noted. Typi ..
MAX9650ATA+TC93 ,High-Current VCOM Drive Op Amps for TFT LCDsFeaturesThe MAX9650/MAX9651 are single- and dual-channel♦ 1300mA Peak Output CurrentVCOM amplifiers ..
MAX5152AEEE+-MAX5153ACEE+-MAX5153AEEE+
Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs
Low-Power, Dual, 13-Bit Voltage-Output DACsith Configurable Outputs19-1304; Rev 0; 10/97
_______________General DescriptionThe MAX5152/MAX5153 low-power, serial, voltage-out-
put, dual 13-bit digital-to-analog converters (DACs)
consume only 500μA from a single +5V (MAX5152) or
+3V (MAX5153) supply. These devices feature Rail-to-
Rail®output swing and are available in space-saving
16-pin QSOP and DIP packages. Access to the invert-
ing input allows for specific gain configurations, remote
sensing, and high output current capability, making
these devices ideally suited for industrial process con-
trols. These devices are also well suited for digitally
programmable (4–20mA) current loops.
The 3-wire serial interface is SPI™/QSPI™ and
Microwire™ compatible. Each DAC has a double-
buffered input organized as an input register followed
by a DAC register, which allows the input and DAC reg-
isters to be updated independently or simultaneously.
Additional features include a programmable shutdown
(2μA), hardware-shutdown lockout, a separate voltage
reference for each DAC, power-on reset, and an active-
low clear input (CL) that resets all registers and DACs
to zero. The MAX5152/MAX5153 provide a programma-
ble logic output pin for added functionality, and a seri-
al-data output pin for daisy chaining.
________________________ApplicationsIndustrial Process ControlMotion Control
Digital Offset and Gain Digitally Programmable
Adjustment4–20mA Current Loops
Remote Industrial ControlsAutomatic Test Equipment
____________________________Features13-Bit Dual DAC with Configurable Output
AmplifierSingle-Supply Operation:+5V (MAX5152)
+3V (MAX5153)Rail-to-Rail Output SwingLow Quiescent Current:
500μA (normal operation)
2μA (shutdown mode)Power-On Reset Clears DAC Outputs to ZeroSPI/QSPI and Microwire CompatibleSpace-Saving 16-Pin QSOP Package Pin-Compatible 12-Bit Versions:
MAX5156/MAX5157
______________Ordering InformationRail-to-Rail is a registered trademark of Nippon Motorola Ltd. SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.*Dice are tested at TA= +25°C, DC parameters only.
Dice*0°C to +70°C±1MAX5152BC/D
16 QSOP0°C to +70°C±1MAX5152BCEE
16 QSOP0°C to +70°C±1/2MAX5152ACEE
16 Plastic DIP0°C to +70°C±1MAX5152BCPE
16 Plastic DIP0°C to +70°C±1/2
MAX5152ACPE
PIN-PACKAGETEMP. RANGEINL
(LSB)PARTREFACLDOUT
16-BIT
SHIFT
REGISTER
CONTROL
INPUT
REG A
SCLKUPOREFBDINCS
DAC A
DAC B
FBA
FBB
OUTA
OUTB
DAC
REG A
INPUT
REG BLOGIC
OUTPUT
DECODE
CONTROL
DAC
REG B
MAX5152
MAX5153
VDDAGNDDGNDPDL
_________________________________________________________Functional Diagram
Pin Configuration appears at end of data sheet.
Low-Power, Dual, 13-Bit Voltage-Output DACsith Configurable Outputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—MAX5152(VDD= +5V ±10%, VREFA= VREFB= 2.5V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at= +25°C, output buffer connected in unity-gain configuration (Figure 9).)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND............................................................-0.3V to +6V
VDDto DGND...........................................................-0.3V to +6V
AGND to DGND..................................................................±0.3V
FBA, FBB to AGND.....................................-0.3V to (VDD+ 0.3V)
REF_, OUT_ to AGND.................................-0.3V to (VDD+ 0.3V)
Digital Inputs (SCLK, DIN, CS, CL, PDL)
to DGND................................................................-0.3V to +6V
Digital Outputs (DOUT, UPO) to DGND.....-0.3V to (VDD+ 0.3V)
Maximum Current into Any Pin.........................................±20mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.5mW/°C above +70°C).............593mW
QSOP (derate 8.30mW/°C above +70°C).....................667mW
CERDIP (derate 10.00mW/°C above +70°C)................800mW
Operating Temperature Ranges
MAX5152_C_E/MAX5153_C_E ...........................0°C to +70°C
MAX5152_E_E/MAX5153_E_E..........................-40°C to +85°C
MAX5152_MJE/MAX5153_MJE......................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
VIN= 0V to VDD
CL, PDL, CS, DIN, SCLK
CL, PDL, CS, DIN, SCLK
Input code = 1FFF hex,
VREF= 1Vp-p at 2.5VDC, f = 25kHz
Input code = 0000 hex,
VREF= (VDD- 1.4Vp-p) at 1kHz
4.5V ≤VDD≤5.5V
Input code = 1FFF hex,
VREF= 0.67Vp-p at 2.5VDC
Normalized to 2.5V
(Note 1)
Guaranteed monotonic
Code = 20
Minimum with code 1555 hex
Normalized to 2.5V
CONDITIONS8CINInput Capacitance0.001±1IINInput Leakage Current200VHYSInput Hysteresis0.8VILInput Low Voltage3.0VIHInput High Voltage82SINADSignal-to-Noise plus
Distortion Ratio-85Reference Feedthrough
kHz600Reference 3dB Bandwidth1420RREFReference Input Resistance0VDD-
1.4REFReference Input Range
±1/2
Bits13NResolution
μV/V20200PSRRVDDPower-Supply
Rejection Ratio
ppm/°C3Gain-Error Tempco
LSB-0.5±6Gain Error
LSB±1INLIntegral Nonlinearity
LSB±1DNLDifferential Nonlinearity±6VOSOffset Error
ppm/°C3TCVOSOffset Tempco
UNITSMINTYPMAXSYMBOLPARAMETERMAX5152A
MAX5152B
STATIC PERFORMANCE
REFERENCE INPUT
MULTIPLYING-MODE PERFORMANCE
DIGITAL INPUTS
Low-Power, Dual, 13-Bit Voltage-Output DACith Configurable Outputs
ELECTRICAL CHARACTERISTICS—MAX5152 (continued)(VDD= +5V ±10%, VREFA= VREFB= 2.5V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at= +25°C, output buffer connected in unity-gain configuration (Figure 9).)
Note 1:Accuracy is specified from code 20 to code 8191.
Note 2:Accuracy is better than 1LSB for VOUTgreater than 6mV and less than VDD- 50mV. Guaranteed by PSRR test at the end
points.
Note 3:Digital inputs are set to either VDDor DGND, code = 0000 hex, RL= ¥.
Note 4:SCLK minimum clock period includes rise and fall times.= VDD, fDIN= 100kHz, VSCLK= 5Vp-p
ISOURCE= 2mA
Rail-to-rail (Note 2)
To 1/2LSB of full-scale, VSTEP= 2.5V
ISINK= 2mA
CONDITIONSnV-s5Digital Crosstalk
nV-s5Digital Feedthrough25Time Required to Exit
Shutdown0±0.1IFB_Current into FBA or FBBVDD-
0.5VOHOutput High Voltage0 to VDDOutput Voltage Swing20Output Settling Time0.130.40VOLOutput Low Voltage
V/μs0.75SRVoltage Output Slew Rate
UNITSMINTYPMAXSYMBOLPARAMETER(Note 4)
(Note 3)
(Note 3)40tCLSCLK Pulse Width Low40tCHSCLK Pulse Width High100tCPSCLK Clock Period±1Reference Current in
Shutdown210IDD(SHDN)Power-Supply Current in
Shutdown0.50.65IDDPower-Supply Current4.55.5VDDPositive Supply Voltage40tDSDIN Setup Time0tCHSSCLK Rise to CSRise Hold
Time40tCSSCSFall to SCLK Rise Setup
Time
CLOAD= 200pF
CLOAD= 200pF80tDO2SCLK Fall to DOUT Valid
Propagation Delay80tDO1SCLK Rise to DOUT Valid
Propagation Delay0tDHDIN Hold Time100tCSWCSPulse Width High40tCS1CSRise to SCLK Rise Hold10tCS0SCLK Rise to CSFall Delay
DIGITAL OUTPUTS (DOUT, UPO)
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS
Low-Power, Dual, 13-Bit Voltage-Output DACsith Configurable Outputs
ELECTRICAL CHARACTERISTICS—MAX5153(VDD= +2.7V to +3.6V, VREFA= VREFB= 1.25V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values
are at TA= +25°C, output buffer connected in unity-gain configuration (Figure 9).)
VIN= 0V to VDD
CL, PDL, CS, DIN, SCLK
CL, PDL, CS, DIN, SCLK
Input code = 1FFF hex,
VREF= 1Vp-p at 1.25VDC, f = 15kHz
Input code = 0000 hex,
VREF= (VDD- 1.4V) at 1kHz
2.7V ≤VDD≤3.6V
Input code = 1FFF hex,
VREF(AC)= 0.67Vp-p at 1.25VDC
Normalized to 1.25V
(Note 5)
Guaranteed monotonic
Code = 40
Minimum with code 1555 hex
Normalized to 1.25V
CONDITIONS8CINInput Capacitance0±0.1IINInput Leakage Current200VHYSInput Hysteresis0.8VILInput Low Voltage2.2VIHInput High Voltage73SINADSignal-to-Noise plus
Distortion Ratio-92Reference Feedthrough
kHz600Reference 3dB Bandwidth14RREFReference Input Resistance0VDD-
1.4REFReference Input Range
Bits13NResolution
μV/V20320PSRRVDDPower-Supply
Rejection Ratio
ppm/°C6Gain-Error Tempco
LSB-0.5±8Gain Error
LSB±2INLIntegral Nonlinearity
LSB±1DNLDifferential Nonlinearity±6VOSOffset Error
ppm/°C6TCVOSOffset Tempco
UNITSMINTYPMAXSYMBOLPARAMETERMAX5153A
MAX5153B
ISINK= 2mA
ISOURCE= 2mA0.130.4VOLOutput Low VoltageVDD- 0.5VOHOutput High Voltage
STATIC PERFORMANCE
REFERENCE INPUT (VREF)
MULTIPLYING-MODE PERFORMANCE
DIGITAL INPUTS
DIGITAL OUTPUTS (DOUT, UPO)
Low-Power, Dual, 13-Bit Voltage-Output DACith Configurable Outputs
ELECTRICAL CHARACTERISTICS—MAX5153 (continued)(VDD= +2.7V to +3.6V, VREFA= VREFB= 1.25V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values
are at TA= +25°C, output buffer connected in unity-gain configuration (Figure 9).)= VDD, fDIN= 100kHz, VSCLK= 3Vp-p
(Note 4)
(Note 7)
(Note 7)
Rail-to-rail (Note 6)
To 1/2LSB of full-scale, VSTEP= 1.25VtCLSCLK Pulse Width Low
CONDITIONS40tCHSCLK Pulse Width High
nV-s5Digital Crosstalk
nV-s5Digital Feedthrough25Time Required to Exit
Shutdown0±0.1IFB_Current into FBA or FBB100tCPSCLK Clock Period±1Reference Current in
Shutdown18IDD(SHDN)Power-Supply Current in
Shutdown0.50.6IDDPower-Supply Current2.73.6VDDPositive Supply Voltage50tDSDIN Setup Time0tCHSSCLK Rise to CSRise Hold
Time40tCSSCSFall to SCLK Rise Setup
Time
CLOAD= 200pF0 to VDDOutput Voltage Swing25Output Settling Time
CLOAD= 200pF120
V/μs0.75SRVoltage Output Slew Rate
UNITSMINTYPMAXSYMBOLPARAMETERtDO2SCLK Fall to DOUT Valid
Propagation Delay120tDO1SCLK Rise to DOUT Valid
Propagation Delay0tDHDIN Hold Time100tCSWCSPulse Width High40tCS1CSRise to SCLK Rise Hold10tCS0SCLK Rise to CSFall Delay
Note 4:SCLK minimum clock period includes rise and fall times.
Note 5:Accuracy is specified from code 40 to code 8191.
Note 6:Accuracy is better than 1LSB for VOUTgreater than 6mV and less than VDD- 100mV. Guaranteed by PSRR test at the end
points.
Note 7:Digital inputs are set to either VDDor DGND, code = 0000 hex, RL= ¥.
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS
Low-Power, Dual, 13-Bit Voltage-Output DACsith Configurable Outputs
__________________________________________Typical Operating Characteristics(VDD= +5V, RL= 10kΩ, CL= 100pF, FB_ tied to OUT_, TA= +25°C, unless otherwise noted.)
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
AX5152 TO
C01
FREQUENCY (kHz)
(d
VREF = 0.67Vp-p AT 2.5VDC
CODE = 1FFF (HEX)
SUPPLY CURRENT
vs. TEMPERATURE
AX5152 TO
C02
TEMPERATURE (°C)
(m
CODE = 1FFF (HEX)
CODE = 0000 (HEX)
RL = ¥
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
AX5152 TOC
FREQUENCY (kHz)
(d
VREF = 1Vp-p AT 2.5VDC
CODE = 1FFF (HEX)
FULL-SCALE ERROR vs. LOAD
AX5152 TOC
LOAD (kW)
(L
VREF = 2.5V
OUTPUT FFT PLOT
5152-TOC
FREQUENCY (kHz)
(d
VREF = 3.6Vp-p AT 1.8VDC
f = 1kHz
CODE = 1FFF (HEX)
NOTE: RELATIVE TO FULL SCALE
REFERENCE FEEDTHROUGH AT 1kHz
AX5152-TO
C05
FREQUENCY (kHz)
(d
VREF = 3.6Vp-p AT 1.88VDC
CODE = 0000 (HEX)
POWER-DOWN CURRENT
vs. TEMPERATURE
AX5152 TOC
TEMPERATURE (°C)
(m
5V/div
AC COUPLED
OUT_
500mV/div
DYNAMIC-RESPONSE RISE TIMEMAX5152 TOC08s/div
5V/div
AC COUPLED
OUT_
500mV/div
DYNAMIC-RESPONSE FALL TIMEMAX5152 TOC09s/div
MAX5152
Low-Power, Dual, 13-Bit Voltage-Output DACith Configurable OutputsREFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
AX5152 TOC10
FREQUENCY (kHz)
(d
VREF = 0.67Vp-p AT 1.25VDC
CODE = 1FFF (HEX)
SUPPLY CURRENT
vs. TEMPERATURE
X5152 TO
C11
TEMPERATURE (°C)
(m
CODE = 1FFF (HEX)
CODE = 0000 (HEX)
RL = ¥
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
AX5152 TOC
FREQUENCY (kHz)
(d
VREF = 1Vp-p AT 1VDC
CODE = 1FFF (HEX)
FULL-SCALE ERROR vs. LOAD
AX5152 TOC
LOAD (kW)
(L
VREF = 1.25V
OUTPUT FFT PLOT
X5152-TOC
FREQUENCY (kHz)
(d
VREF = 1.6Vp-p AT 0.88VDC
f = 1kHz
CODE = 1FFF (HEX)
NOTE: RELATIVE TO FULL SCALE
REFERENCE FEEDTHROUGH AT 1kHz
AX5152-TO
C14
FREQUENCY (kHz)
(d
VREF = 1.6Vp-p AT 0.88VDC
CODE = 0000 (HEX)
POWER-DOWN CURRENT
vs. TEMPERATURE
AX5251 TO
C15
TEMPERATURE (°C)
(m
OUT_
500mV/div
DYNAMIC-RESPONSE RISE TIMEMAX5152 TOC17s/div
2V/div
OUT_
500mV/div
DYNAMIC-RESPONSE FALL TIMEMAX5152 TOC18s/div
2V/div
____________________________Typical Operating Characteristics (continued)(VDD= +3V, RL= 10kΩ, CL= 100pF, FB_ tied to OUT_, TA= +25°C, unless otherwise noted.)
MAX5153
Low-Power, Dual, 13-Bit Voltage-Output DACsith Configurable Outputs
____________________________Typical Operating Characteristics (continued)(VDD= +5V (MAX5152), VDD= +3V (MAX5153), RL= 10kΩ, CL= 100pF, FB_ tied to OUT_, TA= TMINto TMAX, unless otherwise
noted.)
OUTA
1V/div
OUTB
200mV/div
AC COUPLED
MAX5152
ANALOG CROSSTALKMAX5152 TOC21
200ms/div
SCLK
5V/div
OUTA
500mV/div
AC COUPLED
MAX5152
DIGITAL FEEDTHROUGHMAX5152 TOC22s/div
MAX5152/MAX5153MAX5152
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
AX5152 TOC
SUPPLY VOLTAGE (V)
(m
CODE = 1FFF (HEX)
CODE = 0000 (HEX)
RL = ¥0.30
MAX5153
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
5152 TO
C19a
SUPPLY VOLTAGE (V)
(m
CODE = 1FFF (HEX)
CODE = 0000 (HEX)
RL = ¥
2V/div
OUT_
10mV/div
AC COUPLED
MAX5152
MAJOR-CARRY TRANSITIONMAX5152 TOC20s/div
_______________Detailed DescriptionThe MAX5152/MAX5153 dual, 13-bit, voltage-output
DACs are easily configured with a 3-wire serial inter-
face. These devices include a 16-bit data-in/data-out
shift register, and each DAC has a double-buffered
input comprised of an input register and a DAC register
(see Functional Diagram). Both DACs use an inverted
R-2R ladder network that produces a weighted voltage
proportional to the input voltage value. Each DAC has
its own reference input to facilitate independent full-
scale values. Figure 1 depicts a simplified circuit dia-
gram of one of the two DACs.
Reference InputsThe reference inputs accept both AC and DC values
with a voltage range extending from 0V to (VDD- 1.4V).
Determine the output voltage using the following equa-
tion:
VOUT= VREFx NB / 8192
where NB is the numeric value of the DAC’s binary input
code (0 to 8191) and VREFis the reference voltage.
The reference input impedance ranges from 14kΩ(1555
hex) to several giga ohms (with an input code of 0000
hex). This reference input capacitance is code depen-
dent and typically ranges from 15pF with an input code
of all zeros to 50pF with an input code of all ones.
Output AmplifierThe output amplifier’s inverting input is available to the
user, allowing force and sense capability for remote
sensing and specific gain configurations. The inverting
input can be connected to the output to provide a unity-
gain buffered output. The output amplifiers have a typi-
cal slew rate of 0.75V/μs and settle to 1/2LSB within
25μs, with a load of 10kΩin parallel to 100pF. Loads
less than 2kΩdegrade performance.
Low-Power, Dual, 13-Bit Voltage-Output DACith Configurable Outputs
______________________________________________________________Pin Description
PINAnalog GroundAGND1
FUNCTIONNAMEDAC A Output VoltageOUTA2
Reference for DAC AREFA4
DAC A Output Amplifier Feedback Input. Inverting input of the output amplifier.FBA3
Chip-Select InputCS6
Serial Clock Input SCLK8
Serial Data InputDIN7
Active-Low Clear Input. Resets all registers to zero. DAC outputs go to 0V.CL5
Serial Data OutputDOUT10
Power-Down Lockout. The device cannot be powered down when PDLis low.PDL12
User-Programmable OutputUPO11
DAC B Output Amplifier Feedback Input. Inverting input of the output amplifier.FBB14
Positive Power SupplyVDD16
DAC B Output VoltageOUTB15
Reference Input for DAC BREFB13
Digital GroundDGND9
OUT_
FB_
SHOWN FOR ALL 1s ON DAC
D0 D10D11D122R2R2R2RRR
REF_
AGND
Figure 1. Simplified DAC Circuit Diagram
Power-Down ModeThe MAX5152/MAX5153 feature a software-program-
mable shutdown mode that reduces the typical supply
current to 2μA. The two DACs can be shut down inde-
pendently or simultaneously by using the appropriate
programming word. For instance, enter shutdown mode
(for both DACs) by writing an input control word of
111XXXXXXXXXXXXX (Table 1). In shutdown mode, the
reference inputs and amplifier outputs become high
impedance, and the serial interface remains active.
Data in the input registers is saved, allowing the
MAX5152/MAX5153 to recall the output state prior to
entering shutdown when returning to normal mode. Exit
shutdown by recalling the previous condition or by
updating the DAC with new information. When returning
to normal operation (exiting shutdown), wait 20μs for
output stabilization.
Serial Interface The MAX5152/MAX5153 3-wire serial interface is com-
patible with both Microwire (Figure 2) and SPI/QSPI
(Figure 3) serial-interface standards. The 16-bit serial
input word consists of an address bit, two control bits,
and 13 bits of data (MSB to LSB) as shown in Figure 4.
The address and control bits determines the response
of the MAX5152/MAX5153, as outlined in Table 1.
The MAX5152/MAX5153’s digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow for the DACs to act
independently.
Low-Power, Dual, 13-Bit Voltage-Output DACsith Configurable Outputs
D12................D0
MSBLSB
16-BIT SERIAL WORD
FUNCTIONC1C00 0 113 bits of DAC dataLoad input register A; DAC register is unchanged.
0 1 113 bits of DAC dataLoad all DAC registers from the shift register (start up both DACs with new
data).
1 1 013 bits of DAC dataLoad input register B; all DAC registers are updated.
0 1 013 bits of DAC dataLoad input register A; all DAC registers are updated.
1 0 113 bits of DAC dataLoad input register B; DAC register is unchanged.
0 0 01 1 0 x xxxxxxxxxShut down DAC A when PDL= 1.
0 0 01 0 1 x xxxxxxxxxUpdate DAC register B from input register B (start up DAC B with data previ-
ously stored in input register B).
0 0 0 0 0 1 x xxxxxxxxxUpdate DAC register A from input register A (start up DAC A with data previ-
ously stored in input register A).
1 1 1xxxxxxxxxxxxxShut down both DACs if PDL= 1.
1 0 0xxxxxxxxxxxxxUpdate both DAC registers from their respective input registers
(start up both DACs with data previously stored in the input registers).
0 0 01 1 1 x xxxxxxxxxShut down DAC B when PDL= 1.
0 0 0 0 1 0 x xxxxxxxxxUPO goes low (default).
0 0 00 1 1 x xxxxxxxxxUPO goes high.
0 0 01 0 0 1 xxxxxxxxxMode 1, DOUT clocked out on SCLK’s rising edge.
0 0 01 0 0 0 xxxxxxxxxMode 0, DOUT clocked out on SCLK’s falling edge (default).
0 0 00 0 0 x xxxxxxxxxNo operation (NOP).
Table 1. Serial-Interface Programming Commands “x” = don’t care
Note: When A0, C1, and C0 = “0”, D12, D11, D10, and D9 become control bits.
