MAX5041BEAI ,Dual-Phase, Parallelable, Average Current-Mode ControllersFeaturesThe MAX5038/MAX5041 dual-phase, PWM controllers♦ +4.75V to +5.5V or +8V to +28V Input Volta ..
MAX5041EAI ,Dual-Phase / Parallelable / Average Current-Mode ControllersFeaturesThe MAX5038/MAX5041 dual-phase, PWM controllers +4.75V to +5.5V or +8V to +28V Input Volta ..
MAX5041EAI ,Dual-Phase / Parallelable / Average Current-Mode ControllersELECTRICAL CHARACTERISTICS(V = +5V, circuit of Figure 1, T = -40°C to +85°C, unless otherwise noted ..
MAX5041EAI ,Dual-Phase / Parallelable / Average Current-Mode ControllersApplicationsServers and WorkstationsOrdering InformationPoint-Of-Load High-Current/High-DensityTele ..
MAX5041EAI+ ,Dual-Phase, Parallelable, Average Current-Mode ControllersApplications ♦ 28-Pin SSOP PackageServers and WorkstationsOrdering InformationPoint-Of-Load High-Cu ..
MAX5043ETN+ ,Two-Switch Power ICs with Integrated Power MOSFETs and Hot-Swap ControllerApplicationsMAX5042ATN -40°C to +125°C 56 TQFN● High-Eficiency Telecom/Datacom Power SuppliesMAX504 ..
MAX923CPA ,Ultra Low-Power, Single/Dual-Supply ComparatorsMAX921–MAX92419-0115; Rev 3; 3/95Ultra Low-Power, Single/Dual-Supply Comparators_______________
MAX923CPA ,Ultra Low-Power, Single/Dual-Supply ComparatorsELECTRICAL CHARACTERISTICS: 5V OPERATION (continued)(V+ = 5V, V- = GND = 0V, T = T to T , unless ot ..
MAX923CSA ,Ultra Low-Power, Single/Dual-Supply ComparatorsMAX921–MAX92419-0115; Rev 3; 3/95Ultra Low-Power, Single/Dual-Supply Comparators_______________
MAX923CSA ,Ultra Low-Power, Single/Dual-Supply ComparatorsFeaturesThe MAX921–MAX924 single, dual, and quad micro-' µMAX Package—Smallest 8-Pin SOpower, low-v ..
MAX923CSA+ ,Ultra Low-Power, Single/Dual-Supply ComparatorsApplications5 HYSTBattery-Powered SystemsThreshold DetectorsMAX9216 REFWindow ComparatorsGNDV-Oscil ..
MAX923CUA ,Ultra Low-Power, Single/Dual-Supply ComparatorsGeneral Description ________
MAX5041BEAI-MAX5041EAI+
Dual-Phase, Parallelable, Average Current-Mode Controllers
neral DescriptionThe MAX5038/MAX5041 dual-phase, PWM controllers
provide high-output-current capability in a compact
package with a minimum number of external compo-
nents. The MAX5038/MAX5041 utilize a dual-phase,
average current-mode control that enables optimal use
of low RDS(ON)MOSFETs, eliminating the need for exter-
nal heatsinks even when delivering high output currents.
Differential sensing enables accurate control of the out-
put voltage, while adaptive voltage positioning providestimum transient response. An internal regulator
enables operation with input voltage ranges of +4.75V to
+5.5V or +8V to +28V. The high switching frequency, up
to 500kHz per phase, and dual-phase operation allow
the use of low-output inductor values and input capacitor
values. This accommodates the use of PC board-
embedded planar magnetics achieving superior reliabili-
ty, current sharing, thermal management, compact size,
and low system cost.
The MAX5038/MAX5041 also feature a clock input
(CLKIN) for synchronization to an external clock, and a
clock output (CLKOUT) with programmable phase delay
(relative to CLKIN) for paralleling multiple phases. The
MAX5038 offers a variety of factory-trimmed preset output
voltages (see Selector Guide) and the MAX5041 offers an
adjustable output voltage from +1.0V to +3.3V.
The MAX5038/MAX5041 operate over the extended
industrial temperature range (-40°C to +85°C) and are
available in a 28-pin SSOP package. Refer to the
MAX5037 data sheet for a VRM 9.0-compatible, VID-
controlled output voltage controller in a 44-pin MQFP or
QFN package.
ApplicationsServers and Workstations
Point-Of-Load High-Current/High-Density
Telecom DC-DC Regulators
Networking Systems
Large-Memory Arrays
RAID Systems
High-End Desktop Computers
Features+4.75V to +5.5V or +8V to +28V Input Voltage
RangeUp to 60A Output CurrentInternal Voltage Regulator for a +12V or +24V
Power BusTrue Differential Remote Output SensingTwo Out-Of-Phase Controllers Reduce Input
Capacitance Requirement and Distribute Power
DissipationAverage Current-Mode Control
Superior Current Sharing Between Individual
Phases and Paralleled Modules
Accurate Current Limit Eliminates MOSFET and
Inductor DeratingIntegrated 4A Gate DriversSelectable Fixed Frequency 250kHz or 500kHz Per
Phase (Up to 1MHz for 2 Phases)Fixed (MAX5038) or Adjustable (MAX5041) Output
Voltages0.5% Accurate Reference (MAX5041B)External Frequency Synchronization from 125kHz
to 600kHzInternal PLL with Clock Output for Paralleling
Multiple DC-DC ConvertersThermal Protection28-Pin SSOP Package
Dual-Phase, Parallelable, Average Current-Modentrollers 19-2514; Rev 3; 8/04
Ordering Information
PARTTEMP RANGEPIN-
PACKAGE
OUTPUT
VOLTAGE
MAX5038EAI12-40°C to +85°C28 SSOPFixed +1.2V
MAX5038EAI15-40°C to +85°C28 SSOPFixed +1.5V
MAX5038EAI18-40°C to +85°C28 SSOPFixed +1.8V
MAX5038EAI25-40°C to +85°C28 SSOPFixed +2.5V
MAX5038EAI33-40°C to +85°C28 SSOPFixed +3.3V
MAX5041EAI-40°C to +85°C28 SSOPAdj +1.0V to
+3.3V
MAX5041BEAI-40°C to +85°C28 SSOPAdj +1.0V to
+3.3V
Pin Configuration appears at end of data sheet.
Dual-Phase, Parallelable, Average Current-Mode
Controllers
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= +5V, circuit of Figure 1, TA= -40°C to +85°C, unless otherwise noted. Typical specifications are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN to SGND.............................................................-0.3V to +30V
BST_ to SGND…………………………………….…-0.3V to +35V
DH_ to LX_................................-0.3V to [(VBST_ - VLX_) + 0.3V]
DL_ to PGND..............................................-0.3V to (VCC+ 0.3V)
BST_ to LX_..............................................................-0.3V to +6V
VCCto SGND............................................................-0.3V to +6V
VCCto PGND............................................................-0.3V to +6V
SGND to PGND.....................................................-0.3V to +0.3V
All Other Pins to SGND...............................-0.3V to (VCC+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C)............762mW
Operating Temperature Range...........................-40°C to +85°C
Maximum Junction Temperature.....................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SYSTEM SPECIFICATIONS28
Input Voltage RangeVINShort IN and VCC together for +5V input
operation4.755.5V
Quiescent Supply CurrentIQEN = VCC or SGND410mA
EfficiencyηILOAD = 52A (26A per phase)90%
OUTPUT VOLTAGEMAX5038 only, no load-0.8+0.8
Nominal Output Voltage
Accuracy
MAX5038 only, no load, VIN = VCC =
+4.75V to +5.5V or VIN = +8V to +28V
(Note 2)+1
MAX5041 only, no load0.9921.008
MAX5041 only, no load, VIN = VCC =
+4.75V to +5.5V or VIN = +8V to +28V0.9901.010
MAX5041B only, no load0.9951.005
SENSE+ to SENSE- Voltage
Accuracy
MAX5041B only, no load,
VIN = +8V to +28V0.9951.005
STARTUP/INTERNAL REGULATORVCC Undervoltage LockoutUVLOVCC falling4.04.154.5V
VCC Undervoltage Lockout
Hysteresis200mV
VCC Output AccuracyVIN = +8V to +28V, ISOURCE = 0 to 80mA4.855.15.30V
MOSFET DRIVERSOutput Driver ImpedanceRONLow or high output13Ω
Output Driver Source/Sink
CurrentIDH_, IDL_4A
Non-Overlap TimetNOCDH_/DL_ = 5nF60ns
Dual-Phase, Parallelable, Average Current-Modentrollers
ELECTRICAL CHARACTERISTICS (continued)(VCC= +5V, circuit of Figure 1, TA= -40°C to +85°C, unless otherwise noted. Typical specifications are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
OSCILLATOR AND PLLCLKIN = SGND238250262Switching FrequencyfSWCLKIN = VCC475500525kHz
PLL Lock RangefPLL125600kHz
PLL Locking TimetPLL200μs
PHASE = VCC115120125
PHASE = unconnected859095CLKOUT Phase Shift
(at fSW = 125kHz)φCLKOUT
PHASE = SGND556065
degrees
CLKIN Input Pulldown CurrentICLKIN357μA
CLKIN High ThresholdVCLKINH2.4V
CLKIN Low ThresholdVCLKINL0.8V
CLKIN High Pulse WidthtCLKIN200ns
PHASE High ThresholdVPHASEH4V
PHASE Low ThresholdVPHASEL1V
PHASE Input Bias CurrentIPHASEBIA-50+50μA
CLKOUT Output Low LevelVCLKOUTLISINK = 2mA (Note 2)100mV
CLKOUT Output High LevelVCLKOUTHISOURCE = 2mA (Note 2)4.5V
CURRENT LIMITAverage Current-Limit ThresholdVCLCSP_ to CSN_454851mV
Cycle-by-Cycle Current LimitVCLPKCSP_ to CSN_ (Note 3)90112130mV
Cycle-by-Cycle Overload
Response TimetRVCSP_ to VCSN_ = +150mV260ns
CURRENT-SENSE AMPLIFIERCSP_ to CSN_ Input ResistanceRCS_4kΩ
Common-Mode RangeVCMR(CS)-0.3+3.6V
Input Offset VoltageVOS(CS)-1+1mV
Amplifier GainAV(CS)18V/V
3dB Bandwidthf3dB4MHz
CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER)Transconductancegmca550μS
Open-Loop GainAVOL(CE)No load50dB
DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF)Common-Mode Voltage RangeVCMR(DIFF)-0.3+1.0V
DIFF Output VoltageVCMVSENSE+ = VSENSE- = 00.6V
Input Offset VoltageVOS(DIFF)-1+1mV
MAX5038/MAX5041 (+1.2V, +1.5V, +1.8V
output versions)0.99711.003Amplifier GainAV(DIFF)
MAX5038 (+2.5V and +3.3V output versions)0.4950.50.505
V/V
Dual-Phase, Parallelable, Average Current-Mode
Controllers
ELECTRICAL CHARACTERISTICS (continued)(VCC= +5V, circuit of Figure 1, TA= -40°C to +85°C, unless otherwise noted. Typical specifications are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS3dB Bandwidthf3dBCDIFF = 20pF3MHz
Minimum Output Current DriveIOUT(DIFF)1.0mA
SENSE+ to SENSE- Input
ResistanceRVS_50100kΩ
VOLTAGE-ERROR AMPLIFIER (EAOUT)Open-Loop GainAVOL(EA)70dB
Unity-Gain BandwidthfUGEA3MHz
EAN Input Bias CurrentIB(EA)VEAN = +2.0V-100+100nA
Error-Amplifier Output Clamping
VoltageVCLAMP(EA)With respect to VCM810918mV
THERMAL SHUTDOWNThermal ShutdownTSHDN150°C
Thermal-Shutdown Hysteresis8°C
EN INPUTEN Input Low VoltageVENL1V
EN Input High VoltageVENH3V
EN Pullup CurrentIEN4.555.5μA
Note 1:Specifications from -40°C to 0°C are guaranteed by characterization but not production tested.
Note 2:Guaranteed by design. Not production tested.
Note 3:See Peak-Current Comparator section.
Dual-Phase, Parallelable, Average Current-Modentrollers
EFFICIENCY vs. OUTPUT CURRENT AND
INTERNAL OSCILLATOR FREQUENCYX5038/41 toc01
IOUT (A)
(%44403632282420161284
f = 500kHz
f = 250kHz
VIN = +5V
VOUT = +1.8V
EFFICIENCY vs. OUTPUT CURRENT
AND INPUT VOLTAGEAX5038/41 toc02
IOUT (A)
(%44403632282420161284
VIN = +12V
VIN = +5V
VOUT = +1.8V
fSW = 250kHz
EFFICIENCY vs. OUTPUT CURRENTAX5038/41 toc03
IOUT (A)
(%44403632282420161284
VIN = +24V
VOUT = +1.8V
fSW = 125kHz
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGEAX5038/41 toc04
IOUT (A)
(%44403632282420161284
VOUT = +1.1V
VOUT = +1.5VVOUT = +1.8V
VIN = +12V
fSW = 250kHz
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGEAX5038/41 toc05
IOUT (A)
(%44403632282420161284
VOUT = +1.1V
VOUT = +1.5VVOUT = +1.8V
VIN = +5V
fSW = 500kHz
SUPPLY CURRENT
vs. FREQUENCY AND INPUT VOLTAGEAX5038/41 toc06
FREQUENCY (kHz)
(m
VIN = +24V
VIN = +12V
VIN = +5VEXTERNALCLOCK
NO DRIVER LOAD
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCYAX5038/41 toc07
TEMPERATURE (°C)
(m3510-15
250kHz
125kHz
VIN = +12V
CDL_ = 22nF
CDH_ = 8.2nF
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCYAX5038/41 toc08
TEMPERATURE (°C)
(m3510-15
600kHz
500kHz
VIN = +5V
CDL_ = 22nF
CDH_ = 8.2nF
SUPPLY CURRENT
vs. LOAD CAPACITANCE PER DRIVERAX5038/41 toc09
CDRIVER (nF)
(m117953
VIN = +12V
fSW = 250kHz
Typical Operating Characteristic(Circuit of Figure 1. TA= +25°C, unless otherwise noted.)
Dual-Phase, Parallelable, Average Current-Mode
Controllers
Typical Operating Characteristics (continued)(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
CURRENT-SENSE THRESHOLD
vs. OUTPUT VOLTAGEAX5038/41 toc10
VOUT (V)
) (m
PHASE 2
PHASE 1
OUTPUT VOLTAGE vs. OUTPUT CURRENT
AND ERROR AMP GAIN (RF / RIN)AX5038/41 toc11
ILOAD (A)
T (V45403530252015105
VIN = +12V
VOUT = +1.8V
RF / RIN = 15
RF / RIN = 12.5
RF / RIN = 10
RF / RIN = 7.5
DIFFERENTIAL AMPLIFIER BANDWIDTHMAX5038/41 toc12
FREQUENCY (MHz)
(V
(d0.1
PHASE
GAIN
DIFF OUTPUT ERROR
vs. SENSE+ TO SENSE- VOLTAGEAX5038/41 toc13
∆VSENSE (V)
(%
VIN = +12V
NO DRIVER
VCC LOAD REGULATION
vs. INPUT VOLTAGEAX5038/41 toc14
ICC (mA)
(V
VIN = +24V
VIN = +12V
VIN = +8V
DC LOAD
VCC LINE REGULATIONX5038/41 toc15
VIN (V)
(V2420221214161810
ICC = 0
ICC = 40mA
VCC LINE REGULATIONAX5038/41 toc16
VIN (V)
(V
ICC = 80mA
DRIVER RISE TIME
vs. DRIVER LOAD CAPACITANCEAX5038/41 toc17
CDRIVER (nF)
(n261621116
DL_
DH_
VIN = +12V
fSW = 250kHz
DRIVER FALL TIME
vs. DRIVER LOAD CAPACITANCEAX5038/41 toc18
CDRIVER (nF)
tF (n261621116
DL_
DH_
VIN = +12V
fSW = 250kHz
Dual-Phase, Parallelable, Average Current-Modentrollers 100ns/div
HIGH-SIDE DRIVER (DH_)
SINK AND SOURCE CURRENTDH_
1.6A/div
MAX5038/41 toc19
VIN = +12V
CDH_ = 22nF
100ns/div
LOW-SIDE DRIVER (DL_)
SINK AND SOURCE CURRENTDL_
1.6A/div
MAX5038/41 toc20
VIN = +12V
CDL_ = 22nF
100μs/div
PLL LOCKING TIME
250kHz TO 350kHz AND
350kHz TO 250kHzCLKOUT
5V/div
MAX5038/41 toc21
PLLCMP
200mV/div
VIN = +12V
NO LOAD
350kHz
250kHz
100μs/div
PLL LOCKING TIME
250kHz TO 500kHz AND
500kHz TO 250kHzCLKOUT
5V/div
MAX5038/41 toc22
PLLCMP
200mV/div
VIN = +12V
NO LOAD
500kHz
250kHz
100μs/div
PLL LOCKING TIME
250kHz TO 150kHz AND
150kHz TO 250kHzCLKOUT
5V/div
MAX5038/41 toc23
PLLCMP
200mV/div
VIN = +12V
NO LOAD
250kHz
150kHz
40ns/div
HIGH-SIDE DRIVER (DH_)
RISE TIMEMAX5038/41 toc24
VIN = +12V
CDH_ = 22nF
DH_
2V/div
40ns/div
HIGH-SIDE DRIVER (DH_)
FALL TIMEMAX5038/41 toc25
DH_
2V/div
VIN = +12V
CDH_ = 22nF
40ns/div
LOW-SIDE DRIVER (DL_)
RISE TIMEMAX5038/41 toc26
DL_
2V/div
VIN = +12V
CDL_ = 22nF
40ns/div
LOW-SIDE DRIVER (DL_)
FALL TIMEMAX5038/41 toc27
DL_
2V/div
VIN = +12V
CDL_ = 22nF
Typical Operating Characteristics (continued)(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
Dual-Phase, Parallelable, Average Current-Mode
Controllers
Typical Operating Characteristics (continued)(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
500ns/div
OUTPUT RIPPLEMAX5038/41 toc28
VOUT
(AC-COUPLED)
10mV/div
VIN = +12V
VOUT = +1.75V
IOUT = 52A
2ms/div
INPUT STARTUP RESPONSEMAX5038/41 toc29
VIN
5V/div
VIN = +12V
VOUT = +1.75V
IOUT = 52A
VPGOOD
1V/div
VOUT
1V/div
1ms/div
ENABLE STARTUP RESPONSEMAX5038/41 toc30
VEN
2V/div
VPGOOD
1V/div
VOUT
1V/div
VIN = +12V
VOUT = +1.75V
IOUT = 52A
40μs/div
LOAD-TRANSIENT RESPONSEMAX5038/41 toc31
VIN = +12V
VOUT = +1.75V
ISTEP = 8A TO 52A
tRISE = 1μs
VOUT
50mV/div
Dual-Phase, Parallelable, Average Current-Modentrollers
Pin Description
PINNAMEFUNCTION1, 13CSP2,
CSP1
Current-Sense Differential Amplifier Positive Input. Senses the inductor current. The differential voltage
between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of 18.
2, 14CSN2,
CSN1Current-Sense Differential Amplifier Negative Input. Senses the inductor current.PHASEPhase-Shift Setting Input. Connect PHASE to VCC for 120°, leave PHASE unconnected for 90°, or connect
PHASE to SGND for 60° of phase shift between the rising edges of CLKOUT and CLKIN/DH1.PLLCMPExternal Loop-Compensation Input. Connect compensation network for the phase lock loop (see Phase-
Locked Loop section).
5, 7CLP2,
CLP1Current-Error Amplifier Output. Compensate the current loop by connecting an RC network to ground.SGNDSignal Ground. Ground connection for the internal control circuitry.SENSE+
Differential Output Voltage-Sensing Positive Input. Used to sense a remote load. Connect SENSE+ to
VOUT+ at the load. The MAX5038 regulates the difference between SENSE+ and SENSE- according to the
factory preset output voltage. The MAX5041 regulates the SENSE+ to SENSE- difference to +1.0V.SENSE-Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect SENSE- to
VOUT- or PGND at the load.DIFFDifferential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier.EANVoltage-Error Amplifier Inverting Input. Receives the output of the differential remote-sense amplifier.
Referenced to SGND.EAOUTVoltage-Error Amplifier Output. Connect to the external gain-setting feedback resistor. The external error
amplifier gain-setting resistors determine the amount of adaptive voltage positioningENOutput Enable. A logic low shuts down the power drivers. EN has an internal 5μA pullup current.
16, 26BST1,
BST2
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver supply.
Connect 0.47μF ceramic capacitors between BST_ and LX_.
17, 25DH1,
DH2High-Side Gate Driver Output. Drives the gate of the high-side MOSFET.
18, 24LX1, LX2Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal for
the high-side driver.
19, 23DL1, DL2Low-Side Gate Driver Output. Synchronous MOSFET gate drivers for the two phases.VCCInternal +5V Regulator Output. VCC is derived internally from the IN voltage. Bypass to SGND with 4.7μF
and 0.1μF ceramic capacitors.INSupply Voltage Connection. Connect IN to VCC for a +5V system. Connect the VRM input to IN through an
RC lowpass filter, a 2.2Ω resistor and a 0.1μF ceramic capacitor.PGNDPower Ground. Connect PGND, low-side synchronous MOSFET’s source, and VCC bypass capacitor
returns together.CLKOUTOscillator Output. CLKOUT is phase-shifted from CLKIN by the amount specified by PHASE. Use CLKOUT
to parallel additional MAX5038/MAX5041s.CLKIN
CMOS Logic Clock Input. Drive the internal oscillator with a frequency range between 125kHz and 600kHz.
The PWM frequency defaults to the internal oscillator if CLKIN is connected to VCC or SGND. Connect
CLKIN to SGND to set the internal oscillator to 250kHz or connect to VCC to set the internal oscillator to
500kHz. CLKIN has an internal 5μA pulldown current.
Dual-Phase, Parallelable, Average Current-Mode
Controllers MAX5038
MAX5041
PHASE 1
CSP1
DRV_VCC
RAMP1
GMIN
CLK
CLP1
CSN1
SHDNBST1
DL1
LX1
DH1
VCC
TO INTERNAL CIRCUITSCSP1
CSN1
CLP1
PHASE 2
CSP2
DRV_VCC
GMIN
CLK
CLP2
CSN2
SHDN
BST2
DL2
LX2
DH2
CSP2
CSN2
CLP2
PHASE-
LOCKED
LOOP
RAMP
GENERATOR
RAMP2
CLKIN
CLKOUT
PLLCMP
DIFF
AMP
ERROR
AMP
SENSE-
SENSE+
DIFF
EAN
EAOUT
PGND
PGND
PGND
SGND
VREF = VOUT for VOUT ≤ 1.8V (MAX5038)
VREF = VOUT/2 for VOUT > 1.8V (MAX5038)
VREF = +1.0V (MAX5041)
+5V
LDO
REGULATOR
UVLO
POR
TEMP SENSOR
0.6V
Functional Diagram
Dual-Phase, Parallelable, Average Current-Modentrollers
Detailed DescriptionThe MAX5038/MAX5041 (Figures 1 and 2) average cur-
rent-mode PWM controllers drive two out-of-phase
buck converter channels. Average current-mode con-
trol improves current sharing between the channels
while minimizing component derating and size. Parallel
multiple MAX5038/MAX5041 regulators to increase the
output current capacity. For maximum ripple rejection
at the input, set the phase shift between phases to 90°
for two paralleled converters, or 60°for three paralleled
converters. Paralleling the MAX5038/MAX5041s
improves design flexibility in applications requiring
upgrades (higher load).
CLKIN
PLLCMP
PGND
PHASE
DL2
LX2
DH2
DL1
LX1
DH1
VCC
EAOUT
EAN
DIFF
CSP2
CSN2
CSP1
CSN1
MAX5038
C39
VIN = +12V
C1, C2
C25
C26C29
C30C27
C28
SGND
CLP2
CLP1Q2
VIN
VIN
C32
C12
C31
C3–C7R3R2
C13
C8–C11C14,
C15
C16–C24,
C33
LOAD
+1.8V AT 60A
VOUT
SENSE -
SENSE +
BST1
VCC
BST2
NOTE: SEE TABLE 1 FOR COMPONENT VALUES.
VCC
Figure 1. MAX5038 Typical Application Circuit, VIN= +12V
Dual-Phase, Parallelable, Average Current-Mode
Controllers Dual-phase converters with an out-of-phase locking
arrangement reduce the input and output capacitor
ripple current, effectively multiplying the switching fre-
quency by the number of phases. Each phase of the
MAX5038/MAX5041 consists of an inner average cur-
rent loop controlled by a common outer-loop voltage-
error amplifier (VEA) that corrects the output voltage
errors. The MAX5038/MAX5041 utilize a single control-
ling VEA and an average current mode to force the
phase currents to be equal.
CLKIN
PLLCMP
PGND
PHASE
DL2
LX2
DH2
DL1
LX1
DH1
VCC
EAOUT
EAN
DIFF
CSP2
CSN2
CSP1
CSN1
MAX5041
C39
VIN = +12V
C1,
C25
C26C29
C30C27
C28
SGND
CLP2
CLP1Q2
VIN
VIN
C32
C12
C31
C3–C7R3R2
C13
C8–C11C14,
C15
C16–C24,
C33
LOAD
+1.8V AT 60A
VOUT
SENSE -
SENSE +
BST1
VCC
BST2
NOTE: SEE TABLE 1 FOR COMPONENT VALUES.
VCC
Figure 2. MAX5041 Typical Application Circuit, VIN= +12V
Dual-Phase, Parallelable, Average Current-Modentrollers
VINand VCCThe MAX5038/MAX5041 accept a wide input voltage
range of +4.75V to +5.5V or +8V to +28V. All internal
control circuitry operates from an internally regulated
nominal voltage of +5V (VCC). For input voltages of +8V
or greater, the internal VCCregulator steps the voltage
down to +5V. The VCCoutput voltage regulates to +5V
while sourcing up to 80mA. Bypass VCCto SGND with
4.7μF and 0.1μF low-ESR ceramic capacitors for high-
frequency noise rejection and stable operation (Figures 1
and 2).
Calculate power dissipation in the MAX5038/MAX5041
as a product of the input voltage and the total VCCreg-
ulator output current (ICC). ICCincludes quiescent cur-
rent (IQ) and gate drive current (IDD):
PD = VIN x ICC
ICC= IQ+ fSWx (QG1+ QG2 + QG3+ QG4)
where, QG1, QG2, QG3,and QG4are the total gateharge of the low-side and high-side external
MOSFETs, IQis 4mA (typ), and fSWis the switching fre-
quency of each individual phase.
For applications utilizing a +5V input voltage, disable
the VCCregulator by connecting IN and VCCtogether.
Undervoltage Lockout (UVLO)/
Power-On Reset (POR)/Soft-StartThe MAX5038/MAX5041 include an undervoltage lock-
out with hysteresis and a power-on reset circuit for con-
verter turn-on and monotonic rise of the output voltage.
The UVLO threshold is internally set between +4.0V
and +4.5V with a 200mV hysteresis. Hysteresis at
UVLO eliminates “chattering” during startup.
Most of the internal circuitry, including the oscillator,
turns on when the input voltage reaches +4V. The
MAX5038/MAX5041 draw up to 4mA of current before
the input voltage reaches the UVLO threshold.
The compensation network at the current error ampli-
fiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes a parallel combination of
capacitors (C28, C30) and resistors (R5, R6) in series
with other capacitors (C27, C29) (see Figures 1 and 2).
The voltage at CLP_ limits the maximum current avail-
able to charge output capacitors. The capacitor on
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
Internal OscillatorThe internal oscillator generates the 180°out-of-phase
clock signals required by the pulse-width modulation
(PWM) circuits. The oscillator also generates the 2VP-P
voltage ramp signals necessary for the PWM compara-
tors. Connect CLKIN to SGND to set the internal oscillator
frequency to 250kHz or connect CLKIN to VCCto set the
internal oscillator to 500kHz.
CLKIN is a CMOS logic clock input for the phase-
locked loop (PLL). When driven externally, the internal
oscillator locks to the signal at CLKIN. A rising edge at
CLKIN starts the ON cycle of the PWM. Ensure that the
external clock pulse width is at least 200ns. CLKOUT
provides a phase-shifted output with respect to the ris-
ing edge of the signal at CLKIN. PHASE sets the
amount of phase shift at CLKOUT. Connect PHASE to
VCCfor 120°of phase shift, leave PHASE unconnected
for 90°of phase shift, or connect PHASE to SGND for
60°of phase shift with respect to CLKIN.
The MAX5038/MAX5041 require compensation on
PLLCMP even when operating from the internal oscillator.
The device requires an active PLL in order to generate
the proper clock signal required for PWM operation.
Control LoopThe MAX5038/MAX5041 use an average current-mode
control scheme to regulate the output voltage (Figures
3a and 3b). The main control loop consists of an inner
current loop and an outer voltage loop. The inner loop
controls the output currents (IPHASE1and IPHASE2)
while the outer loop controls the output voltage. The
inner current loop absorbs the inductor pole reducing
the order of the outer voltage loop to that of a single-
pole system.
The current loop consists of a current-sense resistor
(RS), a current-sense amplifier (CA_), a current-error
amplifier (CEA_), an oscillator providing the carrier
ramp, and a PWM comparator (CPWM_). The precision
CA_ amplifies the sense voltage across RSby a factor
of 18. The inverting input to the CEA_ senses the CA_
output. The CEA_ output is the difference between the
voltage-error amplifier output (EAOUT) and the gained-
up voltage from the CA_. The RC compensation net-
work connected to CLP1 and CLP2 provides external
frequency compensation for the respective CEA_. The
start of every clock cycle enables the high-side drivers
and initiates a PWM ON cycle. Comparator CPWM_
compares the output voltage from the CEA_ with a 0 to
+2V ramp from the oscillator. The PWM ON cycle termi-
nates when the ramp voltage exceeds the error voltage.
(1)
(2)
