MAX500ACPE+ ,CMOS, Quad, Serial Interface 8-Bit DACMAX50019-1016; Rev 2; 2/96CMOS, Quad, Serial-Interface 8-Bit DAC_______________
MAX500ACWE+ ,CMOS, Quad, Serial Interface 8-Bit DACGeneral Description ________
MAX500AEJE ,CMOS, Quad, Serial-Interface 8-Bit DAC
MAX500AEPE ,CMOS, Quad, Serial-Interface 8-Bit DAC
MAX500AEPE+ ,CMOS, Quad, Serial Interface 8-Bit DACApplicationsMAX500ACPE0°C to +70°C 16 Plastic DIP ±1MAX500BCPE 0°C to +70°C 16 Plastic DIP ±2Minimu ..
MAX500AEWE+ ,CMOS, Quad, Serial Interface 8-Bit DACApplicationsMAX500ACPE0°C to +70°C 16 Plastic DIP ±1MAX500BCPE 0°C to +70°C 16 Plastic DIP ±2Minimu ..
MAX9150EUI+T ,Low-Jitter, 10-Port LVDS RepeaterApplicationsCellular Phone Base StationsMAX9150Add/Drop MuxesDO2+ 1 28 DO3+Digital CrossconnectsDO2 ..
MAX9152ESE ,800Mbps LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switchapplications requiring high speed, low power, and low-2 x 2 Crosspoint Switchnoise signal distribut ..
MAX9152ESE+ ,800Mbps, LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint Switchapplications requiring high speed, low power, and low-2 x 2 Crosspoint Switchnoise signal distribut ..
MAX9152ESE+T ,800Mbps, LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint SwitchApplicationsCell Phone Base StationsMAX9152Add/Drop MuxesEN0EN1Digital CrossconnectsDSLAMsSEL0 SEL1 ..
MAX9152ESE+T ,800Mbps, LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint SwitchELECTRICAL CHARACTERISTICS (continued)(V = +3.0V to +3.6V, NC/RSEL = open for R = 75Ω ±1%, NC/RSEL ..
MAX9152EUE+ ,800Mbps, LVDS/LVPECL-to-LVDS 2 x 2 Crosspoint SwitchELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, NC/RSEL = open for R = 75Ω ±1%, NC/RSEL = high for R ..
MAX500ACPE+-MAX500ACWE+-MAX500AEPE+-MAX500AEWE+-MAX500BCPE+-MAX500BCWE+-MAX500BEWE+
CMOS, Quad, Serial Interface 8-Bit DAC
_______________General DescriptionThe MAX500 is a quad, 8-bit, voltage-output digital-to-
analog converter (DAC) with a cascadable serial inter-
face. The IC includes four output buffer amplifiers and
input logic for an easy-to-use, two- or three-wire serial
interface. In a system with several MAX500s, only one
serial data line is required to load all the DACs by cas-
cading them. The MAX500 contains double-buffered
logic and a 10-bit shift register that allows all four DACs
to be updated simultaneously using one control signal.
There are three reference inputs so the range of two of
the DACs can be independently set while the other two
DACs track each other.
The MAX500 achieves 8-bit performance over the full
operating temperature range without external trimming.
________________________ApplicationsMinimum Component Count Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Arbitrary Function Generators
Automatic Test Equipment
____________________________FeaturesBuffered Voltage OutputsDouble-Buffered Digital InputsMicroprocessor and TTL/CMOS CompatibleRequires No External AdjustmentsTwo- or Three-Wire Cascadable Serial Interface16-Pin DIP/SO Package and 20-Pin LCCOperates from Single or Dual Supplies
______________Ordering Information
MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
_________________Pin Configurations
________________Functional Diagram19-1016; Rev 2; 2/96
*Contact factory for dice specifications.
MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—Dual Supplies(VDD= +11.4V to +16.5V, VSS= -5V ±10%, AGND = DGND = 0V, VREF= +2V to (VDD- 4V), TA= TMINto TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Power Requirements
VDDto AGND...........................................................-0.3V, +17V
VDDto DGND..........................................................-0.3V, +17V
VSSto DGND..................................................-7V, (VDD+ 0.3V)
VDDto VSS...............................................................-0.3V, +24V
Digital Input Voltage to DGND....................-0.3V, (VDD+ 0.3V)
VREFto AGND.............................................-0.3V, (VDD+ 0.3V)
VOUTto AGND (Note 1)...............................-0.3V, (VDD+ 0.3V)
Power Dissipation (TA= +70°C)
Plastic DIP(derate 10.53mW/°C above+70°C)............842mW
Wide SO (derate 9.52mW/°C above +70°C)................762mW
CERDIP (derate 10.00mW/°C above +70°C)...............800mW
LCC (derate 9.09mW/°C above +70°C).......................727mW
Operating Temperature Ranges
MAX500_C_ _....................................................0°C to + 70°C
MAX500_E_ _...................................................-40°C to +85°C
MAX500_M_ _................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
Note 1:The outputs may be shorted to AGND, provided that the power dissipation of the package is not exceeded.
Typical short-circuit current to AGND is 25mA
MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)(VDD= +11.4V to +16.5V, VSS= -5V ±10%, AGND = DGND = 0V, VREF= +2V to (VDD- 4V), TA= TMINto TMAX, unless otherwise noted.)
__________________________________________Typical Operating Characteristics
MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
ELECTRICAL CHARACTERISTICS—Single Supply(VDD= +15V ±5%, VSS= AGND = DGND = 0V, VREF= 10V, TA= TMINto TMAX, unless otherwise noted.)
Note 2:Guaranteed by design. Not production tested.
Note 3:TA= +25°C, VREF= 10kHz, 10V peak-to-peak sine wave.
Note 4:LOADhas a weak internal pull-up resistor to VDD.
Note 5:DAC switched from all 1s to all 0s, and all 0s to all 1s code.
Note 6:Sample tested at +25°C to ensure compliance.
Note 7:Slow rise and fall times are allowed on the digital inputs to facilitate the use of opto-couplers. Only timing for SCL is given
because the other digital inputs should be stable when SCL transitions.
MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
MAX500-01
VOUT (V)
ISINK
(mA)10
SUPPLY CURRENT
vs. TEMPERATURE
MAX500-02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
ZERO-CODE ERROR
vs. TEMPERATUREMAX500-03
TEMPERATURE (°C)
ZERO-CODE ERROR (mV)
____________________________Typical Operating Characteristics (continued)
_______________Detailed Description
The MAX500 has four matched voltage-output digital-to-
analog converters (DACs). The DACs are “inverted”
R-2R ladder networks which convert 8 digital bits into
equivalent analog output voltages in proportion to the
applied reference voltage(s). Two DACs in the MAX500
have a separate reference input while the other two
DACs share one reference input. A simplified circuit
diagram of one of the four DACs is provided in Figure 1.
VREFInputThe voltage at the VREFpins (pins 4, 12, and 13) sets
the full-scale output of the DAC. The input impedance
of the VREFinputs is code dependent. The lowest
value, approximately 11kΩ(5.5kΩfor VREFA/B), occurs
when the input code is 01010101. The maximum value
of infinity occurs when the input code is 00000000.
Because the input resistance at VREFis code depen-
dent, the DAC’s reference sources should have an out-
put impedance of no more than 20Ω(no more than
10Ωfor VREFA/B). The input capacitance at VREFis
also code dependent and typically varies from 15pF to
35pF (30pF to 70pF for VREFA/B). VOUTA, VOUTB,
VOUTC, and VOUTD can be represented by a digitally
programmable voltage source as:
VOUT= Nbx VREF/ 256
where Nbis the numeric value of the DAC’s binary
input code.
Output Buffer AmplifiersAll voltage outputs are internally buffered by precision
unity-gain followers, which slew at greater than 3V/µs.
When driving 2kΩin parallel with 100pF with a full-scale
transition (0V to +10V or +10V to 0V), the output settles
to ±1/2LSB in less than 4µs. The buffers will also drive
2kΩin parallel with 500pF to 10V levels without oscilla-
tion. Typical dynamic response and settling perfor-
mance of the MAX500 is shown in Figures 2 and 3.
A simplified circuit diagram of an output buffer is
shown in Figure 4. Input common-mode range to
AGND is provided by a PMOS input structure. The out-
put circuitry incorporates a pull-down circuit to actively
drive VOUTto within +15mV of the negative supply
(VSS). The buffer circuitry allows each DAC output to
MAX500sink, as well as source up to 5mA. This is especially
important in single-supply applications, where VSSis
connected to AGND, so that the zero error is kept at or
under 1/2LSB (VREF= +10V). A plot of the Output Sink
Current vs. Output Voltage is shown in the Typical
Operating Characteristicssection.
Digital Inputs
and Interface LogicThe digital inputs are compatible with both TTL and 5V
CMOS logic; however, the power-supply current (IDD)
is somewhat dependent on the input logic level. Supply
current is specified for TTL input levels (worst case) but
is reduced (by about 150µA) when the logic inputs are
driven near DGND or 4V above DGND.
Do not drive the digital inputs directly from CMOS logic
running from a power supply exceeding 5V. When driv-
ing SCL through an opto-isolator, use a Schmitt trigger
to ensure fast SCL rise and fall times.
The MAX500 allows the user to choose between a
3-wire serial interface and a 2-wire serial interface.
The choice between the 2-wire and the 3-wire inter-
face is set by the LOADsignal. If the LOADis allowed
to float (it has a weak internal pull-up resistor to VDD),
the 2-wire interface is selected. If the LOADsignal is
kept to a TTL-logic high level, the 3-wire interface
is selected.
3-Wire InterfaceThe 3-wire interface uses the classic Serial Data (SDA),
Serial Clock (SCL), and LOADsignals that are used
in standard shift registers. The data is clocked in on
the falling edge of SCL until all 10 bits (8 data bits and
2 address bits) are entered into the shift register.
CMOS, Quad, Serial-Interface
8-Bit DACFigure 2. Positive and Negative Settling Times
Figure 3. Dynamic Response
Figure 4. Simplified Output Buffer Circuit
