MAX4820EUP+ ,+3.3V/+5V, 8-Channel, Cascadable Relay Drivers with Serial/Parallel InterfaceELECTRICAL CHARACTERISTICS(V = +3V to +5.5V, V = V , T = -40°C to +85°C, unless otherwise noted. Ty ..
MAX4820EUP+T ,+3.3V/+5V, 8-Channel, Cascadable Relay Drivers with Serial/Parallel InterfaceApplications*EP = Exposed pad.Central OfficePin ConfigurationsATETOP VIEWDSL, ADSL Line CardsIndust ..
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MAX8878EZK28-TG50 ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX8878EZK30+T ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX8878EZK30-T ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX8878EZK32+T ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX8878EZK32-T ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX8878EZK33+T ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX4820EUP+-MAX4820EUP+T
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers with Serial/Parallel Interface
AVAILABLE
General DescriptionThe MAX4820/MAX4821 8-channel relay drivers offer
built-in kickback protection and drive +3.3V/+5V non-
latching or dual-coil-latching relays. These devices are
especially useful when driving +3V relays. Each inde-
pendent open-drain output features a 2Ωon-resistance
and is guaranteed to sink 70mA (min) of load current.
Both devices consume less than 50µA (max) quiescent
current and have 1µA output off-leakage current.
The MAX4820 features an SPI™-/QSPI™-/MICROWIRE™-
compatible serial interface. Input data is shifted into an 8-
bit shift register and latched to the outputs when CS
transitions from low to high. Each data bit in the shift reg-
ister corresponds to a specific output, allowing indepen-
dent control of all outputs.
The MAX4821 features a 4-bit (A0, A1, A2, LVL) paral-
lel-input interface. The first three bits (A0, A1, A2) deter-
mine the output address, and the fourth bit (LVL)
determines whether the selected output is switched on
or off. Data is latched to the outputs when CStransi-
tions from low to high.
Both devices feature separate set and reset functions
that allow the user to turn on or turn off all outputs simul-
taneously with a single control line. Built-in hysteresis
(Schmidt trigger) on all digital inputs allows this device
to be used with slow rising and falling signals, such as
those from optocouplers or RC power-up initialization
circuits. The MAX4820/MAX4821 are available in 20-pin
TSSOP and space-saving 20-pin Thin QFN packages.
ApplicationsCentral Office
ATE
DSL, ADSL Line Cards
Industrial Equipment
E1/T1 Redundancy
Features8 Independent Output ChannelsBuilt-In Inductive Kickback ProtectionDrive +3V and +5V RelaysGuaranteed 70mA (min) Coil Drive CurrentSET
Function to Turn On All Outputs
SimultaneouslyRESET
Function to Turn Off All Outputs
SimultaneouslySPI-/QSPI-/MICROWIRE-Compatible Serial
Interface (MAX4820)Serial Digital Output for Daisy Chaining
(MAX4820)Parallel Interface (MAX4821)Low 50µA (max) Quiescent Supply CurrentSpace-Saving 20-Pin Thin QFN PackageTOP VIEW
*CONNECT EP TO GND.
*EP191817
SETV
OUT1OUT2
PGND
OUT5
COM
OUT4
OUT3
OUT6
SCLK
DINDOUT789
N.C.
GND
OUT8OUT7
PGND
MAX4820
THIN QFNRESET
Pin Configurations+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configurations continued at end of data sheet.
Typical Application Circuits and Functional Diagrams
appear at end of data sheet.SPI and QSPI are trademarks of Motorola, Inc.
PARTTEMP RANGEPIN-PACKAGE
MAX4820ETP+-40°C to +85°C 20 Thin QFN-EP*
MAX4820EUP+ -40°C to +85°C 20 TSSOP-EP*
MAX4821ETP+-40°C to +85°C 20 Thin QFN-EP*
MAX4821EUP+ -40°C to +85°C 20 TSSOP-EP*
MAX4820/MAX4821
Ordering Information
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= +3V to +5.5V, VCOM= VCC, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
VCC, COM..............................................................-0.3V to +6.0V
OUT_........................................................-0.3V to (VCOM + 0.3V)
CS, SCLK, DIN, SET, RESET, A0, A1, A2, LVL......-0.3V to +6.0V
DOUT..........................................................-0.3V to (VCC + 0.3V)
Continuous OUT_ Current (all outputs turned on)............150mA
Continuous OUT_ Current (single output turned on)........300mA
Continuous Power Dissipation (TA= +70°C)
20-Lead Thin QFN (derate 16.9mW/°C above +70°C)..1350mW
θJA(Note 1)...............................................................59.3°C/W
20-Pin TSSOP (derate 21.7mW/°C above +70°C).....1739mW
θJA(Note 1)..................................................................46°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Soldering Temperature (10s)...........................................+300°C
Reflow Temperature.........................................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOperating VoltageVCC2.35.5V
VCC = 3.6V1550Quiescent CurrentIQIOUT_ = 0µA,
logic inputs = 0V or VCCVCC = 5.5V2070µA
Thermal Shutdown160°C
Power-On Reset0.81.52.2V
Power-On Reset Hysteresis140mV
DIGITAL INPUTS (SCLK, DIN, CS, LVL, A0, A1, A2, RESET, SET)VCC = 3.3V2.0Input Logic-High VoltageVIHVCC = 5V2.4V
VCC = 3.3V0.6Input Logic-Low VoltageVILVCC = 5V0.8V
Input Logic HysteresisVHYST150mV
Input Leakage CurrentsILEAKInput voltages = 0V or 5.5V-1.00.01+1.0µA
CIN Input CapacitanceCIN5pF
DIGITAL OUTPUT (DOUT)DOUT Low VoltageVOLISINK = 6mA0.4V
DOUT High VoltageVOHISOURCE = 0.5mAVCC - 0.5V
RELAY OUTPUT DRIVERS (OUT1–OUT8)VCC = 2.7V70OUT_ Drive CurrentVCC = 4.5V70mA
OUT_ On-ResistanceRONVCC = 2.7V26Ω
OUT_ VoltageVOUT_VCC = 3.0V, IOUT_ = 70mA0.4V
IOUT Off-Leakage CurrentILEAKVOUT_ = VCC, all outputs off-1+1µA
Kickback Diode Forward VoltageVFORWIOUT_ = 150mA (Note 3)1.5V
Note 1:Package thermal resistances were obtained using the method described in JEDEC specifications. For detailed information on
package thermal considerations, refer to /thermal-tutorial.
MAX4820/MAX4821
3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SPI TIMING (MAX4820)Turn-On Time (OUT_)tONFrom rising edge of CS, RL = 50Ω,
CL = 50pF1.0µs
Turn-Off Time (OUT_)tOFFFrom rising edge of CS, RL = 50Ω,
CL = 50pF1.0µs
SCLK FrequencyfSCLK02.1MHz
Cycle TimetCH + tCL480ns
CS Fall to SCLK Rise SetuptCSS240ns
CS Rise to SCLK HoldtCSH240ns
SCLK High TimetCH190ns
SCLK Low TimetCL190ns
Data Setup TimetDS100ns
Data Hold TimetDH0ns
SCLK Fall to DOUT ValidtDO50% of SCLK to 10% of DOUT,
CL = 50pF85120ns
Rise Time (DIN, SCLK, CS, SET,
RESET)tSCR20% of VCC to 70% of VCC, CL = 50pF2µs
Fall Time (DIN, SCLK, CS,
RESET, SET)tSCF20% of VCC to 70% of VCC, CL = 50pF2µs
RESET Min Pulse WidthtRW70ns
SET Min Pulse WidthtSW70ns
PARALLEL TIMING (MAX4821)Turn-On TimetONFrom rising edge of CS, RL = 50Ω,
CL = 50pF1µs
Turn-Off TimetOFFFrom rising edge of CS, RL = 50Ω,
CL = 50pF1µs
LVL Setup TimetLS100ns
LVL Hold TimetLH0ns
Address to CS Setup TimetAH100ns
Address to CS Hold TimetAS0ns
Rise Time (A2, A1, A0, LVL)tSCR20% of VCC to 70% of VCC, CL = 50pF2µs
Fall Time (A2, A1, A0, LVL)tSCF20% of VCC to 70% of VCC, CL = 50pF2µs
RESET Pulse WidthtRW70ns
SET Pulse WidthtSW70ns
ELECTRICAL CHARACTERISTICS (continued)(VCC= +3V to +5.5V, VCOM= VCC, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Note 2:Specifications at -40°C are guaranteed by design and not production tested.
Note 3:After relay turn-off, inductive kickback may momentarily cause the voltage at OUT_ to exceed VCOM. This is considered part
of normal operation and will not damage the device.
MAX4820/MAX4821
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
Typical Operating Characteristics(VCOM= VCC, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGEMAX4820 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
ALL LOGIC INPUTS = 0
SUPPLY CURRENT
vs. TEMPERATUREMAX4820 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (3510-15
VCC = 5VVCC = 5.5V
VCC = 2.3V
VCC = 3.3V
SUPPLY CURRENT
vs. INPUT LOGIC VOLTAGEINPUT LOGIC VOLTAGE (V)
SUPPLY CURRENT (321
VCC = 3.3V
VCC = 5V
ALL LOGIC INPUTS
CONNECTED
ON-RESISTANCE
vs. SUPPLY VOLTAGEMAX4820 toc04
SUPPLY VOLTAGE (V)
IOUT_SINK = 70mA
ON-RESISTANCE
vs. TEMPERATUREMAX4820 toc05
TEMPERATURE (°C)3510-15
VCC = 3.3VVCC = 2.3V
VCC = 5.5V
VCC = 5V
IOUT_SINK = 70mA
POWER-ON RESET VOLTAGE
vs. TEMPERATUREMAX4820 toc06
TEMPERATURE (°C)
POWER-ON RESET VOLTAGE (V)35-1510
OUTPUT OFF-LEAKAGE CURRENT
vs. SUPPLY VOLTAGE
MAX4820 toc07
SUPPLY VOLTAGE (V)
OUTPUT OFF-LEAKAGE (nA)
OUTPUT OFF-LEAKAGE CURRENT
vs. TEMPERATURE
MAX4820 toc08
TEMPERATURE (°C)
OUTPUT OFF-LEAKAGE (nA)35-1510
VCC = 5.5V
VCC = 5V
VCC = 2.3V
VCC = 3.3V
OUT_ TURN-ON/TURN-OFF DELAY TIMES
vs. SUPPLY VOLTAGEMAX4820 toc09
SUPPLY VOLTAGE (V)
tON
OFF
DELAY TIME (ns)
RL = 50Ω
CL = 50pF
tON
tOFF
MAX4820/MAX4821
3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
INPUT LOGIC THRESHOLD
vs. SUPPLY VOLTAGEMAX4820 toc10
SUPPLY VOLTAGE (V)
INPUT LOGIC THRESHOLD (V)
PIN
MAX4820MAX4821
THIN
QFNTSSOPTHIN
QFNTSSOP
NAMEFUNCTION13RESET
Reset Input. Drive RESET low to clear all latches and registers (all outputs
are turned off). RESET overrides all other inputs. If RESET and SET are pulled
low at the same time, then RESET takes precedence.24CS
Chip-Select Input.
MAX4820: Drive CS low to select the device. When CS is low, data at DIN isclocked into the 8-bit shift register on SCLK’s rising edge. Drive CS from low
to high to latch the data to the registers and activate the appropriate relays.
MAX4821: Drive CS low to select the device and set level on LVL. Drive CSfrom low to high to latch the address and level data to the output.5——DINSerial-Data Input6——SCLKSerial-Clock Input7——DOUT
Serial-Data Output. DOUT is the output of the 8-bit shift register. This output
can be used to daisy chain multiple MAX4820s. The data at DOUT appears
synchronous to SCLK’s falling edge.8——N.C.No Connection979GNDGround10810OUT8Open-Drain Output 8. Connect OUT8 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.11911OUT7Open-Drain Output 7. Connect OUT7 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.
10, 1612, 1810, 1612, 18PGNDPower Ground. PGND is a return for the output sinks. Connect PGND pins
together and to GND.131113OUT6Open-Drain Output 6. Connect OUT6 to the low side of a relay coil. This
Typical Operating Characteristics (continued)(VCOM= VCC, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
BACK EMF CLAMPING
WITH STANDARD 3V RELAYMAX4820 toc11
200μs/div
VCS
5V/div0
OUT_
1V/div
OUT_ TURNS OFF
VCC = 3.3V
Pin DescriptionMAX4820/MAX4821
+3.3V/+5V, 8-Channel, Cascadable Relay Drivers
with Serial/Parallel Interface
Detailed DescriptionThe MAX4820/MAX4821 8-channel relay drivers offer
built-in kickback protection and drive +3.3V/+5V non-
latching or dual-coil-latching relays. These devices are
especially useful when driving +3V relays. Each inde-
pendent open-drain output features a 2Ωon-resistance
and is guaranteed to sink 70mA (min) load current. Both
devices consume less than 50µA (max) quiescent cur-
rent and feature 1µA (min) output off-leakage current.
The MAX4820 features an SPI/QSPI/MICROWIRE-com-
patible serial interface. Input data is shifted into an 8-bit
shift register and latched to the outputs when CStransi-
tions from low to high. Each data bit in the shift register
corresponds to a specific output, allowing independent
The MAX4821 features a 4-bit (A0, A1, A2, LVL) parallel
input interface. The three bits (A0, A1, A2) determine
the output address, and LVL determines whether the
selected output is switched on or off. Data is latched to
the outputs when CStransitions from low to high.
Both devices feature separate set and reset functions
that allow the user to turn on or turn off all outputs
simultaneously with a single control line. Built-in hys-
teresis (Schmidt trigger) on all digital inputs allows this
device to be used with slow rising and falling signals,
such as those from optocouplers or RC power-up ini-
tialization circuits. The MAX4820/MAX4821 are avail-
able in 20-pin TSSOP and space-saving 20-pin Thin
QFN packages.
PIN
MAX4820MAX4821
THIN
QFNTSSOPTHIN
QFNTSSOP
NAMEFUNCTION141214OUT5Open-Drain Output 5. Connect OUT5 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.151315COM
Common Free-Wheeling Diodes. Connect COM to VCC. COM can also be
connected to a separate supply that is higher than VCC. In that case, bypass
VCC to GND with a 0.1µF capacitor.161416OUT4Open-Drain Output 4. Connect OUT4 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.171517OUT3Open-Drain Output 3. Connect OUT3 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.191719OUT2Open-Drain Output 2. Connect OUT2 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.201820OUT1Open-Drain Output 1. Connect OUT1 to the low side of a relay coil. This
output is pulled to PGND when activated, but otherwise is high impedance.1191VCCInput Supply Voltage. Bypass VCC to GND with a 0.1µF capacitor.2202SET
Set Input. Drive SET low to set all latches and registers high (all outputs are
turned on). SET overrides all parallel and serial control inputs. RESET
overrides SET under all conditions.—35LVL
Level Input. LVL determines whether the selected address is switched on or
off. A logic high on LVL switches on the addressed output. A logic low on
LVL switches off the addressed output.—46A0Digital Address “0” Input. (See Table 2 for address mapping.)—57A1Digital Address “1” Input. (See Table 2 for address mapping.)—68A2Digital Address “2” Input. (See Table 2 for address mapping.)———EPExposed Pad. Connect exposed pad to GND.
Pin Description (continued)MAX4820/MAX4821