MAX4810CTN+ ,Dual, Unipolar/Bipolar, High-Voltage Digital PulsersApplications GC2C 47 24 INP2DC2Ultrasound Medical Flaw DetectionV 23 EN248EE2ImagingPiezoelectric D ..
MAX481CPA ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversApplicationsIndustrial-Control Local Area Networks Ordering Information appears at end of data shee ..
MAX481CPA ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversApplicationsguarantees a logic-high output if the input is open circuit.MAX3030E–MAX3033E: ±15kV E ..
MAX481CPA ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversApplicationsMAX3483E/MAX3485E/MAX3486E/MAX3488E/Low-Power RS-485 TransceiversMAX3490E/MAX3491E: +3. ..
MAX481CPA+ ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversELECTRICAL CHARACTERISTICS(V = 5V ±5%, T = T to T , unless otherwise noted.) (Notes 1, 2)CC A MIN M ..
MAX481CPA+ ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversApplicationsIndustrial-Control Local Area Networks Ordering Information appears at end of data shee ..
MAX8878EUK25+T ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX8878EUK28 ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX8878EUK28 ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX8878EUK29 ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX8878EUK29+T ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX8878EUK29-T ,Low-Noise, Low-Dropout, 150mA Linear Regulators with '2982 Pinout
MAX4810CTN+
Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers
General DescriptionThe MAX4810/MAX4811/MAX4812 integrated circuits
generate high-voltage, high-frequency, unipolar or bipo-
lar pulses from low-voltage logic inputs. These dual
pulsers feature independent logic inputs, independent
high-voltage pulser outputs with active clamps and
independent high-voltage supply inputs.
The MAX4810/MAX4811/MAX4812 feature a 9Ωoutput
impedance for the high-voltage outputs, and a 27Ω
impedance for the active clamp. The high-voltage out-
puts are guaranteed to provide 1.3A output current.
All devices use three logic inputs per channel to control
the positive and negative pulses and active clamp. Also
included are two independent enable inputs. Disabling
EN ensures the output MOSFETs are not accidentally
turned on during fast power-supply ramping. This allows
for faster ramp times and smaller delays between puls-
ing modes. A low-power shutdown mode reduces
power consumption to less than 1µA. All digital inputs
are CMOS compatible.
The MAX4810 includes clamp output overvoltage pro-
tection, while the MAX4811 features both pulser output
and clamp output overvoltage protection. The MAX4812
does not provide overvoltage protection. See the
Ordering Information/Selector Guide.
The MAX4810/MAX4811/MAX4812 are available in a
56-pin (7mm x 7mm), TQFN exposed-pad package and
are specified over the 0°C to +70°C commercial tem-
perature range.
FeaturesHighly Integrated, High-Voltage, High-Frequency
Unipolar/Bipolar Pulser9ΩOutput Impedance and 1.3A (min) Output
Current27ΩActive ClampPulser and Clamp Overvoltage Protection
(MAX4810/MAX4811)0 to +220V Unipolar or ±110V Bipolar OutputsMatched Rise/Fall Times and Matched
Propagation DelaysCMOS-Compatible Logic Inputs56-Pin, 7mm x 7mm, TQFN Package
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers19-4138; Rev 0; 10/08
EVALUATION KIT
AVAILABLE
Pin ConfigurationTOP VIEW
MAX4810
MAX4811
MAX4812
TQFN7mm x 7mmGND
VCC1
INN1
INC1
INP1
EN1
AGND
EN2
INP2
INC2
INN2
VCC2
GND
CDP1
GND
VCC1
CGC1
CDC1
VEE1
VSS
VDD
VEE2
CDC2
CGC2
VCC2
GND
CDP223456789101112131441403938373635343332313029
NN1
GN1
DN1
NN1
N.C.ON1
OCN1
GND
OCP1
OP1N.C.
PP1
PP1
GP1
NN2
GN2
DN2
NN2
N.C.ON2OCN2GNDOCP2OP2N.C.V
PP2
PP2
GP2
*EP = EXPOSED PAD, CONNECT EP TO VSS.
*EP
+SHDN
Ordering Information/
Selector Guide
Note:All devices are specified over the 0°C to +70°C operating
temperature range.
+Denotes a lead-free/RoHS-compliant package.
*Future product—contact factory for availability.
**EP = Exposed pad.
PARTPROTECTED
OUTPUTS
OUTPUT
CURRENT
(A)
PIN-
PACKAGE
MAX4810CTN+OCP_, OCN_1.356 TQFN-EP**
MAX4811CTN+OCP_, OCN_,
OP_, ON_1.356 TQFN-EP**
MAX4812CTN+*None1.356 TQFN-EP**
Ultrasound Medical
Imaging
Cleaning Equipment
Flaw Detection
Piezoelectric Drivers
Test Instruments
Applications
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +6V, VCC_= +4.75V to +12.6V, VEE_= -12.6V to -4.75V, VNN_= -200V to 0, VPP_= 0 to (VNN_+ 200V), VSS≤the lower of
VNN1or VNN2, TA= TJ= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 3) (See Figures 8, 9, and 10.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(Voltages referenced to GND.)
VDD Logic Supply Voltage........................................-0.3V to +6V
VCC_Output Driver Positive Supply Voltage..........-0.3V to +15V
VEE_Output Driver Negative Supply Voltage.........-15V to +0.3V
VPP_ High Positive Supply Voltage.......................-0.3V to +230V
VNN_High Negative Supply Voltage....................-230V to +0.3V
VSSVoltage................................................(VPP_- 250V) to VNN_
VPP1- VNN1, VPP2- VNN2 Supply Voltage............-0.6V to +250V
INP_, INN_, INC_, EN_, SHDNLogic Input...-0.3V to VDD + 0.3V
OP_,OCP_, OLN_, ON_..............(-0.3V + VNN_) to (-0.3V to VPP_)
CGN_Voltage............................(-0.3V + VNN_) to (+15V + VNN_)
CGP_Voltage.............................(+0.3V + VPP_) to (-15V + VPP_)
CGC_Voltage...........................................................-15V to +15V
CDC_,CDP_, CDN_ Voltage......................................-0.3V to VCC_
Peak Current per Output Channel........................................3.0A
Continuous Power Dissipation (TA= +70°C) (Note 1)
56-Pin TQFN (derate 40mW/°C above +70°C)..........3200mW
Thermal Resistance (Note 2)
θJA................................................................................25°C/W
θJC...............................................................................0.8°C/W
Operating Temperature Range...............................0°C to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLY (VDD, VCC_, VEE_, VPP_, VNN_)Logic Supply VoltageVDD+2.7+3+6V
Positive Drive Supply VoltageVCC_+4.75+12+12.6V
Negative Drive Supply VoltageVEE_-12.6-12-4.75V
High-Side Supply VoltageVPP_0VNN_ +
220V
Low-Side Supply VoltageVNN_-2000V
VPP_ - VNN_ Supply Voltage0+220V
SUPPLY CURRENT (Single Channel)VINN_/VINP_ = 0 , VSHDN = 01
VDD Supply CurrentIDDVEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD,
VINN_ = VINP_, f = 5MHz100200µA
VSHDN = 0, CH1 and CH21
VEN_ = VDD, VSHDN = VDD, CH1 and CH2130200µA
VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD,
VINN_ = VINP_, f = 5MHz, VCC_ = 5V, VDD = 3V,
only one channel switchingVCC_ Supply CurrentICC_
VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD,
VINN_ = VINP_, f = 5MHz, VCC_ = 12V, VDD = 3V,
only one channel switching
Note 1:This specification is based on the thermal characteristic of the package, the maximum junction temperature, and the setup
described by JEDEC 51. The maximum power dissipation for the MAX4810/MAX4811/MAX4812 might be limited by the thermal
protection included in the device.
Note 2:Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to /thermal-tutorial.
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +6V, VCC_= +4.75V to +12.6V, VEE_= -12.6V to -4.75V, VNN_= -200V to 0, VPP_= 0 to (VNN_+ 200V), VSS≤the lower of
VNN1or VNN2, TA= TJ= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 3) (See Figures 8, 9, and 10.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVSHDN = 0, CH1 and CH225
VEN_ = VDD, VSHDN = VDD, CH1 and CH21
VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD,
VINN_ = VINP_, f = 5MHz, VEE_ = -5V,
only one channel switching
200VEE_ Supply CurrentIEE_
VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD,
VINN_ = VINP_, f = 5MHz, VEE_ = -12V,
only one channel switching
VSHDN = 0, CH1 and CH21
VEN_ = VDD, VSHDN = VDD, CH1 and CH290160µAE N _ = V D D , V SHDN = V D D , V I N C _ = 0 or V D D ,I N N _ = VI NP_, f = 5M H z, V P P _ = + 5V , V N N _ = - 5V ,
no l oad , onl y one channel sw i tchi ng
VPP_ Supply CurrentIPP_
VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD,
VPP_ = +80V, VNN_ = -80V, pulse repetition
frequency = 10kHz, f = 10MHz, 4 periods,
no load, only one channel switching
VSHDN = 0, CH1 and CH21
VEN_ = VDD, VSHDN = VDD, CH1 and CH24080µAE N _ = V D D , V SHDN = V D D , V I N C _ = 0 or V D D ,I N N _ = VI NP_, f = 5M H z, V N N _ = - 5V , V P P _ = + 5V ,
no l oad , onl y one channel sw i tchi ng
VNN_ Supply CurrentINN_
VEN_ = VDD, VSHDN = VDD, VINC_ = 0 or VDD,
VPP_ = +80V, VNN_ = -80V, pulse repetition
frequency = 10kHz, f = 10MHz, 4 periods,
no load, only one channel switching
LOGIC INPUTS (EN_, SHDN, INN_, INP_, INC_)
Low-Level Input VoltageVIL0.25 x
VDDV
High-Level Input VoltageVIH0.75 x
VDDV
Logic-Input CapacitanceCIN5pF
Logic-Input LeakageIINVIN = 0 or VDD±1µA
OUTPUT (OUT_)No load at OUT_VNN_VPP_
Unprotected outputs (see the Ordering
Information/Selector Guide), 100mA load
VNN_ +
VPP_ -
1.5OUT_ Output-Voltage RangeVOUT_
Protected outputs (see the Ordering
Information/Selector Guide), 100mA load
VNN_ +
VPP_ -
IOP _ = - 100m A, V C C _ = + 12V ± 5%, D C - coup l ed 917Low-Side Small-Signal Output
ImpedanceROLSIOP _ = - 100m A, V C C _ = + 5V ± 5%, D C - coup l ed 9.518Ω
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +6V, VCC_= +4.75V to +12.6V, VEE_= -12.6V to -4.75V, VNN_= -200V to 0, VPP_= 0 to (VNN_+ 200V), VSS≤the lower of
VNN1or VNN2, TA= TJ= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 3) (See Figures 8, 9, and 10.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSIOP _ = - 100m A, V C C _ = + 12V ± 5%, D C - coup l ed 10.517High-Side Small-Signal Output
ImpedanceROHSIOP _ = - 100m A, V C C _ = + 5V ± 5%, D C - coup l ed 1218Ω
Low-Side Output CurrentIOLVCC_ = +12V ±5%, VOUT_ - VNN_ = 100V1.3A
High-Side Output CurrentIOHVCC_ = +12V ±5%, VOUT_ - VPP_ = 100V1.3A
MAX481045
Off-Output CapacitanceCO(OFF)
OP_, ON_, OCP_ and OCN_
connected together,
VPP_ = +100V, VNN_ = -100VMAX481175
Off-Output Leakage CurrentILKVNN_ = -100V, VPP_ = 100V, EN_ = 0,
OUT = -100V to +100V-1+1µA
IOC N _ = - 100m A, D C - coup l ed , V C C _ = + 12V ± 5% ,E E _ = - V C C _ 2250
Low-Side Signal-Clamp Output
ImpedanceRCLS
IOCN_ = -100mA, DC-coupled, VCC_ = +5V ±5%,
VEE_ = -VCC_2465
IOC P _ = - 100m A, D C - coup l ed , V C C _ = + 12V ± 5% ,E E _ = - V C C _ 2850
High-Side Signal-Clamp Output
ImpedanceRCHS
IOCP_ = -100mA, DC-coupled, VCC_ = +5V ±5%,
VEE_ = -VCC_3865
VCC_ = +12V ±5%, VEE_ = -VCC_, ICGN = 10mA,
EN_ = 0100Ω
Low-Side Gate Short
ImpedanceRLSH
VCC_ = +12V ±5%, VEE_ = -VCC_, ICGN = 10mA,
EN_ = VDD57.510kΩ
VCC_ = +12V ±5%, VEE_ = -VCC_, ICGN = 10mA,
EN_ = 0100Ω
High-Side Gate Short
ImpedanceRHSH
VCC_ = +12V ±5%, VEE_ = -VCC_, ICGN = 10mA,
EN_ = VDD57.510kΩ
THERMAL SHUTDOWNThermal ShutdownTSHDNJunction temperature rising150°C
Thermal-Shutdown Hysteresis20°C
DYNAMIC CHARACTERISTICS (RL = 100Ω, CL = 100pF, unless otherwise noted)Logic Input to Output Rise
Propagation DelaytPLHVCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 415ns
Logic Input to Output Fall
Propagation DelaytPHLVCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 415ns
Logic Input to Output Rise
Propagation DelaytPOHVCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 415ns
Logic Input to Output Fall
Propagation DelaytPOLVCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 415ns
Logic Input to Output-Rise
Propagation Delay ClamptPLOVCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 415ns
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +6V, VCC_= +4.75V to +12.6V, VEE_= -12.6V to -4.75V, VNN_= -200V to 0, VPP_= 0 to (VNN_+ 200V), VSS≤the lower of
VNN1or VNN2, TA= TJ= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 3) (See Figures 8, 9, and 10.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSLogic Input to Output-Fall
Propagation Delay ClamptPHOVCC_ = +12V, VPP_ = +5V, VNN_ = -5V, Figure 415ns
OUT_ Rise Time (GND to VPP_)tR0PV P P _ = + 100V , V N N _ = - 100V , V C C _ = + 12V ± 5%,E E _ = - V C C _ , Fi g ur e 4920ns
OUT_ Rise Time (VNN_ to GND)tRN0V P P _ = + 100V , V N N _ = - 100V , V C C _ = + 12V ± 5%,E E _ = - V C C _ , Fi g ur e 41735ns
OUT_ Rise Time (VNN_ to VPP_)tRNPV P P _ = + 100V , V N N _ = - 100V , V C C _ = + 12V ± 5%,E E _ = - V C C _ , Fi g ur e 410.535ns
OUT_ Fall Time (GND to VNN_)tF0NV P P _ = + 100V , V N N _ = - 100V , V C C _ = + 12V ± 5%,E E _ = - V C C _ , Fi g ur e 4920ns
OUT_ Fall Time (VPP_ to GND)tFP0V P P _ = + 100V , V N N _ = - 100V , V C C _ = + 12V ± 5%,E E _ = - V C C _ , Fi g ur e 41735ns
OUT_ Fall Time (VPP_ to VNN_)tFPNV P P _ = + 100V , V N N _ = - 100V , V C C _ = + 12V ± 5%,E E _ = - V C C _ , Fi g ur e 410.535ns
VCC_ = +12V ± 5%, VEE_ = -VCC_100OUT Enable Time from EN
(Figure 5)tENVCC_ = +5V ± 5%, VEE_ = -VCC_150ns
VCC_ = +12V ± 5%, VEE_ = -VCC_100OUT Disable Time from EN
(Figure 5)tDIVCC_ = +5V ± 5%, VEE_ = -VCC_150ns
VCC_ = +12V ± 5%, VEE_ = -VCC_150Clamp Enable Time from INC
(Figure 6)tEN-CLVCC_ = +5V ± 5%, VEE_ = -VCC_180ns
VCC_ = +12V ± 5%, VEE_ = -VCC_150Clamp Disable Time from INC
(Figure 6)tDI-CLVCC_ = +5V ± 5%, VEE_ = -VCC_150ns
VPP_ = 12V, VNN_ = 0, VCC_ = +12V ± 5%,
VEE_ = -VCC_1000Short Enable Time from EN
(Figure 7)tEN_SHVPP_ = 5V, VNN_ = 0, VCC_ = +5V ± 5%,
VEE_ = -VCC_1000
VPP_ = 12V, VNN_ = 0, VCC_ = +12V ± 5%,
VEE_ = -VCC_250Short Disable Time from EN
(Figure 7)tDI_SH
VPP_ = 5V, VNN_ = 0, VCC_ = +5V ± 5%,
VEE_ = -VCC_250
IN P _ to IN N _ Over l ap Tol er ance|3|ns
CrosstalkVPP_ = VCC_ = +5V, VNN_ = VEE_ = -5V,
f = 5MHz69dB
2nd Harmonic Distortion2HDVPP_ = VNN_ = 100V, fOUT = 5MHz, VCC_ = 12V-48dB
RMS Output JittertJVCC_ = 12V9ps
Note 3:Specifications are guaranteed for the stated global conditions, unless otherwise noted and are 100% production tested at= +25°C and TA= +70°C. Specifications at TA= 0°C are guaranteed by design.
Note 4:100% production tested at TA= +25°C. Specifications over temperature are guaranteed by design.
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
Typical Operating Characteristics(VDD= +3.3V, VCC_ = +12V, VEE_ = -12V, VSS= -100V, VPP_ = +100V, VNN_ = -100V, fOUT= 5MHz, TA= +25°C, unless otherwise noted.)
ICC vs. OUTPUT FREQUENCY
MAX4810/11/12 toc01
FREQUENCY (MHz)
ICC
(mA)
4 PULSES, PRF = 10kHz523678910
ICC vs. OUTPUT FREQUENCYMAX4810/11/12 toc02
FREQUENCY (MHz)
ICC
(mA)
CONTINUOUS SWITCHING,
VPP_ = VCC_ = +5V,
VNN_ = VEE_ = -5V,
VDD = +3.3V, NO LOAD
ICC vs. TEMPERATURE
MAX4810/11/12 toc03
TEMPERATURE (°C)
ICC
4 PULSES AT 10MHz, PRF = 10kHz
ICC vs. TEMPERATURE
MAX4810/11/12 toc04
TEMPERATURE (°C)
ICC
(mA)
CONTINUOUS SWITCHING,
fOUT = 2.5MHz,
VPP_ = VCC_ = +5V,
VNN_ = VEE_ = -5V,
VDD = +3.3V, NO LOAD
IPP vs. OUTPUT FREQUENCY
MAX4810/11/12 toc05
FREQUENCY (MHz)
(mA)
4 PULSES, PRF = 10kHz245678910
IPP vs. OUTPUT FREQUENCYMAX4810/11/12 toc06
FREQUENCY (MHz)
IPP
(mA)
CONTINUOUS SWITCHING,
VPP_ = VCC_ = +5V,
VNN_ = VEE_ = -5V,
VDD = +3.3V, NO LOAD
IPP vs. TEMPERATURE
MAX4810/11/12 toc07
TEMPERATURE (°C)
(mA)
4 PULSES AT 10MHz, PRF = 10kHz10203040506070
IPP vs. TEMPERATUREMAX4810/11/12 toc08
TEMPERATURE (°C)
(mA)
CONTINUOUS SWITCHING,
fOUT = 2.5MHz,
VPP_ = VCC_ = +5V,
VNN_ = VEE_ = -5V,
VDD = +3.3V, NO LOAD
INN vs. OUTPUT FREQUENCY
MAX4810/11/12 toc09
FREQUENCY (MHz)
INN
(mA)
4 PULSES, PRF = 10kHz
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
Typical Operating Characteristics (continued)(VDD= +3.3V, VCC_ = +12V, VEE_ = -12V, VSS= -100V, VPP_ = +100V, VNN_ = -100V, fOUT= 5MHz, TA= +25°C, unless otherwise noted.)245678910
INN vs. OUTPUT FREQUENCYMAX4810/11/12 toc10
FREQUENCY (MHz)
INN
(mA)
CONTINUOUS SWITCHING,
VPP_ = VCC_ = +5V,
VNN_ = VEE_ = -5V,
VDD = +3.3V, NO LOAD
INN vs. TEMPERATURE
MAX4810/11/12 toc11
TEMPERATURE (°C)
INN
(mA)
4 PULSES AT 10MHz, PRF = 10kHz10203040506070
INN vs. TEMPERATUREMAX4810/11/12 toc12
TEMPERATURE (°C)
INN
(mA)
CONTINUOUS SWITCHING,
fOUT = 2.5MHz,
VPP_ = VCC_ = +5V,
VNN_ = VEE_ = -5V,
VDD = +3.3V, NO LOAD
OUT RISE TIME (GND TO VPP_)
vs. VCC_/VEE_ SUPPLY VOLTAGEMAX4810/11/12 toc13
tROP
(ns)
VCC_/VEE_ SUPPLY VOLTAGE (V)
+4.75/-4.75+7.5/-7.5+12/-12
+5/-5+10/-10+12.6/-12.6
RL = 100Ω, CL = 100pF
OUT FALL TIME (GND TO VNN_)
vs. VCC_/VEE_ SUPPLY VOLTAGEMAX4810/11/12 toc14
FON
(ns)
VCC_/VEE_ SUPPLY VOLTAGE (V)
+4.75/-4.75+7.5/-7.5+12/-12
+5/-5+10/-10+12.6/-12.6
RL = 100Ω, CL = 100pF
INP-TO-OUT RISE PROPAGATION DELAY
vs. VCC_/VEE_ SUPPLY VOLTAGEMAX4810/11/12 toc15
VCC_/VEE_ SUPPLY VOLTAGE (V)
tPLH
(ns)
+4.75/-4.75+7.5/-7.5+12/-12
+5/-5+10/-10+12.6/-12.6
RL = 100Ω, CL = 100pF10203040506070
INP-TO-OUT RISE PROPAGATION DELAY
vs. TEMPERATUREMAX4810/11/12 toc16
TEMPERATURE (°C)
tPLH
(ns)
RL = 100Ω, CL = 100pF
INP-TO-OUT FALL PROPAGATION DELAY
vs. VCC_/VEE_ SUPPLY VOLTAGEMAX4810/11/12 toc17
tPHL
(ns)
+4.75/-4.75+7.5/-7.5+12/-12
+5/-5+10/-10+12.6/-12.6
RL = 100Ω, CL = 100pF10203040506070
INP-TO-OUT FALL PROPAGATION DELAY
vs. TEMPERATUREMAX4810/11/12 toc18
TEMPERATURE (°C)
tPHL
(ns)
RL = 100Ω, CL = 100pF
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
Pin Description
PINNAMEFUNCTIONCGP1Channel 1 High-Side Gate Input. Connect a 1nF to 10nF capacitor between CDP1 and CGP1 as close as
possible to the device.
2 , 3VPP1
Channel 1 High-Side Positive Supply Voltage Input. Bypass VPP1 to GND with a 0.1µF as close as
possible to the device. See the Power Supplies and Bypassing section. Depending on the output,
additional bypassing may be required.
4, 10, 33,N.C.No Connection. Not connected internally.OP1Channel 1 High-Side Drain OutputOCP1Channel 1 High-Side Clamp Output
7, 15, 28,
36, 44, 55GNDGroundOCN1Channel 1 Low-Side Clamp OutputON1Channel 1 Low-Side Drain Output
11, 12VNN1
Channel 1 High-Side Negative Supply Voltage Input. Bypass VNN1 to GND with a 0.1µF as close as
possible to the device. See the Power Supplies and Bypassing section. Depending on the output,
additional bypassing may be required.CGN1Channel 1 Low-Side Gate Input. Connect a 1nF to 10nF capacitor between CDN1 and CGN1 as close as
possible to the device.CDN1Channel 1 Low-Side Driver Output. Connect a 1nF to 10nF capacitor between CDN1 and CGN1 as close
as possible to the device.
16, 54VCC1
Channel 1 Gate-Drive Supply Voltage Input. Bypass VCC1 to GND with a 0.1µF as close as possible to
the device. See the Power Supplies and Bypassing section. Depending on the output, additional
bypassing may be required.INN1Channel 1 Low-Side Logic Input (Table 1)INC1Channel 1 Clamp Logic Input. Clamps OCP1 and OCN1 are turned on when INC1 is high and when INP1
and INN1 are low (see Table 1).INP1Channel 1 High-Side Logic Input (Table 1)EN1Channel 1 Enable Logic Input. Drive EN1 high to enable OP1 and ON1. Pull EN1 low to turn on the gate-
source short circuit (see Table 1).SHDNShutdown Logic Input (Table 1)AGNDAnalog Ground. Must be connected to common GND.EN2Channel 2 Enable Logic Input. Drive EN2 high to enable OP2 and ON2. Pull EN2 low to turn on the gate-
source short circuit. See Table 1.INP2Channel 2 High-Side Logic Input (Table 1)INC2Channel 2 Clamp Logic Input. Clamps OCP2 and OCN2 are turned on when INC2 is high and when INP2
and INN2 are low. See Table 1.INN2Channel 2 Low-Side Logic Input (Table 1)
27, 45VCC2
Channel 2 Gate-Drive Supply Voltage Input. Bypass VCC2 to GND with a 0.1µF as close as possible to
the device. See the Power Supplies and Bypassing section. Depending on the output, additional
bypassing may be required.CDN2Channel 2 Low-Side Driver Output. Connect a 1nF to 10nF capacitor between CDN2 and CGN2 as close
as possible to the device.CGN2Channel 2 Low-Side Gate Input. Connect a 1nF to 10nF capacitor between CDN2 and CGN2 as close as
possible to the device.
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
Detailed DescriptionThe MAX4810/MAX4811/MAX4812 are dual high-volt-
age, high-speed pulsers that can be independently
configured for either unipolar or bipolar pulse outputs.
These devices have independent logic inputs for full
pulse control and independent active clamps. The
clamp input, INC_, can be set high to activate the
clamp automatically when the device is not pulsing to
the positive or negative high-voltage supplies.
Logic Inputs (INP_, INN_, INC_, EN_, SHDN)The MAX4810/MAX4811/MAX4812 have a total of nine
logic input signals. SHDN controls power-up and power-
down of the device. There are two sets of INP_, INN_,
INC_, and EN_ signals: one for each channel. INP_
PINNAMEFUNCTION31, 32VNN2
Channel 2 High-Side Negative Supply Voltage Input. Bypass VNN2 to GND with a 0.1µF as close as
possible to the device. See the Power Supplies and Bypassing section. Depending on the output,
additional bypassing may be required.ON2Channel 2 Low-Side Drain OutputOCN2Channel 2 Low-Side Clamp OutputOCP2Channel 2 High-Side Clamp OutputOP2Channel 2 High-Side Drain Output
40, 41VPP2
Channel 2 High-Side Supply Voltage Input. Bypass VPP2 to GND with a 0.1µF as close as possible to the
device. See the Power Supplies and Bypassing section. Depending on the output, additional bypassing
may be required.CGP2Channel 2 High-Side Gate Input. Connect a 1nF to 10nF capacitor between CDP2 and CGP2 as close as
possible to the device.CDP2Channel 2 High-Side Driver Output. Connect a 1nF to 10nF capacitor between CDP2 and CGP2 as close
as possible to the device.CGC2Channel 2 High-Side Clamp Gate Input. Connect a 1nF to 10nF capacitor between CDC2 and CGC2 as
close as possible to the device.CDC2Channel 2 High-Side Clamp Driver Output. Connect a 1nF to 10nF capacitor between CDC2 and CGC2 as
close as possible to the device.VEE2
Channel 2 Negative Supply Input. |VEE2| ≤ VCC2. Gate Drive Supply Voltage for the OCP clamp. Bypass
VEE2 to GND with a 0.1µF as close as possible to the device. See the Power Supplies and Bypassing
section. Depending on the output, additional bypassing may be required.VDD
Logic Supply Voltage Input. Bypass VDD to GND with a 0.1µF as close as possible to the device. See the
Power Supplies and Bypassing section. Depending on the output, additional bypassing may be
required.VSSSubstrate Voltage. Connect VSS to a voltage equal to or more negative than the more negative of VNN1 or
VNN2.VEE1
Channel 1 Negative Supply Input. |VEE1| ≤ VCC1. Gate Drive Supply Voltage for the OCP clamp. Bypass
VEE1 to GND with a 0.1µF as close as possible to the device. See the Power Supplies and Bypassing
section. Depending on the output, additional bypassing may be required.CDC1Channel 1 High-Side Clamp Driver Output. Connect a 1nF to 10nF capacitor between CDC1 and CGC1 as
close as possible to the device.CGC1Channel 1 High-Side Clamp Gate Input. Connect a 1nF to 10nF capacitor between CDC1 and CGC1 as
close as possible to the device.CDP1Channel 1 High-Side Driver Output. Connect a 1nF to 10nF capacitor between CDP1 and CGP1 as close
as possible to the device.
—EPExposed Pad. EP must be connected to VSS. Do not use EP as the only VSS connection for the device.
Pin Description (continued)
MAX4810/MAX4811/MAX4812
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulserscontrols the on and off states of the high side FET, INN_
controls the on and off states of the low side FET, INC_
controls the active clamp and EN_ controls the gate to
source short. These signals give complete control of the
output stage of each driver (see Table 1 for all logic
combinations).
The MAX4810/MAX4811/MAX4812 logic inputs are
CMOS logic compatible and the logic level are refer-
enced to VDDfor maximum flexibility. The low 5pF (typ)
input capacitance of the logic inputs reduces loading
and increases switching speed.
High-Voltage Output Protection
(MAX4811 Only)The high-voltage outputs of the MAX4811 feature an
integrated overvoltage protection circuit that allows the
user to implement multilevel pulsing by connecting the
outputs of multiple pulser channels in parallel. Internal
diodes in series with the ON_ and OP_ outputs prevent
the body diode of the high-side and low-side FETs from
switching on when a voltage greater than VNN_or VPP_
Active ClampsThe MAX4810/MAX4811/MAX4812 feature an active
clamp circuit to improve pulse quality and reduce 2nd
harmonic output. The clamp circuit consists of an N-
channel (DC-coupled) and a P-channel (AC and DC
delay coupled) high-voltage FETs that are switched on
or off by the logic clamp input (INC_). The MAX4810/
MAX4811 feature protected clamp devices, allowing
the clamp circuit to be used in bipolar pulsing circuits
(see Figures 1 and 2). A diode in series with the OCN_
output prevents the body diode of the low-side FET
from turning on when a voltage lower than GND is pre-
sent. Another diode in series with the OCP_ output pre-
vents the body diode of the high-side FET from turning
on when a voltage higher than ground is present. The
MAX4812 does not have diode protection on the clamp
outputs. Thus, the device is suitable for use in circuits
where only unipolar pulsing is required.
The user can connect the active clamp input (INC_) to a
logic-high voltage and drive only the INP_ and INN_
inputs to minimize the number of signals used to drive the
X = Don’t care.
0 = Logic-low.
1 = Logic-high.
INPUTSOUTPUTSSDHN
EN_INP_INN_INC_OP_ON_OCP_,
OCN_
STATEXX0High
impedance
High
impedance
High
impedance
Powered down, INP_/INN_ disabled, gate-source
short disabledXX1High
impedance
High
impedanceGNDPowered down, INP_/INN_ disabled, gate-source
short disabledXX0High
impedance
High
impedance
High
impedance
Powered up, INP_/INN_ disabled, gate-source short
enabledXX1High
impedance
High
impedanceGNDPowered up, INP_/INN_ disabled, gate-source short
enabled1000High
impedance
High
impedance
High
impedance
Powered up, all inputs enabled, gate-source short
disabled1001High
impedance
High
impedanceGNDPowered up, all inputs enabled, gate-source short
disabled101XHigh
impedanceVNN_High
impedance
Powered up, all inputs enabled, gate-source short
disabled110XVPP_High
impedance
High
impedance
Powered up, all inputs enabled, gate-source short
disabled111XVPP_VNN_High
impedanceNot allowed (3ns maximum overlap)
Table 1. Truth Table
