MAX4714EXT ,PLASTIC ENCAPSULATED DEVICES MAX4714EXT Rev. A RELIABILITY REPORT FOR MAX4714EXT PLASTIC EN ..
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MAX4714EXT
PLASTIC ENCAPSULATED DEVICES
MAX4714EXT Rev. A RELIABILITY REPORT FOR
MAX4714EXT PLASTIC ENCAPSULATED DEVICES April 16, 2002
MAXIM INTEGRATED PRODUCTS 120 SAN GABRIEL DR. SUNNYVALE, CA 94086
Written by Reviewed by
Jim Pedicord Bryan J. Preeshl Quality Assurance Quality Assurance Reliability Lab Manager Executive Director
Conclusion The MAX4714 successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim’s continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim’s quality and reliability standards.
Table of Contents
I. ........Device Description V. ........Quality Assurance Information
II. ........Manufacturing Information VI. .......Reliability Evaluation
III. .......Packaging Information
IV. .......Die Information ......Attachments
I. Device Description A. General The MAX4714 is a low on-resistance, low-voltage single-pole/double-throw (SPDT) analog switch that operates from a single +1.6V to +3.6V supply. The MAX4714 has break-before-make switching. This device also has fast switching speeds (tON = 18ns max, tOFF = 12ns max).
When powered from a +3V supply, the MAX4714 features 0.8 max on-resistance (RON), with 0.18 max RON matching and flatness. The digital logic input is 1.8V CMOS compatible when using a single +3V supply.
The MAX4714 is pin compatible with the MAX4599 and is available in a 6-pin SC70 package B. Absolute Maximum Ratings Item Rating V+, IN to GND -0.3V to +4V COM, NC, NO to GND (Note 1) -0.3V to (V+ + 0.3V) Continuous Current NO,NC to COM +/-150mA Peak Current NO,NC to COM (pulsed at 1ms, 10% duty cycle) +/-300mA Junction Temperature +150°C Storage Temp. -65°C to +150°C Lead Temp. (10 sec.) +300°C Power Dissipation 6-Pin SC70 247mW Derates above +70°C 6-Pin SC70 3.1mW/°C
II. Manufacturing Information A. Description/Function: 0.8 Ohm, Low-Voltage, Single-Supply SPDT Analog Switch in SC70 B. Process: TC35 (0.35 Micron Poly Gate Process) C. Number of Device Transistors: 135 D. Fabrication Location: Taiwan E. Assembly Location: Malaysia or Thailand F. Date of Initial Production: April, 2001
III. Packaging Information A. Package Type:
6-Lead SC70 B. Lead Frame: Copper C. Lead Finish: Copper or Alloy 42 D. Die Attach: Non-Conductive E. Bondwire: Gold (1.0 mil dia.) F. Mold Material: Epoxy with silica filler G. Assembly Diagram: Buildsheet # 05-1201-0224 H. Flammability Rating: Class UL94-V0 I. Classification of Moisture Sensitivity per JEDEC standard JESD22-A112: Level 1
IV. Die Information A. Dimensions: 30 x 30 mils B. Passivation: Si3N4/SiO2 (Silicon nitride/ Silicon dioxide) C. Interconnect: Al/Cu/Si/Ti D. Backside Metallization: None E. Minimum Metal Width: 0.35 microns (as drawn) F. Minimum Metal Spacing: 0.35 microns (as drawn) G. Bondpad Dimensions: 5 mil. Sq. H. Isolation Dielectric: SiO2
V. Quality Assurance Information A. Quality Assurance Contacts: Jim Pedicord (Reliability Lab Manager) Bryan Preeshl (Executive Director of QA) Kenneth Huening (Vice President) B. Outgoing Inspection Level: 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% For all Visual Defects. C. Observed Outgoing Defect Rate: < 50 ppm D. Sampling Plan: Mil-Std-105D
VI. Reliability Evaluation A. Accelerated Life Test The results of the 135°C biased (static) life test are shown in
Table 1. Using these results, the Failure Rate (l) is calculated as follows:
l = 1 = 1.83 (Chi square value for MTTF upper limit) MTTF 192 x 4389 x 78 x 2 Temperature Acceleration factor assuming an activation energy of 0.8eV l = 13.92 x 10-9 l = 13.92 F.I.T. (60% confidence level @ 25°C) This low failure rate represents data collected from Maxim’s reliability qualification and monitor programs. Maxim also performs weekly Burn-In on samples from production to assure reliability of its processes. The reliability required for lots which receive a burn-in qualification is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece sample. Maxim performs failure analysis on rejects from lots exceeding this level. The attached Burn-In Schematic (Spec. # 06-5735) shows the static circuit used for this test. Maxim also performs 1000 hour life test monitors quarterly for each process. This data is published in the Product Reliability Report (RR-
1M). B. Moisture Resistance Tests Maxim evaluates pressure pot stress from every assembly process during qualification of each new design. Pressure Pot testing must pass a 20% LTPD for acceptance. Additionally, industry standard 85°C/85%RH or HAST tests are performed quarterly per device/package family. C. E.S.D. and Latch-Up Testing The AH80 die type has been found to have all pins able to withstand a transient pulse of ±2500V, per Mil-Std-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of ±250mA and/or ±20V.
Table 1 Reliability Evaluation Test Results
MAX4714EXT
TEST ITEM TEST CONDITION FAILURE SAMPLE NUMBER OF IDENTIFICATION SIZE FAILURES
Static Life Test (Note 1) Ta = 135°C DC Parameters 78 0 Biased & functionality Time = 192 hrs.
Moisture Testing (Note 2) Pressure Pot Ta = 121°C DC Parameters 77 0 P = 15 psi. & functionality RH= 100% Time = 168hrs. 85/85 Ta = 85°C DC Parameters 44 0 RH = 85% & functionality Biased Time = 1000hrs.
Mechanical Stress (Note 2) Temperature -65°C/150°C DC Parameters 77 0 Cycle 1000 Cycles Method 1010 Note 1: Life Test Data may represent plastic DIP qualification lots. Note 2: Generic Process/Package data
Attachment #1 TABLE II. Pin combination to be tested. 1/ 2/ 1/ Table II is restated in narrative form in 3.4 below. 2/ No connects are not to be tested. 3/ Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc). 3.4 Pin combinations to be tested. a. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. b. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins (e.g., VSS1, or VSS2 or VSS3 or VCC1, or VCC2) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. c. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open.
TERMINAL B
TERMINAL A
CURRENT
PROBE
(NOTE 6)
R = 1.5kWW
C = 100pf
SHORT
R2
S2 R1
