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MAX3992UTG+
10Gbps Clock and Data Recovery with Equalizer
General DescriptionThe MAX3992 is a 10Gbps clock and data recovery
(CDR) with equalizer IC for XFP optical transmitters. The
MAX3992 and the MAX3991 (CDR with limiting amplifier)
form a signal conditioner chipset for use in XFP trans-
ceiver modules. The chipset is XFI compliant and offers
multirate operation for data rates from 9.95Gbps to
11.1Gbps.
The MAX3992 recovers the data for up to 12 inches of
FR-4 and one connector without the need for a stand-
alone equalizer. The phase-locked loop is optimized for
jitter tolerance in SONET, Ethernet, and Fibre-Channel
applications. Low jitter generation of 4mUIRMSleaves
adequate margin for meeting SONET jitter requirements
at the optical output.
An AC-based power detector asserts the loss-of-signal
(LOS) output when the input signal is removed. An exter-
nal reference clock, with frequency equal to 1/64 or 1/16
of the serial data rate, is used to aid in frequency acqui-
sition. A loss-of-lock (LOL) indicator is provided to indi-
cate the lock status of the receiver PLL.
The MAX3992 is available in a 4mm x 4mm, 24-pin QFN
package. It consumes 356mW from a single +3.3V sup-
ply and operates over a 0°C to +85°C temperature range.
Applications9.95Gbps to 11.1Gbps Optical XFP Modules
SONET OC-192/SDH STM-64 XFP Transceivers
10.3Gbps/11.1Gbps Ethernet XFP Transceivers
10.5Gbps Fibre-Channel XFP Transceivers
10Gbps DWDM Transceivers
10Gbps XFP Copper Modules
High-Speed Backplane Interconnects
FeaturesMultirate Operation from 9.95Gbps to 11.1GbpsSpan Up to 300mm (12in) FR4 with One ConnectorLow-Output Jitter Generation: 4mUIRMSLow-Output Deterministic Jitter: 4.6psP-PXFI-Compliant Input InterfaceLOS IndicatorLOL IndicatorPower Dissipation: 356mW
MAX3992
10Gbps Clock and Data Recovery
with Equalizer19-3496; Rev 2; 11/06
Ordering Information
PARTTEMP RANGEPIN-
PACKAGE
PKG
CODEMAX3992UTG0°C to +85°C24 QFNT2444-4
MAX3992UTG+*0°C to +85°C24 QFNT2444-4
VCC1
GND2
SDI-3
SDI+4
GND5
VCC6
VCC18
GND17
SDO-16
SDO+15
GND14
VCC13
SCLKO+
SCLKO-
FCTL2
POL
CFIL
VTH
FCTL1
REFCLK-
REFCLK+
LOS
LOL
MAX3992
4mm x 4mm QFN**THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT-BOARD GROUND FOR
PROPER THERMAL AND ELECTRICAL PERFORMANCE.
TOP VIEW
Pin Configuration
Typical Application Circuit appears at end of data sheet.*Future product—contact factory for availability.
+Denotes lead-free package.
MAX3992
10Gbps Clock and Data Recovery
with Equalizer
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +4.0V
Input Voltage Levels
(SDI+, SDI-, REFCLK+,
REFCLK-)....................................(VCC- 1.0V) to (VCC+ 0.5V)
CML Output Voltage
(SDO+, SDO-, SCLKO+,
SLCKO-)......................................(VCC- 1.0V) to (VCC+ 0.5V)
Voltage at (CFIL, LOL, VTH, POL,
LOS, FCTL1, FCTL2)..............................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
24-Pin QFN (derate 20.8mW/°C above +85°C).........1355mW
Junction Temperature Range.............................-40°C to+150°C
Storage Temperature Range.............…………..-55°C to +150°C
Lead Temperature (soldering, 10s)..……………………..+300°C
ELECTRICAL CHARACTERISTICS(See Table 1 for operating conditions. Typical values at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITSSupply CurrentICC108145mA
DATA INPUT SPECIFICATION (SDI±)Single-Ended Input ResistanceRSE425058Ω
Differential Input ResistanceRD84100116Ω
Single-Ended Input Resistance
Matching±5%
0.1GHz to 5.5GHz (Note 1)15Differential-Input Return LossSDD115.5GHz to 12GHz (Note 1)6dB
Differential to Common-Mode
ConversionSCD110.1GHz to 15GHz17dB
Common-Mode Input Return
LossSCC110.1GHz to 15GHz7dB
REFERENCE CLOCK SPECIFICATION (REFCLK±)Single-Ended Input Resisitance84100116Ω
Differential Input Resistance168200232Ω
CML OUTPUT SPECIFICATION (SDO±)SDO± Differential Output Swing(Note 2)575650725mVP-P
SDO± Output Common-Mode
VoltageRL = 50Ω to VCCVCC -
0.16V
SCLKO± Differential Output380mVP-P
Single-Ended Output Resistance425058Ω
Differential Output ResistanceRO84100116Ω
Single-Ended Output Resistance
Matching±5%
0.1GHz to 5.5GHz (Note 1)13Differential-Output Return LossSDD225.5GHz to 12GHz (Note 1)8dB
Rise/Fall Time(20% to 80%) (Note 2)182330ps
Power-Down Assert Time(Note 3)50µs
MAX3992
10Gbps Clock and Data Recovery
with Equalizer
ELECTRICAL CHARACTERISTICS (continued)(See Table 1 for operating conditions. Typical values at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
JITTER SPECIFICATION120kHz < f ≤ 8MHz (Notes 2, 4)0.050.25Jitter PeakingJPf ≤ 120kHz (Note 5)0.03dB
Jitter Transfer BandwidthJBW(Notes 2, 4)5.68.0MHz
f = 400kHz2.8>2.8N ote 6)
f = 4MHz0.40.55Sinusoidal Jitter Tolerance(Notes 2, 4, 7)
f = 80MHz0.40.45
UIP-P
Jitter Generation(Notes 2, 4, 8)45.5mUIRMS
Serial-Data Output Deterministic
JitterDJPRBS 27 - 1 (Note 2)4.613psP-P
PLL ACQUISITION/LOCK SPECIFICATIONAcquisition TimeFigures 1, 2 (Note 2)200µs
LOL Assert TimeFigure 1 (Note 2)90µs
Maximum Frequency Pullin Time(Note 9)2ms
Frequency Difference at which
LOL Is Asserted∆f/fREFCLK∆f = |fVCO / N - fREFCLK|,
N = 16 or 64651ppm
Frequency Difference at which
LOL Is Deasserted∆f/fREFCLK∆f = |fVCO / N - fREFCLK|,
N = 16 or 64500ppm
LOSS-OF-SIGNAL (LOS) SPECIFICATIONVTH Control Voltage RangeVTH150500mV
LOS Gain FactorVTH/
VLOS_ASSERT10V/V
Minimum LOS Assert VoltageVLOS_ASSERT15mV
Maximum LOS Assert VoltageVLOS_ASSERT50mV
LOS Gain-Factor Accuracy(Notes 2, 10)-1.5+1.5dB
LOS Hysteresis(Notes 2, 11)3.53.73.9dB
LOS Gain-Factor Stability(Note 2) Overtemperature and supply-10+10%
LOS Assert TimeFigure 2 (Note 2)390µs
LOS Deassert TimeFigure 2 (Note 2)90µs
VTH Input Current-5+5µA
LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LOS, FCTL1, FCTL2)Input High VoltageVIH2.0V
Input Low VoltageVIL0.8V
Input Current-30+30µA
Output High VoltageVOHSourcing 30µAVCC -
0.5V
Output Low VoltageVOLSinking 1mA0.4V
MAX3992
10Gbps Clock and Data Recovery
with Equalizer
ELECTRICAL CHARACTERISTICS (continued)(See Table 1 for operating conditions. Typical values at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
Note 1:Measured with 100mVP-Pdifferential amplitude.
Note 2:Guaranteed by design and characterization.
Note 3:Measured from the time that the FCTL1 input goes high with FCTL2 = 0, to the time when the supply current drops to less
than 40% of the nominal value.
Note 4:Measured with PRBS = 231 - 1.
Note 5:Larger CFILTcan be used to reduce jitter peaking at ≤120kHz. A larger CFILTwill increase acquisition time. CFILTshould
not exceed 200nF.
Note 6:Measurement limited by test equipment.
Note 7:Jitter tolerance is for BER ≤10-12, measured with additional 0.1VI deterministic jitter through 15 inches of FR4. (See Typical
Operating Characteristics1.)
Note 8:Measured with 50kHz to 80MHz SONET filter.
Note 9:Applies on power-up or after standby.
Note 10:Over process, temperature and supply.
Note 11:Hysteresis is defined as 20Log(VLOS-DEASSERT/VLOS-ASSERT).
Table 2. Serial Data Rate and Reference Clock Frequency
APPLICATIONDATA RATE (Rb)
(Gbps)
/16 REFERENCE CLOCK
FREQUENCY (MHz)
/64 REFERENCE CLOCK
FREQUENCY (MHz)OC-192 SONET – SDH649.95328622.08155.52
OC-192 SONET over FEC10.664666.5166.625
ITU G.70910.709669.3125167.328125
10Gbps Ethernet, IEEE 802.3ae10.3125644.53125161.1328125
10Gbps Ethernet over ITU G.70911.09573693.483125173.3707813
10Gbps Fibre Channel10.51875657.421875164.355469
Table 1. Operating Conditions (Unless otherwise noted, FCTL1 = FCTL2 = 0.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply VoltageVCC3.03.6V
Ambient TemperatureTA0+85°C
Input Data RateRb(See Table 2)Gbps
Differential Input Voltage to
Transmission LineVD0 to 12 inches FR-44001000mVP-P
Output Load ResistanceRLRL is AC-coupled50Ω
REFCLK± Differential Input Voltage
Swing3001600mVP-P
REFCLK Duty Cycle3070%
Rb / 16REFCLK FrequencyfREFCLKRb / 64GHz
REFCLK AccuracyRelative to Rb / 16 or Rb / 64-100+100ppm
FREFCLK = Rb / 641200REFCLK Rise/Fall Times (20% to
80%)fREFCLK = Rb / 16300ps
REFCLK Random JitterNoise bandwidth < 100MHz10psRMS
Note:The part should be in standby mode when data rates are being switched.
MAX3992
10Gbps Clock and Data Recovery
with EqualizerFigure 1. TX LOL Assert and PLL Acquisition Time
LOL
ACQUISITION
TIME
LOL
ASSERT TIME
*ASSERT AND ACQUISITION TIME ARE DEFINED
WITH A VALID REFERENCE CLOCK APPLIED.
651ppm
500ppm
∆f/fREFCLK
Figure 2. LOS Assert/Deassert Time
LOS
LOS DEASSERT TIME
DATA INPUT
POWER
LOS ASSERT TIME
LOL
ACQUISITION TIME
MAX3992
10Gbps Clock and Data Recovery
with Equalizer
Typical Operating Characteristics(VCC= 3.3V, TA= +25°C, unless otherwise noted.)
NORMALIZED BIT TIME (UI)
MAX3992 INPUT
(15in FR-4)MAX3992 toc01
DIFFERENTIAL SIGNAL AMPLITUDE (mV)-500
RECOVERED REFERENCE SIGNAL
PRBS 231-1 15in FR-4
MAX3992 toc02
DIFFERENTIAL SIGNAL AMPLITUDE
(100mV/div)
NORMALIZED BIT TIME (UI)10
JITTER GENERATION vs. POWER-SUPPLY
WHITE NOISE AMPLITUDE (BW < 100kHz)
MAX3992 toc03
NOISE AMPLITUDE (mVRMS)
JITTER GENERATION (mUI
RMS
PRBS 231-1
POWER-SUPPLY INDUCED OUTPUT
JITTER vs. RIPPLE FREQUENCYMAX3992 toc04
FREQUENCY (Hz)
JITTER GENERATION (ps
P-P/
P-P100k10k
0.0710M
SINUSOIDAL JITTER TOLERANCE
12in FR-4 231-1 PRBS DATAMAX3992 toc05
FREQUENCY (Hz)
JITTER TOLERANCE (U|
P-P
10M1M100k
0.0110k100M
TOLERANCE EXCEEDS
MODULATION
CAPABILITIES OF TEST
EQUIPMENT
XFI TELECOM
MASK
JITTER TRANSFER
MAX3992 toc06
FREQUENCY (Hz)
JITTER TRANSFER (dB)
10M1M10k100k
-21100M
MAX3992
SUPPLY CURRENT vs. TEMPERATURE
MAX3992 toc07
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
DIFFERENTIAL S11
SDD11MAX3992 toc08
FREQUENCY (Hz)
SDD11 (dB)
10G1G100M
10M100G
XFI MASK
