MAX3984UTE+ Fast Delivery |IC PHOENIX CO.,LIMITED

MAX3984UTE+ ,1Gbps to 10Gbps Preemphasis Driver with Receive EqualizerApplicationsTEMP PKG PART PIN-PACKAGE8.5Gbps Fibre Channel Active Cable AssembliesRANGE CODE10.3Gbp ..
MAX398CSE ,Precision, 8-Channel/Dual 4-Channel, Low-Voltage, CMOS Analog MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = V = +2.4V, V = ..
MAX398CSE ,Precision, 8-Channel/Dual 4-Channel, Low-Voltage, CMOS Analog MultiplexersMAX398/MAX39919-0299; Rev. 2; 7/96Precision, 8-Channel/Dual 4-Channel,Low-Voltage, CMOS Analog Mult ..
MAX398CSE+ ,Precision, 8-Channel/Dual 4-Channel, Low-Voltage, CMOS Analog MultiplexersApplicationsMAX398CGE 0°C to +70°C 16 QFN-EP* G1655-3Sample-and-Hold CircuitsMAX398CEE 0°C to +70°C ..
MAX398CSE+T ,Precision, 8-Channel/Dual 4-Channel, Low-Voltage, CMOS Analog MultiplexersApplicationsMAX398CGE 0°C to +70°C 16 QFN-EP* G1655-3Sample-and-Hold CircuitsMAX398CEE 0°C to +70°C ..
MAX398EJE ,Precision, 8-Channel/Dual 4-Channel, Low-Voltage, CMOS Analog MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = V = +2.4V, V = ..
MAX749 ,Digitally Adjustable LCD Bias SupplyApplications______________Ordering InformationNotebook ComputersPART TEMP. RANGE PIN-PACKAGELaptop ..
MAX7490EEE ,Dual Universal Switched-Capacitor FiltersFeaturesThe MAX7490/MAX7491 consist of two identical low- Dual 2nd-Order Filter in a 16-Pin QSOP P ..
MAX7490EEE+ ,Dual Universal Switched-Capacitor FiltersFeaturesThe MAX7490/MAX7491 consist of two identical low-♦ Dual 2nd-Order Filter in a 16-Pin QSOP P ..
MAX7490EEE+ ,Dual Universal Switched-Capacitor FiltersApplicationsPIN-PART TEMP RANGE VOLTAGETunable Active FiltersPACKAGE(+V)Multipole FiltersMAX7490CEE ..
MAX7491 ,Dual Universal Switched-Capacitor FiltersApplicationsPIN-PART TEMP RANGE VOLTAGETunable Active FiltersPACKAGE(+V)Multipole FiltersMAX7490CEE ..
MAX7491EEE ,Dual Universal Switched-Capacitor FiltersFeaturesThe MAX7490/MAX7491 consist of two identical low- Dual 2nd-Order Filter in a 16-Pin QSOP P ..

MAX3984UTE+
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer
General Description
The MAX3984 is a single-channel, preemphasis driver
with input equalization that operates from 1Gbps to
10.3Gbps. It provides compensation for copper links,
such as 8.5Gbps Fibre Channel and 10.3Gbps
Ethernet, allowing spans of up to 10m with 24 AWG
cable. The driver provides four selectable preemphasis
levels, and the selectable input equalizer compensates
for up to 10in of FR-4 circuit board material at 10Gbps.
The MAX3984 also features SFP-compliant loss-of-sig-
nal (LOS) detection and TX_DISABLE. Selectable out-
put swing reduces EMI and power consumption. The
MAX3984 is packaged in a lead-free, 3mm x 3mm,
16-pin thin QFN and operates from a 0°C to +85°C tem-
perature range.
Applications
FeaturesDrives Up to 10m of 24 AWG CableDrives Up to 30in of FR-4Selectable 1000mVP-Por 1200mVP-PDifferential
Output SwingSelectable Output PreemphasisSelectable Input EqualizationLOS Detection with Built-In SquelchTransmit DisableHot Pluggable
MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
Ordering Information
19-0868; Rev 0; 7/07
+Denotes a lead-free package.
*EP = Exposed pad.
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
PARTTEMP
RANGEPIN-PACKAGEPKG
CODE
MAX3984UTE+ 0°C to +85°C 16 Thin QFN-EP* T1633F-3
8.5Gbps Fibre Channel
10.3Gbps Ethernet
Active Cable Assemblies
STM-64
TX_DISABLE
PE1
IN_LEV
PE0
OUT_LEV
IN+
IN-
LOSVCC
GND
GND
VCC
+3.3V
OUT+
OUT-
MAX3984
0.01μF
0.01μF
LOS
PE1
IN_LEV
PE0
OUT_LEV
VCC
GND
GND
+3.3V
IN+
IN-
MAX3984
OUT+
OUT-
0.01μF
0.01μF
22pF
39Ω
22pF
0.01μF
0.01μF
39Ω
22pF
39Ω
22pF
39Ω
LOS
LOS
PE1
IN_LEV
PE0
OUT_LEV
IN+
IN-
VCC
GND
GND
+3.3V
OUT+
OUT-
MAX3984
0.01μF
0.01μF
LOSPE1
IN_LEV
PE0
OUT_LEV
TX_DISABLE
VCC
GND
GND
VCC
+3.3V
IN+
IN-
MAX3984
OUT+
OUT-
0.01μF
0.01μF
0.01μF
0.01μF
≤ 10m (24 AWG)
UP TO 10Gbps
COPPER CABLE
DIFFERENTIAL
100Ω TWIN-AX
ACTIVE CABLE ASSEMBLY
Tx+
Tx-
Rx+
Rx-
DISK
ENCLOSURE
SWITCH
SERDES
≤ 5V
≥ 4.7kΩ
Rx+
Rx-
Tx+
Tx-
FABRIC SWTCH
SWITCH
SERDES
≤ 5V
RPULLUP≥ 4.7kΩ
Typical Operating Circuits
MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage Range (VCC).................................-0.5V to +4.1V
Continuous Output Current Range
(OUT+, OUT-)...............................................-25mA to +25mA
Input Voltage Range (IN+, IN-)..................-0.5V to (VCC+ 0.5V)
Logic Inputs Range (PE1, PE0,
TX_DISABLE, IN_LEV, OUT_LEV)..........-0.5V to (VCC+ 0.5V)
LOS Open-Collector Supply Voltage Range
(with ≥4.7kΩpullup).........................................-0.5V to +5.5V
Storage Ambient Temperature Range (TSTG)...-55°C to +150°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Supply Voltage VCC 3.0 3.3 3.6 V
Supply Noise Tolerance 1MHz f < 2GHz 40 mVP-P
Operating Ambient Temperature TA 0 25 85 °C
Bit Rate NRZ data 1.0 8.5 10.3 Gbps
Consecutive Identical Digits
(CID) CID (bits) 100 Bits
IN_LEV = high, Figure 2;
4.25Gbps < data rate 10.3Gbps 360 1200
IN_LEV = high, Figure 2;
1.25Gbps < data rate 4.25Gbps 360 1600
IN_LEV = high, Figure 2;
1.0Gbps data rate 1.25Gbps 360 2400
Input Swing (Measured
differentially at data source,
point A of Figure 2 and 3. Pins
LOS and TX_DISABLE are
floating.)
IN_LEV = low, Figure 3;
1.0Gbps < data rate 10.3Gbps 100 360
mVP-P
Time to Reach 50%
Mark/Space Ratio 1 μs
MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
OUT_LEV = low, TX_DISABLE = low 100 124 Supply Current ICC OUT_LEV = high, TX_DISABLE = low 120 148 mA
Inrush Current Beyond steady state supply current (Note 1) 10 mA
Power-On Delay (Note 1) 1 30 ms
EQUALIZER AND DRIVE SPECIFICATIONS
Input Return Loss S11 100MHz to 5GHz 10 dB
Input Resistance Measured differentially (Note 2) 85 100 115
Measured differentially at point B in Figure
2; TX_DISABLE = low, OUT_LEV = high,
PE1 = PE0 = high
1000 1300
Measured differentially at point B in Figure
2; TX_DISABLE = low, OUT_LEV = low,
PE1 = PE0 = high
800 1100
Different Output Swing
(Notes 3, 4)
TX_DISABLE = high, PE1 = PE0 = high 10
mVP-P
Common-Mode Output (AC)
(Note 4)
Measured at point B in Figure 2;
TX_DISABLE = low, OUT_LEV = high (Note 5) 25 mVRMS
Output Resistance ROUT OUT+ or OUT-, single-ended 42 50 58
Output Return Loss S22 100MHz to 5GHz 12 dB
Output Transition Time 20%
to 80% tr, tf 20% to 80% (Note 6) 32 40 ps
Random Jitter (Note 4) Measured at point D in Figure 3 (Note 7) 0.8 psRMS
PE1 PE0
0 0 3.5
0 1 6.5
1 0 9.5
Output Preemphasis Figure 1 (Note 3) 1 13
dB
Source to IN OUT to
load PE1 PE0
3m,
24 AWG 0 0
5m,
24 AWG 0 1
7m,
24 AWG 1 0
Residual Output Deterministic
Jitter at 1.0Gbps
(Notes 4, 8, and 9) 6-mil, 10in of
FR-4
10m,
24 AWG 1 1 0.02 UIP-P
ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at TA= +25°C, VCC= +3.3V, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Source to IN OUT to
load PE1 PE0
3m,
24 AWG 0 1
5m,
24 AWG 1 0
7m,
24 AWG 1 0
Residual Output Deterministic
Jitter at 5.0Gbps
(Notes 4, 8, and 9) 6-mil, 10in of
FR-4
10m,
24 AWG 1 1
0.09 0.12 UIP-P
Source to IN OUT to
load PE1 PE0
3m,
24 AWG 0 1
5m,
24 AWG 1 0
7m,
24 AWG 1 0
Residual Output Deterministic
Jitter at 8.5Gbps
(Notes 4, 8, and 9) 6-mil, 10in of
FR-4
10m,
24 AWG 1 1
0.15 0.20 UIP-P
Source to IN OUT to
load PE1 PE0
3m,
24 AWG 0 1
5m,
24 AWG 1 0
7m,
24 AWG 1 1
Residual Output Deterministic
Jitter at 10Gbps
(Notes 4, 8, and 9) 6-mil, 10in of
FR-4
10m,
24 AWG 1 1
0.18 0.25 UIP-P
PE1 PE0 Residual Output Deterministic
Jitter at 10.0Gbps
(Notes 4, 8, and 10)
10in of FR-4 at OUT±; no
cable; see Figure 3
0 0
0.10 UIP-P
Propagation Delay 230 ps
STATUS OUTPUT: LOS
IN_LEV = high (Note 11) 300 LOS Deassert IN_LEV = low (Note 11) 100
LOS Assert IN_LEV = high (Note 11) 80
mVP-P
IN_LEV = high (Note 11) 20 LOS Hysteresis (Note 4) mVP-P
MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at TA= +25°C, VCC= +3.3V, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LOS asserted 0 25 μA
LOS asserted; VOL 0.4V 1.0 mA LOS Open-Collector Current
Sink
(Note 12) 0 25 μA
LOS Response Time
(Note 4)
Time from VIN dropping below deassert level
or rising above assert level to 50% point of
LOS output transition 10 μs
LOS Transition Time
Rise time or fall time (10% to 90%);
pullup supply = 5.5V; external pullup 4.7k
200 ns
CONTROL INPUTS: TX_DISABLE, PE0, PE1, OUT_LEV, IN_LEV
Logic-High Voltage VIH 2.0 V
Logic-Low Voltage VIL 0.8 V
Logic-High Current IIHCurrent required to maintain logic-high state
at VIH > +2.0V -150 μA
Logic-Low Current IILCurrent required to maintain logic-low state
at VIL < +0.8V 350 μA
MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
Note 1:Supply voltage to reach 90% of final value in less than 100µs, but not less than 10µs. Power-on delay interval measured
from the 50% level of the final voltage at the filter’s device side to 50% level of final current. The supply is to remain at or
above 3V for at least 100ms. Only one full-scale transition is permitted during this interval. Aberrations on the transition are
limited to less than 100mV.
Note 2:IN+ and IN- are single-ended, 50Ωterminations to (VCC- 1.5V) ±0.2V.
Note 3:Load is 50Ω±1% at each side and the pattern is 0000011111 or equivalent pattern at 2.5Gbps.
Note 4:Guaranteed by design and characterization.
Note 5:PE1 = PE0 = logic-high (maximum preemphasis), load is 50Ω±1% at each side. The pattern is 11001100 (50% edge den-
sity) at 10Gbps. AC common-mode output is computed as:
VACCM_RMS= RMS[(VP+ VN) / 2) - VDCCM]
where:= time-domain voltage measured at OUT+ with at least 10GHz bandwidth.= time-domain voltage measured at OUT- with at least 10GHz bandwidth.
AC common-mode voltage (VACCM_RMS) expressed as an RMS value.
DC common-mode voltage (VDCCM) = average DC voltage of (VP+ VN) / 2.
Note 6:Using 0000011111 or equivalent pattern at 2.5Gbps. PE0 = PE1 = logic-low for minimum preemphasis. Measured within
2in of the output pins with Rogers 4350 dielectric, or equivalent, and ≥10-mil line width. For transition time, the 0% refer-
ence is the steady state level after four zeros, just before the transition, and the 100% reference level is the steady state
level after four consecutive logic ones.
Note 7:Pattern is 0000011111 or equivalent pattern at 10Gbps and 100mVP-Pdifferential swing. IN_LEV = logic-low and PE0 =
PE1 = logic-low for minimum preemphasis. Signal transition time is controlled by the 4th-order BT filter (7.5GHz band-
width) or equivalent. See Figure 3 for setup.
Note 8:Test pattern (464 bits): 100 zeros, 1010, PRBS7, 100 ones, 0101, PRBS7.
Note 9:Input range selection is IN_LEV = logic-high for FR-4 input equalization. Cables are unequalized, Amphenol Spectra-Strip
(160-2499-997) 24 AWG or equivalent. Residual deterministic jitter is the difference between the source jitter at point A
and the load jitter point D in Figure 2. The deterministic jitter (DJ) at the output of the transmission line must be from media
induced loss and not from clock source modulation. DJ is measured at point D of Figure 2.
Note 10:Input range selection is IN_LEV = logic-low. Residual deterministic jitter is the difference between the source jitter at point
A and the load jitter point D in Figure 3. The deterministic jitter (DJ) at the output of the transmission line must be from
media induced loss and not from clock source modulation. DJ is measured at point D of Figure 3.
Note 11:Measured with 101010… pattern at 10Gbps with less than 1in of FR-4 at the input.
Note 12:True open-collector outputs. VCC= 0 and the external 4.7kΩpullup resistor is connected to +5.5V.
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at TA= +25°C, VCC= +3.3V, unless otherwise noted.)
MAX3984
Figure 1. TX Preemphasis in dB
Figure 2. Transmit Test Setup (The points labeled A, B, and D are referenced for AC parameter test conditions. Deterministic jitter
and eye diagrams measured at point D.)
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
VLOW_PPVHIGH_PP
PE(dB) = 20 log VHIGH_PP
VLOW_PP⎜⎢⎜⎢
MAX3984
SIGNAL
SOURCE
PCB (FR-4)AB
OSCILLOSCOPE OR
ERROR DETECTOR
SMA CONNECTORSSMA CONNECTORS
24 AWG 100Ω TWIN-AX
6 MILS
6 MILS
6 MILSINOUT
TRANSMIT TEST SETUP
FR-4
4.0 ≤ εR ≤ 4.4
tanδ = 0.022
1in ≤ L ≤ 10inL = 2in
L ≤ 1in
MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
Figure 3. Receive-Side Test Setup (The points labeled A and D are referenced for AC parameter tests.)
MAX3984
SIGNAL
SOURCE
PCB (FR-4)AD
SMA CONNECTORSSMA CONNECTORS
6 MILS6 MILSINOUT
RECEIVE TEST SETUP
FR-4
4.0 ≤ εR ≤ 4.4
tanδ = 0.022
L = 10inL = 2in
OSCILLOSCOPE OR
ERROR DETECTOR
Typical Operating Characteristics
(VCC= +3.3V, TA= +25°C, PRBS7 + 100 CID pattern is PRBS 27, 100 zeros, 1010, PRBS 27, 100 ones, 0101, OUT_LEV = high, 10in
of FR-4 at the input, IN_LEV = high, 360mVP-Pat input of FR-4, unless otherwise noted.)
DETERMINISTIC JITTER
vs. CABLE LENGTH (10.3Gbps)
MAX3984 toc01
CABLE LENGTH (m)
DETERMINISTIC JITTER (UI)8642
PE[1,0] = 00
PE[1,0] = 01
PE[1,0] = 10
PE[1,0] = 11
DETERMINISTIC JITTER
vs. CABLE LENGTH (8.5Gbps)
MAX3984 toc02
CABLE LENGTH (m)
DETERMINISTIC JITTER (UI)8642
PE[1,0] = 00
PE[1,0] = 01
PE[1,0] = 10
PE[1,0] = 11
DETERMINISTIC JITTER
vs. CABLE LENGTH (5Gbps)
MAX3984 toc03
CABLE LENGTH (m)
DETERMINISTIC JITTER (UI)8642
PE[1,0] = 00
PE[1,0] = 11
PE[1,0] = 10
PE[1,0] = 01
MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizerypical Operating Characteristics (continued)
(VCC= +3.3V, TA= +25°C, PRBS7 + 100 CID pattern is PRBS 27, 100 zeros, 1010, PRBS 27, 100 ones, 0101, OUT_LEV = high, 10in
of FR-4 at the input, IN_LEV = high, 360mVP-Pat input of FR-4, unless otherwise noted.)
DETERMINISTIC JITTER
vs. FR-4 LENGTH (10.3Gbps)
MAX3984 toc04
FR-4 LENGTH (in)
DETERMINISTIC JITTER (UI)2010
IN_LEV = LOW,
0in OF FR-4 AT THE INPUT
PE[1,0] = 00
PE[1,0] = 01
PE[1,0] = 10
PE[1,0] = 11
DETERMINISTIC JITTER
vs. FR-4 LENGTH (8.5Gbps)
MAX3984 toc05
FR-4 LENGTH (in)
DETERMINISTIC JITTER (UI)2010
IN_LEV = LOW,
0in OF FR-4 AT THE INPUT
PE[1,0] = 00
PE[1,0] = 01
PE[1,0] = 10
PE[1,0] = 11
DETERMINISTIC JITTER
vs. FR-4 LENGTH (5Gbps)
MAX3984 toc06
FR-4 LENGTH (in)
DETERMINISTIC JITTER (UI)2010
IN_LEV = LOW,
0in OF FR-4 AT THE INPUT
PE[1,0] = 00
PE[1,0] = 01
PE[1,0] = 10
PE[1,0] = 11
INPUT RETURN LOSS vs. FREQUENCY
MAX3984 toc07
FREQUENCY (MHz)
DIFFERENTIAL S11 (dB)
10010,000
OUTPUT RETURN LOSS vs. FREQUENCY
MAX3984 toc08
FREQUENCY (MHz)
DIFFERENTIAL S22 (dB)
10010,000
TRANSIENT RESPONSE
MAX3984 toc09
A = 3.5dB, PE = 00
B = 6.5dB, PE = 01
C = 9.5dB, PE = 10
D = 13dB, PE = 11
2.5Gbps K28.7 PATTERN
OUT_LEV = HIGH
500ps/div
VERTICAL EYE OPENING
vs. CABLE LENGTH (10.3Gbps)
MAX3984 toc10
CABLE LENGTH (m)
VERTICAL EYE OPENING (mV
P-P87654321
PE[1,0] = 00
PE[1,0] = 01
PE[1,0] = 10
PE[1,0] = 11
VERTICAL EYE OPENING
vs. CABLE LENGTH (8.5Gbps)
MAX3984 toc11
CABLE LENGTH (m)
VERTICAL EYE OPENING (mV
P-P87654321
PE[1,0] = 00
PE[1,0] = 01
PE[1,0] = 11
PE[1,0] = 10
VERTICAL EYE OPENING
vs. CABLE LENGTH (5Gbps)
MAX3984 toc12
CABLE LENGTH (m)
VERTICAL EYE OPENING (mV
P-P87654321
PE[1,0] = 00
PE[1,0] = 01
PE[1,0] = 11
PE[1,0] = 10
MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
VERTICAL EYE OPENING
vs. FR-4 LENGTH (10.3Gbps)
MAX3984 toc13
FR-4 LENGTH (in)
VERTICAL EYE OPENING (mV
P-P2010
PE[1,0] = 00
PE[1,0] = 01
PE[1,0] = 11
PE[1,0] = 10
IN_LEV = LOW,
0in OF FR-4 AT THE INPUT
VERTICAL EYE OPENING
vs. FR-4 LENGTH (8.5Gbps)
MAX3984 toc14
FR-4 LENGTH (in)
VERTICAL EYE OPENING (mV
P-P2010
PE[1,0] = 00
PE[1,0] = 01
PE[1,0] = 11
PE[1,0] = 10
IN_LEV = LOW,
0in OF FR-4 AT THE INPUT
VERTICAL EYE OPENING
vs. FR-4 LENGTH (5Gbps)
MAX3984 toc15
FR-4 LENGTH (in)
VERTICAL EYE OPENING (mV
P-P2010
PE[1,0] = 00
PE[1,0] = 01
PE[1,0] = 11
PE[1,0] = 10
IN_LEV = LOW,
0in OF FR-4 AT THE INPUT
10m 24 AWG CABLE ASSEMBLY
OUTPUT WITHOUT MAX3984 AT 10.3Gbps
MAX3984 toc16
20ps/div
60mV
P-P
/div
10m 24 AWG CABLE ASSEMBLY
OUTPUT WITH MAX3984 AT 10.3Gbps
(PREEMPHASIS, PE[1,0] = 11, OUT_LEV = HIGH)
MAX3984 toc17
20ps/div
30mV
P-P
/div
10m 24 AWG CABLE ASSEMBLY
OUTPUT WITHOUT MAX3984 AT 8.5Gbps
MAX3984 toc18
20ps/div
60mV
P-P
/div
10m 24 AWG CABLE ASSEMBLY
OUTPUT WITH MAX3984 AT 8.5Gbps
(PREEMPHASIS, PE[1,0] = 11, OUT_LEV = HIGH)
MAX3984 toc19
30mV
P-P
/div
10m 24 AWG CABLE ASSEMBLY
OUTPUT WITHOUT MAX3984 AT 5Gbps
MAX3984 toc20
50ps/div
60mV
P-P
/div
10m 24 AWG CABLE ASSEMBLY
OUTPUT WITH MAX3984 AT 5Gbps
(PREEMPHASIS, PE[1,0] = 11, OUT_LEV = HIGH)
MAX3984 toc21
30mV
P-P
/div
Typical Operating Characteristics (continued)
(VCC= +3.3V, TA= +25°C, PRBS7 + 100 CID pattern is PRBS 27, 100 zeros, 1010, PRBS 27, 100 ones, 0101, OUT_LEV = high, 10in
of FR-4 at the input, IN_LEV = high, 360mVP-Pat input of FR-4, unless otherwise noted.)

Partno	Mfg	Dc	Qty	Available	Descript
MAX3984UTE+	MAXIM	N/a	72	avai	1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer