MAX3971AUGP Fast Delivery |IC PHOENIX CO.,LIMITED

MAX3971AUGP ,+3.3V, 10.7Gbps Limiting AmplifierApplications PKG PART TEMP RANGE PIN-PACKAGECODEVSR OC-192 ReceiversG2044-4 MAX3971AUGP 0°C to +85° ..
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MAX3971AUGP
+3.3V, 10.7Gbps Limiting Amplifier
General Description
The MAX3971A is a compact 10.7Gbps limiting amplifier.
It accepts signals over a wide range of input voltage levels
and provides constant-level output voltages with con-
trolled edge speeds. It functions as a data quantizer with
a 240mVP-Pdifferential CML output signal with a 100Ωdif-
ferential termination. The MAX3971A has a disable func-
tion that allows the outputs to be squelched if required by
the application.
The MAX3971A is designed to work with the MAX3970
transimpedance amplifier (TIA). The limiting amplifier
operates on a single +3.3V supply and functions over a
0°C to +85°C temperature range.
The MAX3971A is offered in die form and in a compact
4mm ×4mm 20-pin QFN and thin QFN package.
Applications
VSR OC-192 Receivers
10Gbps Ethernet Optical Receivers
10Gbps Fibre Channel Receivers
FeaturesSingle +3.3V Power Supply2mVP-PInput Sensitivity1.8ps Typical Deterministic Jitter (VIN= 800mVP-P)Dice and 4mm ×4mm QFN or Thin QFN Package
AvailableOutput Disable Feature
MAX3971A
+3.3V, 10.7Gbps Limiting Amplifier
MAX3971A
MAX3970
TIA100Ω
IN+
GNDIN-
GNDIN+
IN-
SUPPLY FILTER
VCC1VCC2VCC3
OUT+
OUT-
CZ-CZ+
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
DISABLE
50Ω
50Ω
+3.3V
+3.3V
Typical Application Circuit
*EP = Exposed pad.
**Dice are designed to operate over a 0°C to +110°C junction-
temperature (TJ) range, but are tested and guaranteed at = +25°C.
+Denotes lead-free package.
Ordering Information
PARTTEMP RANGEPIN-PACKAGEPKG
CODE
MAX3971AUGP 0°C to +85°C 20 QFN-EP* G2044-4
MAX3971AUTP 0°C to +85°C 20 Thin QFN-EP* T2044-3
MAX3971AUTP+ 0°C to +85°C 20 Thin QFN-EP* T2044-3
MAX3971AU/D 0°C to +85°C Dice** —
19-2391; Rev 2; 2/07
Pin Configurations appear at end of data sheet.
MAX3971A
+3.3V, 10.7Gbps Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC1, VCC2, VCC3......................-0.5V to +5.0 V
Voltage at IN+, IN-, DISABLE, CZ+, CZ-,
OUT+, OUT-.........................................+0.5V to (VCC+ 0.5V)
Differential Voltage Between CZ+ and CZ-...........................±1V
Differential Voltage Between IN+ and IN-...........................±2.5V
Continuous Power Dissipation (TA= +85°C)
20-Pin QFN (derate 20mW/°C above +85°C).................1.3W
Operating Ambient Temperature Range.............-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Die Attach Temperature...................................................+400°C
Lead Temperature (soldering, 10s).................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, output load = 50Ωto VCC, TA= 0°C to +85°C, unless otherwise noted. All AC parameters are measured with
a 223 - 1 PRBS pattern applied to the input at 10.7Gbps. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Supply CurrentICC5085mA
Small-Signal BandwidthBW10GHz
Input SensitivityVIN-min(Notes 1, 2)25mVP-P
Input OverloadVIN-max(Note 1)1200mVP-P
Low-Frequency CutoffCZ = 0.1µF (Note 1)6075kHz
5mVP-P input (Notes 1, 3)5.216.0
10mVP-P input (Notes 1, 3)3.514.0
800mVP-P input (Notes 1, 3)1.87.0Deterministic Jitter
1200mVP-P input (Notes 1, 3)1.911.0
Random Jitter20mVP-P < input < 1200mVP-P (Notes 1, 4)0.61.1psRMS
Transition Timetr, tf20% to 80%, differential output (Note 1)2030ps
Data Input ImpedanceSingle ended425058Ω
Data Output-Voltage SwingDifferential signal amplitude between
OUT+ and OUT-190240400mVP-P
Data Output Voltage when
Disabled
Differential signal amplitude
between OUT+ and OUT-0.2550mVP-P
Data Output Common-Mode
Voltage
VCC -mV
Data Output ImpedanceSingle ended425058Ω
Data Output Offset when
DISABLE is High75200mV
Disable Input Current3060µA
DISABLE High VoltageVIH2V
DISABLE Low VoltageVIL0.8V
Disable Response Time20ns
Note 1:Guaranteed by design and characterization.
Note 2:The output signal amplitude at the sensitivity is >.95 ✕the amplitude with large input.
Note 3:Deterministic jitter is measured with K28.5 pattern (0011 1110 1011 0000 0101) at 10.7Gbps. It is the peak-to-peak devia-
tion from the ideal time crossing, measured at the zero-level crossing of the differential output.
Note 4:For a bit-error rate of 10-12, the peak-to-peak random jitter is 14.1 ✕the RMS random jitter.
MAX3971A
+3.3V, 10.7Gbps Limiting Amplifier
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 10mVP-P, AT 10.7Gbps)
MAX3971A toc01
20ps/div
45mV/div23 - 1PRBS
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 5mVP-P, AT 10.3Gbps)
MAX3971A toc02
20ps/div
45mV/div23 - 1PRBS
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 1200mVP-P, AT 10.3Gbps)
MAX3971A toc03
20ps/div
45mV/div23 - 1PRBS
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 800mVP-P, AT 10.7Gbps)
MAX3971A toc04
20ps/div
45mV/div
223 - 1PRBS
OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX3971A toc07
VIN (mVP-P)
OUT
(mV
P-P4321
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
MAX3971A toc05
TEMPERATURE (°C)
SUPPLY CURRENT (mA)604050203010
SMALL-SIGNAL GAIN
MAX3971A toc06
FREQUENCY (GHz)
GAIN (dB)1311124567891023
MAX3971A UGP
RANDOM JITTER vs. INPUT AMPLITUDE
MAX3971A toc08
INPUT AMPLITUDE (mVP-P)
RANDOM JITTER (ps
RMS
3.510,000
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
MAX39971A toc09
INPUT AMPLITUDE (mVP-P)
JITTER (ps
P-P
10001001010,000
10.7Gbps, K28.5,
VCC = +3V, TEMP = 85°C
Typical Operating Characteristics
(VCC= +3.3V, output load = 50Ωto VCC, TA = +25°C, unless otherwise noted.)
MAX3971A
+3.3V, 10.7Gbps Limiting Amplifier
Typical Operating Characteristics (continued)
(VCC= +3.3V, output load = 50Ωto VCC, TA = +25°C, unless otherwise noted.)
DETERMINISTIC JITTER
vs. TEMPERATURE
MAX3971A toc10
AMBIENT TEMPERATURE (°C)
JITTER (ps
P-P605040302010
VIN = 5mV
VIN = 800mV
10.7Gbps with K28.5
INPUT RETURN LOSS (S11)
(VCC = +3.3V)
MAX3971A toc11
FREQUENCY (GHz)
LOSS (dB)87654321
MAX3971A
OUTPUT RETURN LOSS (S22)
(VCC = +3.3V)
MAX3971A toc12
FREQUENCY (GHz)
LOSS (dB)86723451
MAX3971A
OUTPUT NOISE POWER
(INPUT CONNECTED TO 50Ω TO GND)
MAX3971A toc13
TEMPERATURE (°C)
NOISE POWER (dBm)605040302010
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX3971A toc14
FREQUENCY (Hz)
PSRR (dB)
10M1M100k
10k100M
PSRR = -20log ΔVOUT/ΔVCC
INPUT COMMON-MODE REJECTION
RATIO vs. FREQUENCY
MAX3971A toc15
FREQUENCY (Hz)
CMRR (dB)100M10M1M
10010G
CMRR = -20log(VOUT/VIN)
VIN = VIN+ = VIN-
Pin Description
PINNAMEFUNCTIONGNDIN+ Input Ground for Shielding Input Signal IN+. Not connected internally. IN+ Noninverting Input Signal IN- Inverting Input Signal GNDIN- Input Ground for Shielding Input Signal IN-. Not connected internally.
5, 7, 9, 10 N.C. No Connection. Leave unconnected.
6, 8, 11 GND Ground
12, 15 VCC3 Output Circuitry Power Supply
13 OUT- Inverting Output of Amplifier
14 OUT+ Noninverting Output of Amplifier
16 DISABLE When DISABLE is connected to VCC or left floating, outputs are disabled. When DISABLE is
connected to GND, outputs are enabled.
17 VCC2 Power Supply to Circuitry other than Input and Output Circuits
18 CZ+ Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed
Description section.
19 CZ- Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed
Description section.
20 VCC1 Input Circuitry Power Supply EP Exposed Pad. Must be soldered to supply ground for proper electrical and thermal operation.
MAX3971A
+3.3V, 10.7Gbps Limiting Amplifier
Detailed Description and
Applications Information
Figure 1 is a functional diagram of the MAX3971A limit-
ing amplifier. The signal path consists of an input buffer
followed by a gain stage and output amplifier. A feed-
back loop provides offset correction by driving the
average value of the differential output to zero.
Gain Stage and Offset Correction
The limiting amplifier provides approximately 42dB
gain. The large gain makes the amplifier susceptible to
small DC offsets, which cause deterministic jitter. A
low-frequency loop is integrated into the limiting ampli-
fier to reduce output offset, typically to less than 2mV.
The external capacitor (CZ) is required for stability and
to set the low-frequency cutoff for the offset correction
loop. The time constant of the loop is set by the product
of an equivalent 20kΩon-chip resistor and the value of
the off-chip capacitor (CZ). For stable operation, the
minimum value of CZ is 0.01µF. To minimize pattern-
dependent jitter, CZ should be as large as possible.
For 10Gbps ethernet and SONET applications, the typi-
cal value of CZ is 0.1µF. Keep CZ close to the package
to reduce parasitic inductance.
CML Input Circuit
The input buffer is designed to accept CML input sig-
nals such as the output from the MAX3970 transimped-
ance amplifier. An equivalent circuit for the input is
shown in Figure 2. For lowest deterministic jitter in all
operating conditions, AC-coupling capacitors are rec-
ommended on the input.
MAX3971A
CZ-CZ+
LOWPASS
FILTER
OFFSET
CORRECTION
AMP
INPUT
AMPLIFIER
GAIN
42dB
OUTPUT
AMPLIFIER
OUT+
OUT-
IN+
GNDIN+
GNDIN-
IN-
DISABLE
100Ω
Figure 1. Functional Diagram
CML Output Circuit
An equivalent circuit for the output network is shown in
Figure 3. It consists of a pair of 50Ωresistors connect-
ed to VCCdriven by the collectors of an output differen-
tial transistor pair (Q1 and Q2). The differential output
signals are clamped by transistors Q3 and Q4 when
the DISABLE input is high.
DISABLE Function
A logic signal can be applied to the DISABLE pin to
squelch the output signal. When the output is disabled,
an offset is added to the output, preventing the follow-
ing stage from oscillating, if DC-coupled. See Figure 4
for the input stage of the DISABLE function.
MAX3971A
+3.3V, 10.7Gbps Limiting Amplifier
+3.3V
100kΩ
DISABLE
20μA
Figure 4. TTL Input Stage
VCC1
50Ω50Ω
IN+
GNDIN+
GNDIN-
IN-
ESD
STRUCTURES
Figure 2. CML Input Equivalent Circuit
VCC3
50Ω50ΩQ2Q3Q4
OUT+
OUT-
DISABLE
DATA
ESD
STRUCTURES
Figure 3. CML Output Equivalent Circuit
+3.3V
MAX3971A
VCC1VCC2VCC3
0.001μF0.001μF0.001μFSUPPLY FILTER
Figure 5. Power-Supply Filter

Partno	Mfg	Dc	Qty	Available	Descript
MAX3971AUGP	MAXIM	N/a	790	avai	+3.3V, 10.7Gbps Limiting Amplifier