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MAX3892EGH+-MAX3892EGH-TD-MAX3892ETH+-MAX3892ETH+T
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis
General DescriptionThe MAX3892 serializer is ideal for converting 4-bit-
wide, 622Mbps parallel data to 2.5Gbps serial data in
DWDM and SONET/SDH applications. A 4 ✕4-bit FIFO
allows for any static delay between the parallel output
clock and parallel input clock. Delay variation up to a
unit interval (UI) is allowed after reset. A fully integrated
phase-locked loop (PLL) synthesizes an internal
2.5GHz serial clock from a 622MHz, 155.5MHz,
77.8MHz, or 38.9MHz reference clock. A selectable
dual VCO allows excellent jitter performance at both
SONET and forward-error correction (FEC) data rates.
Operating from a single 3.3V supply, this device
accepts low-voltage differential-signal (LVDS) clock and
data inputs for interfacing with high-speed digital circuit-
ry, and delivers current-mode logic (CML) serial data
and clock outputs. A loopback data output is provided
to facilitate system diagnostic testing. The MAX3892 is
available in the extended temperature range (-40°C to
+85°C) in 44-pin QFN and TQFN packages.
ApplicationsSONET/SDH OC-48 Transmission Systems
WDM Transponders
Add/Drop Multiplexers
Dense Digital Cross-Connects
Backplane Interconnects
FeaturesSingle +3.3V Supply455mW Power Consumption1.4psRMSMaximum Jitter Generation4 ✕4-Bit FIFO Input Buffer622Mbps/666Mbps Parallel to 2.5Gbps/2.7Gbps
Serial Conversion622MHz/667MHz or 311MHz/333MHz Clock InputOn-Chip Clock SynthesizerMultiple Clock Reference Frequencies:
(622.08MHz, 155.52MHz, 77.76MHz, 38.88MHz) or
(666.51MHz, 166.63MHz, 83.31MHz, 41.66MHz)LVDS Parallel Clock and Data InputsCML Serial Data and Clock OutputsAdditional CML Output for System Loopback
Testing
MAX3892
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
Ordering Information19-2215; Rev 6; 10/07
EVALUATION KIT
AVAILABLE
PART TEMP
RANGE
PIN-
PACKAGE
PKG
CODE MAX3892EGH -40°C to +85°C44 QFN G4477-3
MAX3892ETH+ -40°C to +85°C44 TQFN T4477-3
PDI0+
PDI0-
PDI3+
PDI3-
RCLK+RCLK-CLKSETFIL
RESET
RATESET
SDO+
SDO-
SCLKO+
SCLKO-
SLBEN
SLBO+
SLBO-
PCLKI+
PCLKI-
PCLKO+
PCLKO-
MODE
FIFOERRORLOL
SONET/SDH
FRAMER
LVPECL
LVDS
LVDS
LVDS
CML
CML
CML
VCCVCO
VCCVCO
LASER
DRIVER
OPTIONAL
FOR
SYSTEM
LOOPBACK
TEST
TTL
THIS SYMBOL REPRESENTS A TRANSMISSION
LINE OF CHARACTERISTIC IMPEDANCE ZO = 50Ω.
SLBPD
MAX3273
MAX3882
VCC
MAX3892
1:4 DESERIALIZER
WITH CDR
100Ω
Typical Application Circuit+Denotes a lead-free package.
MAX3892
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, differential LVDS load = 100Ω±1%, TA= +25°C,
unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage VCC,VCCO, VCCVCO.....................-0.5V to +5V
All Inputs and FIL.......................................-0.5V to (VCC+ 0.5V)
LVDS Output Voltage (PCLKO±)................-0.5V to (VCC+ 0.5V)
CML Output Current (SDO±, SCLKO±, SLBO±)................22mA
Continuous Power Dissipation (TA= +85°C)
44-Pin QFN (derate 25mW/°C above +85°C)............1625mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply CurrentICC(Note 2)138190mA
LVDS INPUT SPECIFICATIONS (PDI[3..0]±, PCLKI±)Input Voltage RangeVI02400mV
Differential Input Voltage|VID|100mV
Input Common-Mode CurrentLVDS input VOS = 1.2V61µA
Threshold Hysteresis45mV
Differential Input ResistanceRIN83100117Ω
LVPECL INPUT SPECIFICATIONS (RCLK±)Input High VoltageVIHVCC -
VCC -
0.88V
Input Low VoltageVILVCC -
VCC -
1.48V
Input Bias VoltageVCC - 1.3V
Single-Ended Input Resistance>1.0kΩ
Differential Input Voltage Swing3001900mVP-P
LVDS OUTPUT SPECIFICATIONS (PCLKO±)Output High VoltageVOH1.475V
Output Low VoltageVOL0.925V
Differential Output Voltage|VOD|250400mV
Change in Magnitude of
Differential Output Voltage for
Complementary States
Δ|VOD|25mV
Offset Output Voltage1.1251.275V
Change in Magnitude of Output
Offset Voltage for Complementary
States
Δ|VOS|25mV
MAX3892
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, differential LVDS loads = 100Ω±1%, CML loads =
50Ω±1%, TA= +25°C, unless otherwise noted.) (Note 3)
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, differential LVDS load = 100Ω±1%, TA= +25°C,
unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDifferential Output Resistance80140Ω
Output CurrentShorted together12mA
Output CurrentShorted to ground40mA
CML OUTPUT SPECIFICATIONS (SDO±, SCLKO±, SLBO±)Differential OutputRL = 100Ω differential6408001000mVP-P
Differential Output Resistance83100117Ω
Output Common-Mode VoltageRL = 50Ω to VCCVCC - 0.2V
LVTTL SPECIFICATIONS (RESET, RATESET, SLBEN, SLBPD FIFOERROR, LOL)Input High VoltageVIH2.0V
Input Low VoltageVIL0.8V
Input High CurrentIIH-30+10µA
Input Low CurrentIIL-50+10µA
Output High VoltageVOHIOH = 20µA2.4VCCV
Output Low VoltageVOLIOL = 1mA0.4V
PROGRAMMING INPUTS (CLKSET, MODE)Input CurrentInput = 0 or VCC-500+500µA
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PARALLEL INPUT SPECIFICATIONS (PDI±, PCLKI±)RATESET = GND622Parallel Input Data RateRATESET = VCC666Mbps
MODE = OPEN or VCC622Parallel Input Clock RateMODE = SHORT or 30kΩ to GND311MHz
Parallel Input Setup TimetSU(Note 4)-94ps
Parallel Input Hold TimetH(Note 4)300ps
PARALLEL CLOCK OUTPUT SPECIFICATIONS (PCLKO±)Parallel Clock Output Rise/Fall
Timetr, tf20% to 80%100200ps
Parallel Clock Output Duty Cycle4654%
SERIAL OUTPUT SPECIFICATIONS (SDO±, SCLKO±)RATESET = GND2.488Serial Output Data RateRATESET = VCC2.666Gbps
Serial Data Output Rise/Fall Timetr, tf20% to 80%80ps
Serial Output Clock to Data DelaytCLK-Q(Note 5)-2525ps
MAX3892
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
Note 1:Specifications at -40°C are guaranteed by design and characterization.
Note 2:Measured with SLBO/CLK622 and SCLK outputs disabled and CML outputs open.
Note 3:AC characteristics are guaranteed by design and characterization.
Note 4:In 622MHz clock mode, the parallel data is clocked in by the rising edge of the 622MHz/666MHz parallel clock input. In the
311MHz clock mode, the parallel data is clocked in on both the rising and falling edges of the clock. The parallel input
setup and hold time increases by 60ps if the duty cycle is between 48% to 52% in 311MHz mode (Figure 1).
Note 5:Relative to the falling edge of the SCLKO.
Note 6:Measurement bandwidth is BW = 12kHz to 20MHz.
Note 7:Measured with 00001111 pattern, RCLK to PCLKI/PDI[3:0] phase approximately 40ps. See the Jitter Generation vs. RCLK to
PCLK/PDI[3:0] Phaseplot in the Typical Operating Characteristicssection.
Note 8:Deterministic jitter includes pattern-dependent jitter and pulse-width distortion. Measured using a 27- 1 PRBS pattern with
96 consecutive identical digits.
AC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, differential LVDS loads = 100Ω±1%, CML loads =
50Ω±1%, TA= +25°C, unless otherwise noted.) (Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSerial Clock Output Jitter
GenerationJG(Notes 6 and 7)1.01.4psRMS
Serial Data Output Random JitterRJ(Note 7)1.4psRMS
Serial Data Output Deterministic
JitterDJ(Note 8)19psP-P
REFERENCE CLOCK INPUT SPECIFICATIONS (RCLK)Reference Clock Frequency
Tolerance
±100ppm
Reference Clock Input Duty Cycle3070%
RESET INPUTS (RESET)Minimum Pulse Width of FIFO
ResetUI is PCLKO period4UI
Tolerated Drift Between PCLKI
and PCLKO After ResetUI is PCLKO period±1UI
MAX3892
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock SynthesisSUPPLY CURRENT vs. TEMPERATURE
MAX3892 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
50ps/div
ELECTRICAL EYE DIAGRAMMAX3892 toc02
PATTERN 213-1 PRBS
DATA RATE = 2.5Gbps1k10k
POWER-SUPPLY JITTER GENERATION
vs. RIPPLE FREQUENCYMAX3892 toc03
RIPPLE FREQUENCY (kHz)
JITTER GENERATION (ps
P-P
100mVP-P
50mVP-P
JITTER GENERATION vs. POWER SUPPLY
NOISE AMPLITUDE (BW = 2MHz)
MAX3892 toc04
NOISE AMPLITUDE (VP-P)
JITTER GENERATION (ps
RMS
JITTER GENERATION
vs. RCLK to PCLKI/PDI[3:0] PHASEMAX3892 toc05
RCLK TO PCLKI/PDI[3:0] PHASE (ps)
JITTER GENERATION (ps
RMS
PATTERN = 00001111
5ps/div
SERIAL-DATA OUTPUT JITTERMAX3892 toc06
TOTAL WIDEBAND RMS JITTER = 1.3ps
PEAK-TO-PEAK JITTER = 15.8ps
fRCLK = 622MHz
Typical Operating Characteristics(VCC= +3.3V, CML loads AC-coupled to 50Ω±1%, TA= +25°C, unless otherwise noted.)
Pin Description
PINNAMEFUNCTION1, 16, 22, 27,
33, 44GNDSupply Ground
2, 5, 8, 11VCCOSupply Voltage for Outputs +3.3V. Add bypass capacitors near these pins before connecting to
the VCC power plane.SCLKO-Negative Serial Clock Output, CML 2.488GHz or 2.666GHzSCLKO+Positive Serial Clock Output, CML 2.488GHz or 2.666GHzSDO-Negative Serial Data Output, CML 2.488Gbps or 2.666GbpsSDO+Positive Serial Data Output, CML 2.488Gbps or 2.666Gbps
MAX3892
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
Pin Description (continued)
PINNAMEFUNCTIONSLBO-Negative System Loop-Back Output or 622MHz/666MHz Clock Output. Select CML data or clock
as shown in Table 1.SLBO+Positive System Loop-Back Output or 622MHz/666MHz Clock Output. Select CML data or clock as
shown in Table 1.SLBPDSystem Loopback Power Down, TTL Input. SLPD = high activates the system loopback output
driver; SLBPD = low powers down the loop-back output driver.SLBENSystem Loop-Back Enable Input, TTL Input. SLBEN = high activates the system loop-back output;
SLBEN = low activates the 622MHz/666MHz reference clock output.RESETFIFO Reset, TTL Input. An active-high reset recenters the FIFO to tolerate maximum skew between
PCLKI and PCLKO.FIFOERRORFIFO Error Indicator, TTL Output. Active high when the read/write clocks access the same FIFO
address. This signal may be used to control RESET.
17, 28, 36, 43VCCSupply Voltage, +3.3VLOLLoss of Lock, TTL Output. An active low indicates that the VCO and reference frequency differ by
500ppm.MODE
Clock Control Input:
MODE = GND; fPCLKI = 311.04MHz/333MHz with SCLKO active
MODE = 30kΩ to GND; fPCLKI = 311.04MHz/333MHz with SCLKO off
MODE = OPEN (float); fPCLKI = 622.08MHz/666MHz with SCLKO off
MODE = VCC; fPCLKI = 622.08MHz/666MHz with SCLKO activePCLKI+Positive Parallel Clock, LVDS Input. Data is written to the input register on the clock rising edge in
622Mbps mode and on both rising and falling edges in 311Mbps mode (Figure 1).PCLKI-Negative Parallel Clock, LVDS Input (Figure 1).
23, 25, 29, 31PDI3+ to
PDI0+Positive Data Inputs, LVDS (622Mbps or 666Mbps)
24, 26, 30, 32PDI3- to
PDI0-Negative Data Inputs, LVDS (622Mbps or 666Mbps)PCLKO+Positive Parallel Clock Output, LVDS. This clock may be 622.08MHz or 666MHz.PCLKO-Negative Parallel Clock Output, LVDS. This clock may be 622.08MHz or 666MHz.RCLK+Positive Reference Clock Input, LVPECLRCLK-Negative Reference Clock Input, LVPECLCLKSET
Reference Clock Rate Programming Pin:
CLKSET = VCC; RCLK = 622.08MHz/666MHz
CLKSET = OPEN (float); RCLK = 155.52MHz/167MHz
CLKSET = 30kΩ to GND; RCLK = 77.76MHz/83.3MHz
CLKSET = GND; RCLK = 38.88MHz/41.6MHzRATESETData Rate Select, TTL Input. RATESET = high for 2.666Gbps, RATESET = low for 2.488Gbps.VCCVCOSupply Voltage for VCO +3.3V. Add bypass capacitors near this pin before connecting to the VCC
power plane.FILPLL Capacitor Pin. Connect a 0.1µF capacitor from this pin to VCCVCO.Exposed
PaddleThe exposed paddle must be soldered to ground for proper thermal and electrical operation.
