MAX3890ECB ,+3.3V / 2.5Gbps / SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS InputsApplicationsOrdering Information2.5Gbps SDH/SONET Transmission SystemsPART TEMP. RANGE PIN-PACKAGE2 ..
MAX3892EGH+ ,+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock SynthesisApplications Ordering InformationSONET/SDH OC-48 Transmission SystemsTEMP PIN- PKG PART WDM Transpo ..
MAX3892EGH-TD ,+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock SynthesisELECTRICAL CHARACTERISTICS (continued)(V = +3.0V to +3.6V, T = -40°C to +85°C. Typical values are a ..
MAX3892ETH+ ,+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock SynthesisFeaturesThe MAX3892 serializer is ideal for converting 4-bit- ♦ Single +3.3V Supplywide, 622Mbps pa ..
MAX3892ETH+ ,+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesisapplications. A 4 ✕ 4-bit FIFO♦ 1.4ps Maximum Jitter Generationallows for any static delay between ..
MAX3892ETH+T ,+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock SynthesisELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V = +3.3V, ..
MAX742CWP ,Switch-Mode Regulator with +5V to 【12V or 【15V Dual OutputELECTRICAL CHARACTERISTICS(Circuit of Figure 2, V+ = 5V, 100/200 = 12/15 = 0V; T = T to T , unless ..
MAX742CWP ,Switch-Mode Regulator with +5V to 【12V or 【15V Dual OutputELECTRICAL CHARACTERISTICS(Circuit of Figure 2, +4.5V < V+ < +5.5V.)PARAMETER SYMBOL CONDITIONS MIN ..
MAX742CWP+ ,Switch-Mode Regulator with 5V to ±12 or ±15V Dual-OutputFeatures' Specs Guaranteed for In-Circuit PerformanceThe MAX742 DC-DC converter is a controller for ..
MAX742CWP-T ,Switch-Mode Regulator with 5V to ±12 or ±15V Dual-OutputBlock DiagramDistributed Power Systems+5VComputer PeripheralsINPUTMAX742CC-__________________Pin Co ..
MAX742EPP ,Switch-Mode Regulator with +5V to 【12V or 【15V Dual OutputApplications* Contact factory for dice specificationsDC-DC Converter Module Replacement__________Si ..
MAX742EWP ,Switch-Mode Regulator with +5V to 【12V or 【15V Dual OutputFeatures' Specs Guaranteed for In-Circuit PerformanceThe MAX742 DC-DC converter is a controller for ..
MAX3890ECB
+3.3V / 2.5Gbps / SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs
General DescriptionThe MAX3890 serializer is ideal for converting 16-bit-
wide, 155Mbps parallel data to 2.5Gbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts low-voltage
differential-signal (LVDS) clock and data inputs for
interfacing with high-speed digital circuitry, and deliv-
ers PECL serial data and clock outputs. A fully integrat-
ed PLL synthesizes an internal 2.5GHz serial clock from
a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz ref-
erence clock. A loopback data output is provided to
facilitate system diagnostic testing.
The MAX3890 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP exposed-
paddle (EP) package.
Applications2.5Gbps SDH/SONET Transmission Systems
2.5Gbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross-Connects
ATM Backplanes
FeaturesSingle +3.3V Supply495mW Power ConsumptionExceeds ANSI, ITU, and Bellcore Specifications 155Mbps (16-bit wide) Parallel to 2.5Gbps Serial
ConversionClock Synthesis for 2.5GbpsMultiple Clock Reference Frequencies
(155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)LVDS Parallel Clock and Data InputsAdditional High-Speed Output for System
Loopback Testing
MAX3890
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputsypical Operating Circuit
Pin Configuration appears at end of data sheet.*EP = Exposed Paddle
MAX3890
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, differential LVDS loads = 100W±1%, PECL loads = 50W±1% to (VCC - 2V), CML loads = 50W±1% to VCC,= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Terminal Voltage (with respect to GND)
VCC.......................................................................-0.5V to +5V
All Inputs, FIL+, FIL-...............................-0.5V to (VCC+ 0.5V)
Output Current
LVDS Outputs (PCLKO±)................................................10mA
PECL Outputs (SDO±, SCLKO±)....................................50mA
CML Outputs (SLBO±)....................................................15mA
Continuous Power Dissipation (TA= +85°C)
TQFP-EP (derate 44.8mW/°C above +85°C)......................1W
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX3890
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
Note 1:AC characteristics guaranteed by design and characterization.
Note 2:Setup and hold times are relative to the rising edge of PCLKI+, measured by applying a 155.52MHz differential parallel
clock with rise/fall time = 1ns (20% to 80%). See Figure 2.
Note 3:For fRCLK = 38.88MHz, the minimum reference clock amplitude is ‡ 200mV.
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, differential LVDS load = 100W±1%, PECL loads = 50W ±1% to (VCC - 2V), CML loads = 50Ω±1% to VCC,= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.) (Note 1)
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, differential LVDS loads = 100W±1%, PECL loads = 50W±1% to (VCC - 2V), CML loads = 50W±1% to VCC,= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.)
MAX3890
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS InputsSUPPLY CURRENT
vs. TEMPERATURE
MAX3890-01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
5ps/div
SERIAL-DATA OUTPUT JITTERMAX3890-03
TOTAL WIDEBAND RMS JITTER = 2.155ps,
PEAK-TO-PEAK JITTER = 15.7ps
50ps/div
SERIAL-DATA OUTPUT EYE DIAGRAMMAX3890-02
OUTPUT JITTER GENERATION
vs. RCLK AMPLITUDE
MAX3890 toc04
RCLK AMPLITUDE (mV)
OUTPUT JITTER GENERATION (ps)
Typical Operating Characteristics(VCC= +3.3V, PECL loads = 50Ω±1%, TA= +25°C, unless otherwise noted.)
MAX3890
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
Pin Description
MAX3890
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________Detailed DescriptionThe MAX3890 converts 16-bit-wide, 155Mbps data to
2.5Gbps serial data (Figure 1). It is composed of a 16-
bit parallel input register, a 16-bit shift register, control
and timing logic, PECL output buffers, LVDS input/out-
put buffers, and a frequency-synthesizing PLL (consist-
ing of a phase/frequency detector, loop filter/amplifier,
voltage-controlled oscillator (VCO), and prescaler).
The PLL synthesizes an internal 2.5Gbps reference
used to clock the output shift register. This clock is
generated by locking onto the external 155.52MHz,
77.76MHz, 51.84MHz, or 38.88MHz reference-clock
signal (RCLK).
The incoming parallel data is clocked into the
MAX3890 on the rising transition of the parallel-clock-
input signal (PCLKI). Proper operation is ensured if the
parallel input register is latched within a window of time
(tSKEW) that is defined with respect to the parallel-
clock-output signal (PCLKO). PCLKO is the synthe-
sized 2.5Gbps internal serial-clock signal divided by
16. The allowable PCLKO-to-PCLKI skew is 0 to +4ns.
This defines a timing window after the PCLKO rising
edge, during which a PCLKI rising edge may occur
(Figure 2).
System LoopbackThe MAX3890 is designed to allow system loopback test-
ing. The loopback outputs (SLBO+, SLBO-) of the
MAX3890 may be directly connected to the loopback
inputs of a deserializer (such as the MAX3880) for system
diagnostics. To enable the SLBO outputs, apply a TTL
logic-high signal to the SOS input. Note:The same signal
that controls the SOS enable input may also be used to
control the SIS enable input on the MAX3880.
