MAX3885ECB+ Fast Delivery |IC PHOENIX CO.,LIMITED

MAX3885ECB+ ,+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS OutputsApplicationsOrdering Information2.488Gbps SDH/SONET Transmission SystemsPART TEMP RANGE PIN-PACKAGE ..
MAX3885ECB+ ,+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS OutputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, differential loads = 100Ω±1%, T = -40°C to +85°C, un ..
MAX388CPN ,High-Voltage, Fault-Protected Analog MultiplexersGeneral Description The MAX388 8-channel single-ended (I-ot-to and the W389 4-channel different ..
MAX388CWG ,High-Voltage, Fault-Protected Analog MultiplexersELECTRICAL CHARACTERISTICS (continued) (V+ " 15v. v- = -15v. GND = WA = OV, AB = +2.4v, TA = +25'C ..
MAX388EPN ,High-Voltage, Fault-Protected Analog MultiplexersELECTRICAL CHARACTERISTICS (continued) (V+ " 15v. v- = -15v. GND = WA = OV, AB = +2.4v, TA = +25'C ..
MAX388EWG ,High-Voltage, Fault-Protected Analog MultiplexersELECTRICAL CHARACTERISTICS (V+ = 15V, V- = -15V, GND = WA = OV, Ag = +2.4V. TA = +25°C. unless oth ..
MAX7428EKA+T ,Standard Definition Video Reconstruction Filters and BuffersApplicationsMSPB is a trademark of Maxim Integrated Products, Inc.Set-Top BoxesµMAX is a registered ..
MAX7428EKA-T ,Standard Definition Video Reconstruction Filters and BuffersELECTRICAL CHARACTERISTICS(V = +5V ±10%, R = 300kΩ ±1%, C = 0.1µF, C = (1nF to 1µF) ±1%, C = 0 to 2 ..
MAX7428EKA-T ,Standard Definition Video Reconstruction Filters and BuffersFeaturesThe MAX7428/MAX7430/MAX7432 filters are low-cost, Ideal for CVBS, Y/C (S-Video), and RGB ..
MAX742CPP ,Switch-Mode Regulator with +5V to 【12V or 【15V Dual Outputfeatures undervoltage lockout, thermal shut-down, and programmable soft-start. MAX742C/D 0°C to +70 ..
MAX742CWP ,Switch-Mode Regulator with +5V to 【12V or 【15V Dual OutputBlock DiagramDistributed Power Systems+5VComputer PeripheralsINPUTMAX742CC-__________________Pin Co ..
MAX742CWP ,Switch-Mode Regulator with +5V to 【12V or 【15V Dual OutputELECTRICAL CHARACTERISTICS(Circuit of Figure 2, V+ = 5V, 100/200 = 12/15 = 0V; T = T to T , unless ..

MAX3885ECB+
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs
General Description
The MAX3885 deserializer is ideal for converting
2.488Gbps serial data to 16-bit wide, 155Mbps parallel
data in SDH/SONET applications. Operating from a sin-
gle +3.3V supply, this device accepts PECL serial
clock and data inputs, and delivers low-voltage differ-
ential-signal (LVDS) clock and data outputs for interfac-
ing with high-speed digital circuitry. It also provides an
LVDS synchronization input that enables data realign-
ment and reframing. The MAX3885 is available in the
extended temperature range (-40°C to +85°C) in a 64-
pin TQFP package.
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross Connects
Features♦Single +3.3V Supply♦2.488Gbps Serial to 155Mbps Parallel Conversion♦660mW Operating Power♦LVDS Data Outputs and Synchronization Inputs♦Self-Biasing PECL Inputs Ease AC Coupling♦Synchronization Inputs for Data Realignment and
Reframing
MAX3885
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
19-4767; Rev 4; 12/07
Pin Configuration appears at end of data sheet.
Ordering Informationypical Operating Circuit
MAX3875
MAX3885
DATA
AND
CLOCK
RECOVERY
SERIAL DATA
INPUTS
OVERHEAD
TERMINATION
100Ω*
100Ω*
100Ω*
VCC = +3.3V
PD15+
PD15-
SD+
SD-
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.
VCC
GND
133Ω133Ω
86.6Ω86.6Ω
VCC = +3.3V
VCC = +3.3V
133Ω133Ω
86.6Ω86.6Ω
VCC = +3.3V
SCLK+
SCLK-
PD0+
PD0-
PCLK+
PCLK-
SYNC+
SYNC-
PART TEMP RANGE PIN-PACKAGE
MAX3885ECB-40°C to +85°C 64 TQFP
MAX3885ECB+ -40°C to +85°C 64 TQFP
+Denotes a lead-free package.
EVALUATION KITAVAILABLE
MAX3885
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Positive Supply Voltage (VCC)...............................-0.5V to +7.0V
Input Voltage Level (all inputs)...................-0.5V to (VCC+ 0.5V)
Output Current LVDS outputs.............................................10mA
Continuous Power Dissipation (TA= +85°C)
TQFP (derate 24mW/°C above +85°C).......................1000mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, differential loads = 100Ω±1%, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V,= +25°C.)
Figure 1
Common-mode voltage = 50mV
Differential input voltage = 100mV
VIN= VIH(MAX)
VIN= VIL(MIN)
CONDITIONS±2.5±10ΔRO
Change in Magnitude of Single-
Ended Output Resistance for
Complementary Outputs4095140ROSingle-Ended Output Resistance±25ΔVOS
Change in Magnitude of Output
Offset Voltage for Complementary
States1.1251.275VOSOutput Offset Voltage±25ΔVOD
Change in Magnitude of Differential
Output Voltage for Complementary
States250400VODDifferential Output Voltage0.925VOLOutput Low Voltage1.475VOHOutput High VoltageVCC- 1.16VCC- 0.88VIHInput High Voltage200280ICCSupply Current85100115RINDifferential Input Resistance78VHYSTThreshold Hysteresis-100100VIDTHDifferential Input Threshold02.4VIInput Voltage RangeVCC- 1.81VCC- 1.48VILInput Low Voltage-900900IIHInput High Current-900900IILInput Low Current
UNITSMINTYPMAXSYMBOLPARAMETER
PECL INPUTS (SD+/-, SCLK+/-)
LVDS INPUTS AND OUTPUTS (SYNC+/-, PCLK+/-, PD_+/-)
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential loads = 100Ω±1%, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V,= +25°C.) (Note 1, Figure 4)
CONDITIONS100tHSerial Data Hold Time100tSU
GHz2.488fSCLKMaximum Serial Clock Frequency
Serial Data Setup Time200450900tCLK-QParallel Clock-to-Data Output Delay
UNITSMINTYPMAXSYMBOLPARAMETER
MAX3885
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
MAXIMUM SERIAL CLOCK FREQUENCY
vs. TEMPERATURE
MAX3885-01
TEMPERATURE (°C)
MAX SERIAL CLOCK FREQUENCY (GHz)
VCC = 3.6V
VCC = 3V
SERIAL DATA-SETUP TIME
vs. TEMPERATURE
MAX3885-02
TEMPERATURE (°C)
SERIAL DATA-SETUP TIME (ps)
SERIAL DATA-HOLD TIME
vs. TEMPERATURE
MAX3885-03
TEMPERATURE (°C)
SERIAL DATA-HOLD TIME (ps)
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
MAX3885-05
TEMPERATURE (°C)
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
Typical Operating Characteristics
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3885-04
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
VCC = 3.6V
VCC = 3V
MAX3885
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
NAMEFUNCTION
1, 2, 8, 16, 17,
24, 32, 33, 41,
48, 49, 57, 64
GNDGround
3, 5, 7, 9, 11,
13, 25, 34, 42,
47, 56
VCC+3.3V Supply Voltage
PINSD+Serial Data Noninverting PECL Input. Data is clocked on the SCLK signal’s positive transi-
tion.SD-Serial Data Inverting PECL Input. Data is clocked on the SCLK signal’s positive transition.SYNC+Synchronizing Pulse Noninverting LVDS Input. Pulse the SYNC signal high for at least four
SCLK periods to shift the data alignment by dropping one bit.SYNC-Synchronizing Pulse Inverting LVDS Input. Pulse the SYNC signal high for at least four SCLK
periods to shift the data alignment by dropping one bit.SCLK-Serial Clock Inverting PECL InputSCLK+Serial Clock Noninverting PECL Input
21, 23, 27, 29,
31, 36, 38, 40,
44, 46, 51, 53,
55, 59, 61, 63
PD0+ to PD15+Parallel Data Noninverting LVDS Outputs. Data is updated on the negative transition of the
PCLK signal.
20, 22, 26, 28,
30, 35, 37, 39,
43, 45, 50, 52,
54, 58, 60, 62
PD0- to PD15-Parallel Data Inverting LVDS Outputs. Data is updated on the negative transition of the PCLK
signal.PCLK+Parallel Clock Noninverting LVDS OutputPCLK-Parallel Clock Inverting LVDS Output
Pin Description
SINGLE-ENDED OUTPUT|VOD|
VPD-VOH
VOS
VOD, P - P = VPD+ - VPD-
-VOD
+VOD0V (DIFF.)
VOLVPD+
DIFFERENTIAL OUTPUT
VPD+ - VPD-
PD+
RL = 100ΩVOD
PD-
MAX3885
Detailed Description
The MAX3885 deserializer uses a 16-bit shift register,
16-bit parallel output register, 4-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 2.488Gbps serial data to
16-bit wide, 155Mbps parallel data (Figure 2). The input
shift register continuously clocks incoming data on the
positive transition of the serial clock (SCLK) input sig-
nal. The 4-bit counter generates a parallel-output clock
(PCLK) by dividing the serial-clock frequency by 16.
The PCLK signal clocks the parallel-output register.
During normal operation, the counter divides the SCLK
frequency by 16, causing the output register to latch
every 16 bits of incoming serial data. The synchroniza-
tion inputs (SYNC+, SYNC-) realign and reframe data.
When the SYNC signal is pulsed high for at least four
SCLK cycles, the parallel output data is delayed by one
SCLK cycle. This realignment is guaranteed to occur
within two complete PCLK cycles of the SYNC signal’s
positive transition. As a result, the first incoming bit of
data during that PCLK cycle is dropped, shifting the
alignment between PCLK and data by one bit. See
Figure 3 for the timing diagram and Figure 4 for the tim-
ing parameters diagram.
Low-Voltage Differential-Signal (LVDS)
Inputs and Outputs
The MAX3885 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 500mVp-p to 800mVp-p dif-
ferential low-voltage swings to achieve fast transition
times, minimize power dissipation, and improve noise
immunity. The parallel clock and data LVDS outputs
(PCLK+, PCLK-, PD_+, PD_-) require 100Ωdifferential
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
16-BITSHIFT
REGISTER
16-BITPARALLEL
OUTPUT
REGISTER
4-BIT
COUNTER
LVDSPECL
PECL
LVDS
LVDS
LVDS
LVDS
PD15+
PD15-
PD1+
PD1-
PD0+
PD0-
PCLK+
PCLK-
SD+
SD-
SCLK+
SCLK-
SYNC+
SYNC-100Ω
MAX3885
Figure 2. Functional Diagram
SCLK
SYNC
PCLK
D15D14D13
D16D32D48
ONE BIT HAS SLIPPED
IN THIS TIME SLICE
D65(LSB) PD0D17D33D49D66PD1
D15(MSB)
TRANSMITTED FIRST
D31D47D64D80PD15•
Figure 3. Timing Diagram
MAX3885
DC termination between the inverting and noninverting
outputs for proper operation. Do not terminate these
outputs to ground. The synchronization LVDS inputs
(SYNC+, SYNC-) are internally terminated with 100Ω
differential input resistance and, therefore, do not
require external termination.
PECL Inputs
Because of the self-biasing resistor networks, the serial
data and clock PECL inputs (SD+, SD-, SCLK+, SCLK-)
require 53Ωtermination to VCC- 2V when interfacing
with a PECL source (see Alternative PECL Input
Termination). This results in an equivalent input resis-
tance of 50Ω.
Applications Information
Alternative PECL Input Termination
Figure 5 shows alternative PECL input-termination
methods. Use Thevenin-equivalent termination when a
VCC- 2V termination voltage is not available. When
interfacing with an ECL-output device, the MAX3885’s
internal self-biasing allows easy ECL AC-coupling ter-
mination.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3885 high-speed inputs and out-
puts.
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
MAX3885
PECL
INPUTS
ZO = 50Ω
ZO = 50Ω
133Ω
86.6Ω
133Ω
86.6Ω
+3.3V
MAX3885
PECL
INPUTS
ZO = 50Ω
53Ω
ZO = 50Ω-2V
53Ω
-2V
THEVENIN-EQUIVALENT TERMINATION
ECL AC-COUPLING TERMINATION
Figure 5. Alternative PECL Input Termination
SCLK
PCLK
PD0–PD15
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
tSCLK = 1 / fSCLK
tSU
tCLK-Q
Figure 4. Timing Parameters

Partno	Mfg	Dc	Qty	Available	Descript
MAX3885ECB+ \|MAX3885ECB	MAXIM	N/a	10	avai	+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs
MAX3885ECB+ \|MAX3885ECB	MAX	N/a	58	avai	+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs