MAX3880ECB ,+3.3V, 2.488Gbps, SDH/SONET 1:16 deserializer with clock recovery.Applications2.488Gbps SDH/SONET Transmission SystemsPin Configuration appears at end of data sheet. ..
MAX3880ECB+D ,+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock RecoveryApplications*Exposed pad2.488Gbps SDH/SONET Transmission Systems+Denotes lead-free package.Add/Drop ..
MAX3882AETX+ ,2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting AmplifierApplications Ordering InformationSDH/SONET Receivers and RegeneratorsPART TEMP RANGE PIN-PACKAGE MA ..
MAX3885ECB+ ,+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS OutputsApplicationsOrdering Information2.488Gbps SDH/SONET Transmission SystemsPART TEMP RANGE PIN-PACKAGE ..
MAX3885ECB+ ,+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS OutputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, differential loads = 100Ω±1%, T = -40°C to +85°C, un ..
MAX388CPN ,High-Voltage, Fault-Protected Analog MultiplexersGeneral Description
The MAX388 8-channel single-ended (I-ot-to and the
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MAX7428EKA ,Standard Definition Video Reconstruction Filters and BuffersELECTRICAL CHARACTERISTICS(V = +5V ±10%, R = 300kΩ ±1%, C = 0.1µF, C = (1nF to 1µF) ±1%, C = 0 to 2 ..
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MAX7428EKA-T ,Standard Definition Video Reconstruction Filters and BuffersELECTRICAL CHARACTERISTICS(V = +5V ±10%, R = 300kΩ ±1%, C = 0.1µF, C = (1nF to 1µF) ±1%, C = 0 to 2 ..
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MAX742CPP ,Switch-Mode Regulator with +5V to 【12V or 【15V Dual Outputfeatures undervoltage lockout, thermal shut-down, and programmable soft-start. MAX742C/D 0°C to +70 ..
MAX3880ECB
+3.3V, 2.488Gbps, SDH/SONET 1:16 deserializer with clock recovery.
General DescriptionThe MAX3880 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers low-
voltage differential-signal (LVDS) parallel clock and
data outputs for interfacing with digital circuitry.
The MAX3880 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3880’s jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor and LVDS synchronization
inputs that enable data realignment and reframing.
The MAX3880 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP (exposed
pad) package.
Applications2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross-Connects
FeaturesSingle +3.3V Supply910mW Operating PowerFully Integrated Clock Recovery and Data
RetimingExceeds ANSI, ITU, and Bellcore SpecificationsAdditional High-Speed Input Facilitates System
Loopback Diagnostic Testing2.488Gbps Serial to 155Mbps Parallel ConversionLVDS Data Outputs and Synchronization InputsTolerates >2000 Consecutive Identical DigitsLoss-of-Lock Indicator
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Typical Application Circuit19-1467; Rev 1; 12/99
Ordering Information*Exposed pad
Pin Configuration appears at end of data sheet.
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, differential loads = 100Ω±1%, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC= +3.3V, TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Positive Supply Voltage (VCC)...............................-0.5V to +7.0V
Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-,
SYNC+, SYNC-)...........................(VCC- 0.5V) to (VCC+ 0.5V)
Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA
Voltage at LOL, SIS, PHADJ+, PHADJ-,
FIL+, FIL-.................................................-0.5V to (VCC+ 0.5V)
Output Current LVDS Outputs............................................10mA
Continuous Power Dissipation (TA= +85°C)
TQFP (derate 33.3mW/°C above +85°C).......................1.44W
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, differential loads = 100Ω±1%, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC= +3.3V, TA= +25°C.) (Note 1)
Note 1:AC characteristics are guaranteed by design and characterization.
Note 2:At jitter frequencies <70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency
jitter tolerance outperforms the instrument’s measurement capability.
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery1,000100
JITTER TOLERANCE vs. INPUT VOLTAGEMAX3880-04
INPUT VOLTAGE (mVp-p)
JITTER TOLERANCE (UIp-p)
BIT ERROR RATE vs. INPUT VOLTAGE
MAX3880-05
INPUT VOLTAGE (mVp-p)
BIT ERROR RATE
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
MAX3880-06
TEMPERATURE (°C)
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
Typical Operating Characteristics(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Pin Description
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Detailed DescriptionThe MAX3880 deserializer with clock recovery converts
2.488Gbps serial data to 16-bit-wide, 155Mbps parallel
data. The device combines a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
16-bit demultiplexer, clock divider, and LVDS output
buffer (Figure 3). The PLL consists of a phase/frequen-
cy detector (PFD), a loop filter, and a voltage-controlled
oscillator (VCO). The MAX3880 is designed to deliver
the best combination of jitter performance and power
dissipation by using a fully differential signal architec-
ture and low-noise design techniques. The PLL recov-
ers the serial clock from the serial input data stream.
The demultiplexer generates a 16-bit-wide 155Mbps
parallel data output.
The synchronization inputs (SYNC+, SYNC-) realign the
output data word. Realignment is guaranteed to occur
within two complete PCLK cycles of the SYNC signal’s
positive transition. During synchronization, the first
incoming bit of data during that PCLK cycle is
