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MAX3880ECB ,+3.3V, 2.488Gbps, SDH/SONET 1:16 deserializer with clock recovery.Applications2.488Gbps SDH/SONET Transmission SystemsPin Configuration appears at end of data sheet. ..
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MAX3885ECB+ ,+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS OutputsApplicationsOrdering Information2.488Gbps SDH/SONET Transmission SystemsPART TEMP RANGE PIN-PACKAGE ..
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MAX7428EKA ,Standard Definition Video Reconstruction Filters and BuffersELECTRICAL CHARACTERISTICS(V = +5V ±10%, R = 300kΩ ±1%, C = 0.1µF, C = (1nF to 1µF) ±1%, C = 0 to 2 ..
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MAX3875EHJ
2.5Gbps / Low-Power / #.3V Clock Recovery and Data Retiming IC
General DescriptionThe MAX3875 is a compact, low-power clock recovery
and data retiming IC for 2.488Gbps SDH/SONET appli-
cations. The fully integrated phase-locked loop recov-
ers a synchronous clock signal from the serial NRZ
data input, which is retimed by the recovered clock.
Differential PECL-compatible outputs are provided for
both clock and data signals, and an additional
2.488Gbps serial input is available for system loopback
diagnostic testing. The device also includes a TTL-
compatible loss-of-lock (LOL) monitor.
The MAX3875 is designed for both section-regenerator
and terminal-receiver applications in OC-48/STM-16
transmission systems. Its jitter performance exceeds all
of the SONET/SDH specifications.
This device operates from a single +3.3V to +5.0V supply
over a -40°C to +85°C temperature range. The typical
power consumption is only 400mW with a +3.3V supply. It is
available in a 32-pin TQFP package, as well as in die form.
ApplicationsSDH/SONET Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
2.488Gbps ATM Receiver
Digital Video Transmission
SDH/SONET Test Equipment
FeaturesExceeds ANSI, ITU, and Bellcore SONET/SDH
Regenerator Specifications400mW Power Dissipation (at +3.3V)Clock Jitter Generation: 0.003UIRMSSingle +3.3V or +5V Power SupplyFully Integrated Clock Recovery and Data RetimingAdditional High-Speed Input Facilitates System
Loopback Diagnostic TestingTolerates >2000 Consecutive Identical DigitsLoss-of-Lock IndicatorDifferential PECL-Compatible Data and Clock
Outputs
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming ICypical Application Circuit19-4789; Rev 0; 10/98
Ordering InformationDice are designed to operate over this range, but are tested
and guaranteed at TA= +25°C only. Contact factory for
availability.
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +7.0V
Input Voltage Levels
(SDI+, SDI-, SLBI+, SLBI-)...........(VCC- 0.5V) to (VCC+ 0.5V)
Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±10mA
PECL Output Voltage
(SDO+, SDO-, SCLKO+, SCLKO-).......................(VCC+ 0.5V)
PECL Output Current, (SDO+, SDO-, SCLKO+, SCLKO-).....56mA
Voltage at LOL, SIS, PHADJ+, PHADJ-,
FIL+, FIL-.................................................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
TQFP (derate 16.1mW/°C above +85°C)........................1.0W
Operating Temperature Range
MAX3875EHJ..................................................-40°C to +85°C
Operating Junction Temperature (die)..............-55°C to +150°C
Storage Temperature Range.............................-60°C to +160°C
Processing Temperature (die).........................................+400°C
Lead Temperature (soldering, 10sec).............................+300°C
Figure 1. Input Amplitude
Note 1:Dice are tested at TA= +25°C only.
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and TA= +25°C.) (Note 2)
Note 2:AC characteristics are guaranteed by design and characterization.
Note 3:See Typical Operating Characteristicsfor worst-case distribution.
Typical Operating Characteristics(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
Pin Description
Typical Operating Characteristics (continued)
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming ICFigure 3. Functional Diagram
Pin Description (continued)
Detailed DescriptionThe MAX3875 consists of a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
and PECL output buffer (Figure 3). The PLL consists of
a phase/frequency detector (PFD), a loop filter, and a
voltage-controlled oscillator (VCO).
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
Input AmplifierInput amplifiers are implemented for both the main data
and system loopback inputs. These amplifiers accept a
differential input amplitude from 50mVp-p up to
800mVp-p. The bit error rate is better than 1 · 10-10for
input signals as small as 10mVp-p, although the jitter
tolerance performance will be degraded. For interfacing
with PECL signal levels, see Applications Information.
Phase DetectorThe phase detector incorporated in the MAX3875 pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming. The
external phase adjust pins (PHADJ+, PHADJ-) allow the
user to vary the internal phase alignment.
Frequency DetectorThe digital frequency detector (FD) aids frequency
acquisition during start-up conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the in-phase and quadra-
ture VCO outputs on both edges of the data input sig-
nal. Depending on the polarity of the frequency
difference, the FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequen-
cy detector.
Loop Filter and VCOThe phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor, CF,
is required to set the PLL damping ratio. Refer to
Design Procedurefor guidelines on selecting this
capacitor.
The loop filter output controls the on-chip LC VCO run-
ning at 2.488GHz. The VCO provides low phase noise
and is trimmed to the correct frequency. Clock jitter
generation is typically 1.2psRMSwithin a jitter band-
width of 12kHz to 20MHz.
Loss-of-Lock MonitorA loss-of-lock (LOL) monitor is incorporated in the
MAX3875 frequency detector. A loss-of-lock condition
is signaled immediately with a TTL low. When the PLL is
frequency locked, LOLswitches to TTL high in approxi-
mately 800ns.
Note that the LOLmonitor is only valid when a data
stream is present on the inputs to the MAX3875. As a
result, LOLdoes not detect a loss-of-power condition
resulting from a loss of the incoming signal.
Design Procedure
Setting the Loop FilterThe MAX3875 is designed for both regenerator and
receiver applications. Its fully integrated PLL is a clas-
sic second-order feedback system, with a loop band-
width (fL) fixed at 1.1MHz. The external capacitor, CF,
can be adjusted to set the loop damping. Figures 4 and
5 show the open-loop and closed-loop transfer func-
tions.
The PLL zero frequency, fZ, is a function of external
capacitor CF, and can be approximated according to:
For an overdamped system (fZ/fL) < 0.25, the jitter peak-
ing (MP) of a second-order system can be approxi-
mated by:
For example, using CF= 0.1µF results in a jitter peaking
of 0.2dB. Reducing CFbelow 0.01µF may result in PLL
instability. The recommended value for CF= 1.0µF to
guarantee a maximum jitter peaking of less than 0.1dB.must be a low TC, high-quality capacitor of type
X7R or better.
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
