MAX3875 Fast Delivery |IC PHOENIX CO.,LIMITED

MAX3875 ,2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming ICApplicationsPART TEMP. RANGE PIN-PACKAGESDH/SONET Receivers and RegeneratorsMAX3875EHJ -40°C to +85 ..
MAX3875AEHJ , 2.5Gbps, Low-Power, 3.3V Clock Recovery and Data Retiming IC
MAX3875EHJ ,2.5Gbps / Low-Power / #.3V Clock Recovery and Data Retiming ICApplicationsPART TEMP. RANGE PIN-PACKAGESDH/SONET Receivers and RegeneratorsMAX3875EHJ -40°C to +85 ..
MAX3880ECB ,+3.3V, 2.488Gbps, SDH/SONET 1:16 deserializer with clock recovery.Applications2.488Gbps SDH/SONET Transmission SystemsPin Configuration appears at end of data sheet. ..
MAX3880ECB+D ,+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock RecoveryApplications*Exposed pad2.488Gbps SDH/SONET Transmission Systems+Denotes lead-free package.Add/Drop ..
MAX3882AETX+ ,2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting AmplifierApplications Ordering InformationSDH/SONET Receivers and RegeneratorsPART TEMP RANGE PIN-PACKAGE MA ..
MAX7425CUA ,5th-Order, Lowpass, Switched-Capacitor Filtersapplications. They feature a shutdown mode Clock-Turnable Corner Frequency (1Hz to 45kHz)that red ..
MAX7426CPA ,5th-Order, Lowpass, Elliptic, Switched-Capacitor FiltersApplications Ordering InformationADC Anti-Aliasing CT2 Base StationsPART TEMP. RANGE PIN-PACKAGEMAX ..
MAX7426CUA ,5th-Order, Lowpass, Elliptic, Switched-Capacitor FiltersELECTRICAL CHARACTERISTICS—MAX7426(V = +5V, filter output measured at OUT, 10kΩ || 50pF load to GND ..
MAX7427CUA ,5th-Order, Lowpass, Elliptic, Switched-Capacitor FiltersELECTRICAL CHARACTERISTICS—MAX7426 (continued)(V = +5V, filter output measured at OUT, 10kΩ || 50pF ..
MAX7427CUA ,5th-Order, Lowpass, Elliptic, Switched-Capacitor FiltersFeaturesThe MAX7426/MAX7427 5th-order, lowpass, elliptic, 5th-Order, Elliptic Lowpass Filtersswitc ..
MAX7427EUA+T ,5th-Order, Lowpass, Elliptic, Switched-Capacitor FiltersApplications Ordering InformationADC Anti-Aliasing CT2 Base StationsPART TEMP. RANGE PIN-PACKAGEMAX ..

MAX3875
2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC
General Description
The MAX3875 is a compact, low-power clock recovery
and data retiming IC for 2.488Gbps SDH/SONET appli-
cations. The fully integrated phase-locked loop recov-
ers a synchronous clock signal from the serial NRZ
data input, which is retimed by the recovered clock.
Differential PECL-compatible outputs are provided for
both clock and data signals, and an additional
2.488Gbps serial input is available for system loopback
diagnostic testing. The device also includes a TTL-
compatible loss-of-lock (LOL) monitor.
The MAX3875 is designed for both section-regenerator
and terminal-receiver applications in OC-48/STM-16
transmission systems. Its jitter performance exceeds all
of the SONET/SDH specifications.
This device operates from a single +3.3V to +5.0V supply
over a -40°C to +85°C temperature range. The typical
power consumption is only 400mW with a +3.3V supply. It is
available in a 32-pin TQFP package, as well as in die form.
Applications
SDH/SONET Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
2.488Gbps ATM Receiver
Digital Video Transmission
SDH/SONET Test Equipment
FeaturesExceeds ANSI, ITU, and Bellcore SONET/SDH
Regenerator Specifications400mW Power Dissipation (at +3.3V)Clock Jitter Generation: 0.003UIRMSSingle +3.3V or +5V Power SupplyFully Integrated Clock Recovery and Data RetimingAdditional High-Speed Input Facilitates System
Loopback Diagnostic TestingTolerates >2000 Consecutive Identical DigitsLoss-of-Lock IndicatorDifferential PECL-Compatible Data and Clock
Outputs
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
PRE/POSTAMPLIFIER
PHOTO-
DIODE
+3.3V
SDI-
SDI+
SLBI-
SLBI+
SDO-
SCLKO+
SCLKO-
SDO+
MAX3875
MAX3866
+3.3V+3.3V
+3.3V
+3.3V
OUT+
OUT-
TTL
LOP
LOLPHADJ-PHADJ+VCC
VCC
SISFIL+FIL-
SYSTEM
LOOPBACKTTL
TTL
1μF
0.01μF0.01μF
82Ω82Ω
130Ω130Ω
82Ω82Ω
130Ω130Ω
1:16
DESERIALIZER
MAX3885ypical Application Circuit
19-4789; Rev 0; 10/98
PART
MAX3875EHJ-40°C to +85°C
TEMP. RANGEPIN-PACKAGE
32 TQFP
Ordering Information
Pin Configuration appears at end of data sheet.
MAX3875E/D-40°C to +85°CDice*Dice are designed to operate over this range, but are tested
and guaranteed at TA= +25°C only. Contact factory for
availability.
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +7.0V
Input Voltage Levels
(SDI+, SDI-, SLBI+, SLBI-)...........(VCC- 0.5V) to (VCC+ 0.5V)
Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±10mA
PECL Output Voltage
(SDO+, SDO-, SCLKO+, SCLKO-).......................(VCC+ 0.5V)
PECL Output Current, (SDO+, SDO-, SCLKO+, SCLKO-).....56mA
Voltage at LOL, SIS, PHADJ+, PHADJ-,
FIL+, FIL-.................................................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
TQFP (derate 16.1mW/°C above +85°C)........................1.0W
Operating Temperature Range
MAX3875EHJ..................................................-40°C to +85°C
Operating Junction Temperature (die)..............-55°C to +150°C
Storage Temperature Range.............................-60°C to +160°C
Processing Temperature (die).........................................+400°C
Lead Temperature (soldering, 10sec).............................+300°C
Figure 1
Excluding PECL output termination= 0°C to +85°C = 0°C to +85°C
CONDITIONSVCC- 0.4VCC+ 0.2VISSingle-Ended Input Voltage
(SDI±, SLBI±)
mVp-p50800 VID122167ICCSupply Current
Differential Input Voltage
(SDI±, SLBI±)2.4VCCVOHTTL Output High Voltage (LOL)-10+10TTL Input Current (SIS)0.8VILTTL Input Low Voltage (SIS)45RINInput Termination to VCC
(SDI±, SLBI±)VCC- 1.025 VCC- 0.88 VOHPECL Output High Voltage
(SDO±, SCLKO±)VCC- 1.81 VCC- 1.62 VOLPECL Output Low Voltage
(SDO±, SCLKO±)2.0VIHTTL Input High Voltage (SIS)
UNITSMINTYPMAXSYMBOLPARAMETER
TTL Output Low Voltage (LOL)VOL0.4V
VCC- 1.085 VCC- 0.88
VCC- 1.83 VCC- 1.555
TA = -40°C
TA = -40°C
Figure 1. Input AmplitudeFigure 2. Output Clock-to-Q Delay
SCLKO+
SDO
tCK
tCK-Q
SDI+
SDI-
VID(SDI+) -
(SDI-)
50mVp-p MIN
800mVp-p MAX
25mV MIN
400mV MAX
Note 1:Dice are tested at TA= +25°C only.
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and TA= +25°C.) (Note 2)
Clock Output Edge Speed20% to 80%
f ≤2MHzps
Figure 2
1.76 2.75
0.21 0.45
f = 100kHz
f = 10MHz (Note 3)
f = 70kHz
f = 1MHz
CONDITIONS0.1JPJitter Peaking110 290
Gbps2.488Serial Output Clock Rate
Clock-to-Q Delay
UIp-p0.0260.056
UIRMS0.0030.006JGENJitter Generation
MHz1.12.0JBWJitter Transfer Bandwidth
UIp-p
Jitter Tolerance0.41 0.67
UNITSMINTYPMAXSYMBOLPARAMETER
Data Output Edge Speed20% to 80%108ps
Tolerated Consecutive
Identical Digits2000Bits
100kHz to 2.5GHz-17
2.5GHz to 4.0GHz-15
Jitter BW = 12kHz to 20MHz
Note 2:AC characteristics are guaranteed by design and characterization.
Note 3:See Typical Operating Characteristicsfor worst-case distribution.
Input Return Loss
(SDI±, SLBI±)dB
Typical Operating Characteristics
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
RECOVERED CLOCK JITTER
MAX3875 toc02
10ps/div
PRBS = 215 - 1
RMSΔ = 1.2ps
10k10M100k1M
JITTER TOLERANCE
MAX3875 toc03
JITTER FREQUENCY (Hz)
INPUT JITTER (UIp-p)
PRBS = 223 - 1
50mVp-p INPUT
BELLCORE
MASK
RECOVERED DATA AND CLOCK
(DIFFERENTIAL OUTPUT)
MAX3875 toc01
100ps/div
CLOCK
DATA223 - 1 PATTERN
VIN = 20mVP-PTA = +85°C
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
BIT ERROR RATE vs. INPUT VOLTAGE
MAX3875toc06
INPUT VOLTAGE (mVp-p)
BIT ERROR RATE
PRBS = 223 - 1
SUPPLY CURRENT
vs. TEMPERATURE
MAX3875toc07
AMBIENT TEMPERATURE (°C)
SUPPLY CURRENT (mA)
VCC = +3.3V
VCC = +5.0V
NAMEFUNCTION
1, 2, 8, 9,
10, 16, 26,
29, 32
GNDSupply Ground
3, 6, 11,
14, 15, 17,
20, 21, 24
VCCPositive Supply Voltage
PINSDI+Positive Data Input. 2.488Gbps serial data stream.SDI-Negative Data Input. 2.488Gbps serial data stream.SLBI-Negative System Loopback Input. 2.488Gbps serial data stream.SLBI+Positive System Loopback Input. 2.488Gbps serial data stream.SISSignal Input Selection, TTL. Low for normal data input. High for system loopback input.
Pin Description
JITTER TOLERANCE vs. INPUT VOLTAGE
MAX3875toc04
INPUT VOLTAGE (mVp-p)
JITTER TOLERANCE (UIp-p)
JITTER FREQUENCY
= 1MHz
JITTER FREQUENCY
= 5MHz
PRBS = 223 - 1
-2.7100k1M10k10M
JITTER TRANSFER
MAX3875 toc05
JITTER FREQUENCY (Hz)
JITTER TRANSFER (dB)
PRBS = 223 - 1
BELLCORE
MASK
DISTRIBUTION OF JITTER TOLERANCE
MAX3875toc05a
JITTER TOLERANCE (UIp-p)
PERCENT OF UNITS (%)
MEAN = 0.41σ = 0.028
fJITTER = 10MHz
VCC = +3.0V
TA = -40°C
Typical Operating Characteristics (continued)
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)SCLKO-Negative Serial Clock Output, PECL, 2.488GHz. SDO- is clocked out on the falling edge of SCLKO-.
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
SDI+
SDI-
SLBI+
SLBI-
SCLKO-
SCLKO+
SDO+
SDO-
PHASE AND
FREQUENCY
DETECTOR
PHADJ-FIL+FIL-
LOOP
FILTER
MAX3875
LOL
PHADJ+SISSIS
MUX
AMP
AMP
VCO
CML
CML
TTL
Figure 3. Functional Diagram
NAMEFUNCTIONPINPHADJ-Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCCif not used.LOLLoss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10kΩpull-up resistor)SDO+Positive Data Output, PECL compatible, 2.488GbpsSDO-Negative Data Output, PECL compatible, 2.488GbpsSCLKO+Positive Serial Clock Output, PECL, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+.PHADJ+Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCCif not used.FIL-Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.FIL+Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Pin Description (continued)
Detailed Description
The MAX3875 consists of a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
and PECL output buffer (Figure 3). The PLL consists of
a phase/frequency detector (PFD), a loop filter, and a
voltage-controlled oscillator (VCO).
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
Input Amplifier
Input amplifiers are implemented for both the main data
and system loopback inputs. These amplifiers accept a
differential input amplitude from 50mVp-p up to
800mVp-p. The bit error rate is better than 1 · 10-10for
input signals as small as 10mVp-p, although the jitter
tolerance performance will be degraded. For interfacing
with PECL signal levels, see Applications Information.
Phase Detector
The phase detector incorporated in the MAX3875 pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming. The
external phase adjust pins (PHADJ+, PHADJ-) allow the
user to vary the internal phase alignment.
Frequency Detector
The digital frequency detector (FD) aids frequency
acquisition during start-up conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the in-phase and quadra-
ture VCO outputs on both edges of the data input sig-
nal. Depending on the polarity of the frequency
difference, the FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequen-
cy detector.
Loop Filter and VCO
The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor, CF,
is required to set the PLL damping ratio. Refer to
Design Procedurefor guidelines on selecting this
capacitor.
The loop filter output controls the on-chip LC VCO run-
ning at 2.488GHz. The VCO provides low phase noise
and is trimmed to the correct frequency. Clock jitter
generation is typically 1.2psRMSwithin a jitter band-
width of 12kHz to 20MHz.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is incorporated in the
MAX3875 frequency detector. A loss-of-lock condition
is signaled immediately with a TTL low. When the PLL is
frequency locked, LOLswitches to TTL high in approxi-
mately 800ns.
Note that the LOLmonitor is only valid when a data
stream is present on the inputs to the MAX3875. As a
result, LOLdoes not detect a loss-of-power condition
resulting from a loss of the incoming signal.
Design Procedure
Setting the Loop Filter
The MAX3875 is designed for both regenerator and
receiver applications. Its fully integrated PLL is a clas-
sic second-order feedback system, with a loop band-
width (fL) fixed at 1.1MHz. The external capacitor, CF,
can be adjusted to set the loop damping. Figures 4 and
5 show the open-loop and closed-loop transfer func-
tions.
The PLL zero frequency, fZ, is a function of external
capacitor CF, and can be approximated according to:
For an overdamped system (fZ/fL) < 0.25, the jitter peak-
ing (MP) of a second-order system can be approxi-
mated by:
For example, using CF= 0.1µF results in a jitter peaking
of 0.2dB. Reducing CFbelow 0.01µF may result in PLL
instability. The recommended value for CF= 1.0µF to
guarantee a maximum jitter peaking of less than 0.1dB.must be a low TC, high-quality capacitor of type
X7R or better.fPZ=20log 1+60 Cz()
MAX3875
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
CF = 1.0μF
fZ = 2.6kHzCF = 0.1μF
fZ = 26kHz
f (kHz)
Figure 4. Open-Loop Transfer Function
CF = 1.0μF
H(j2πf) (dB)
f (kHz)
CLOSED-LOOP GAIN
CF = 0.1μF
Figure 5. Closed-Loop Transfer Function

Partno	Mfg	Dc	Qty	Available	Descript
MAX3875	MAX	N/a	2	avai	2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC