MAX3831UCB ,+3.3V / 2.5Gbps / SDH/SONET / 4-Channel Interconnect Mux/Demux ICs with Clock GeneratorApplicationstern and rolls the demux to maintain proper channelSDH/SONET Backplanes ATM Switching N ..
MAX383CPE ,Precision, Low-Voltage Analog SwitchesGeneral Description ________
MAX383CSE ,Precision, Low-Voltage Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = 2.4V, V = 0.8V ..
MAX383CSE ,Precision, Low-Voltage Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = 2.4V, V = 0.8V ..
MAX383CSE ,Precision, Low-Voltage Analog SwitchesBlock Diagrams/Truth TablesTOP VIEWCOM1 1 16 1 1NO1 COM1 16 NO1 COM1 16 NO1 2N.C. 15 IN1 2 15 IN1 2 ..
MAX383CSE+ ,Precision, Low-Voltage, SPST CMOS Analog SwitchBlock Diagrams/Truth TablesTOP VIEWCOM 1 1 16 1 1NO1 COM 1 16 NO1 COM 1 16 NO1 2N.C. 15 IN1 2 15 IN ..
MAX739CPD ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorslVI/lXI/VI
-5V, -12V, -15V, and Adjustable
Inverting Gurrent-Mode PWM Regulators
MAX739CWE ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorsGeneral Description
The MAX736/MAX737/MAX739/MAX759 are CMOS, in-
verting, switch-mode regulato ..
MAX739EWE ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorsFeatures
. Pre-Set -5V, -12V, -15V or Adjustable Outputs
. Convert Positive Voltages to Negative
..
MAX7400CSA ,8th-Order, Lowpass, Elliptic, Switched-Capacitor Filtersapplications. They fea-' Single-Supply Operationture a shutdown mode that reduces the supply curren ..
MAX7400ESA ,8th-Order, Lowpass, Elliptic, Switched-Capacitor FiltersELECTRICAL CHARACTERISTICS—MAX7400/MAX7403(V = +5V, filter output measured at OUT, 10kΩ || 50pF loa ..
MAX7400ESA+T ,8th-Order, Lowpass, Elliptic, Switched-Capacitor FiltersELECTRICAL CHARACTERISTICS—MAX7400/MAX7403(V = +5V, filter output measured at OUT, 10kΩ || 50pF loa ..
MAX3831UCB
+3.3V / 2.5Gbps / SDH/SONET / 4-Channel Interconnect Mux/Demux ICs with Clock Generator
General DescriptionThe MAX3831/MAX3832 are 4:1 multiplexers (muxes)
and 1:4 demultiplexers (demuxes) with automatic chan-
nel assignment. Operating from a single +3.3V supply,
the mux receives four parallel, 622Mbps SDH/SONET
channels. These channels are bit interleaved to gener-
ate a serial data stream of 2.488Gbps for interfacing to
an optical or an electrical driver. A 10-bit-wide elastic
buffer tolerates up to ±7.5ns skew between any parallel
data input and the reference clock. An external
155MHz reference clock is required for the on-chip PLL
to synthesize a high-frequency 2.488GHz clock for tim-
ing the outgoing data streams.
The MAX3831/MAX3832’s demux receives 2.488Gbps
serial data and the 2.488GHz clock from an external
clock/data recovery device (MAX3876), converting it to
four 622Mbps LVDS outputs. The MAX3831 provides a
622MHz LVDS clock output, and the MAX3832 pro-
vides a 155MHz LVDS clock output. An internal frame
detector looks for a 622Mbps SDH/SONET framing pat-
tern and rolls the demux to maintain proper channel
assignment at the outputs.
These devices also include an embedded pattern gen-
erator that enables a full-speed, built-in self-test (BIST).
Two different loopback modes provide system test flexi-
bility. A TTL loss-of-frame monitor is included. The
MAX3831/MAX3832 are available in 64-pin TQFP-EP
(exposed paddle) packages and are specified over the
upper commercial (0°C to +85°C) temperature range.
Features+3.3V Single Supply1.45W Power Dissipation (MAX3831)4-Channel Mux/Demux with Fully Integrated
2.488GHz Clock GeneratorFrame Detection Maintains Channel Assignment±7.5ns Elastic Store Range2.5ps RMS Serial-Data Output Random Jitter8ps Serial-Data Output Deterministic Jitter622Mbps LVDS Parallel Input/Output2.488Gbps Serial CML Input/OutputOn-Chip Pattern Generator Provides
High-Speed BIST System Test Flexibility: System Loopback,
Line LoopbackLoss-of-Frame Indicator
ApplicationsSDH/SONET BackplanesATM Switching Networks
High-Speed Parallel LinksLine Extenders
Intrarack/SubrackDense Digital Cross-
InterconnectsConnects
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator19-1534; Rev 1; 10/99
Ordering InformationPin Configuration appears at end of data sheet.
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, LVDS differential load = 100Ω±1%, CML load = 50Ω±1% to VCC, all TTL inputs are open, TA= 0°C to
+85°C, unless otherwise noted. Typical values are at TA= +25°C and VCC= +3.3V.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Positive Supply Voltage (VCC)...............................-0.5V to +5.0V
Input Voltage (LVDS, TTL)..........................-0.5V to (VCC+ 0.5V)
CML Input Voltage..........................(VCC- 0.8V) to (VCC+ 0.5V)
FIL+, FIL- Voltage.......................................-0.5V to (VCC+ 0.5V)
TTL Output Voltage....................................-0.5V to (VCC+ 0.5V)
LVDS Output Voltage..................................-0.5V to (VCC+0.5V)
CML Output Currents..........................................................22mA
Continuous Power Dissipation (TA= +85°C) (Note 1)
64-Pin TQFP-EP (derate 40.0mW/°C above +85°C).........2.6W
Operating Temperature Range...............................0°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
Note 1:Based on empirical data from the MAX3831/MAX3832 evaluation kit.
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, LVDS differential load = 100Ω±1%, CML load = 50Ω±1% to VCC, all TTL inputs are open, TA= 0°C to
+85°C, unless otherwise noted. Typical values are at TA= +25°C and VCC= +3.3V.)
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, LVDS differential load = 100Ω±1%, CML load = 50Ω±1% to VCC, all TTL inputs are open, TA= 0°C to
+85°C, unless otherwise noted. Typical values are at TA= +25°C and VCC= +3.3V.) (Note 4)
Note 2:When TEST= GND, the pattern generator will consume an additional 30mA.
Note 3:Guaranteed by design and characterization.
Note 4:AC characteristics are guaranteed by design and characterization.
Note 5:Relative to the positive edge of the 155MHz reference clock. PDI1 to PDI4 aligned to RCLKI at reset.
Note 6:Measured with a reference clock jitter of <1psRMS.
Note 7:Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion.
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock GeneratorFigure 1. Definition of the LVDS Output
Figure 2. Definition of the CML Input
Figure 3. Timing Parameters
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
SERIAL-DATA OUTPUT EYE DIAGRAMMAX3831/2 toc01
50ps/div
SERIAL-DATA OUTPUT JITTERMAX3831/2 toc02
5ps/div
SUPPLY CURRENT vs. TEMPERATURE
MAX3831/2 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
ELASTIC STORE RANGE
MAX3831/2 toc04
DATA TO RCLKI DELAY AT RESET (ns)
VARIATION OF DATA DELAY AFTER RESET (ns)
SERIAL-DATA HOLD TIME
MAX3831/2 toc05
TEMPERATURE (°C)
HOLD TIME (ps)
SERIAL-DATA SETUP TIME
MAX3831/2 toc06
TEMPERATURE (°C)
SETUP TIME (ps)
MAX3831
PARALLEL CLOCK-TO-DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
MAX3831/2 toc07
TEMPERATURE (°C)
PCLKO TO PDO_ PROPAGATION DELAY (ps)
Typical Operating Characteristics(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
Pin Description
_______________Detailed DescriptionThe MAX3831/MAX3832 use a 4:1 mux and 1:4 demux
with an elastic store buffer to simplify SDH/SONET
interconnect I/O routing. The 622Mbps low-voltage dif-
ferential signal (LVDS) parallel inputs pass through the
10-bit elastic store buffer, which accommodates ±7.5ns
skew on any single input relative to the 155MHz refer-
ence clock input RCLKI. This reference clock is
required to synthesize the internal 2.488GHz clock
used to drive the elastic store and 4:1 multiplexer. All
TTL and LVDS outputs can be placed in a high-imped-
ance state. See Figure 4 for a functional diagram.
The 4:1 mux bit-interleaves the parallel data, providing
a 2.488Gbps CML serial output to the optical or electri-
cal driver. The CML serial input receives the
2.488Gbps data, the demux deinterleaves it to
622Mbps and sends the data to the frame detector.
The frame detector monitors one 622Mbps channel and
rolls the demux into the proper channel assignment.
The MAX3831/MAX3832 include high-speed, built-in
self-test (BIST), which also allows testing of the
622Mbps parallel-system loopback and the 2.488Gbps
line loopback.
Elastic Store BufferEach parallel-data input, PDI1 to PDI4, passes through
its respective 10-bit elastic store buffer. Following an
elastic store reset, this buffer accommodates ±7.5ns of
skew on any input relative to the 155MHz reference
clock. Figure 5 illustrates the elastic store buffer rela-
tionship with RCLKI. The Elastic Store Range graph in
the Typical Operating Characteristicsshows the
amount of data skew tolerated.
Following a 10µs power-up period, the locations of the
individual data-channel bit transitions are acquired,
guaranteeing data preservation. The output of this
block passes directly into the 4:1 mux. After power-up,
the elastic store buffer must be reset by applying a low
pulse on RSETESfor at least 10ns.
Due to the inherent uncertainty of the data transitions
between the parallel-data inputs there is no bit or frame
alignment between these inputs. However, the demux
ensures proper channel assignment is maintained.
Bit-Interleaved Multiplexer/
DemultiplexerThe MAX3831/MAX3832 use a bit interleave/deinterleave
mux/demux. To guarantee channel assignment, one of
the four channels is inverted before multiplexing to pro-
vide a reference for the frame detector during demulti-
plexing. After demultiplexing, the same channel is
inverted back to the original data format.
Frame DetectorAfter a 2.5Gbps serial data is bit deinterleaved into four
622Mbps channels, an SDH/SONET frame detector
monitors the fourth channel, looking for the 32-bit pat-
tern (A1A1A2A2) in the OC-12 header. To maintain cor-
rect channel assignment, the demux outputs rotate until
this 32-bit overhead pattern is reliably detected. A loss-
of-frame output, LOF, indicates when the received data
is in or out of frame. When LOFgoes high, the frame
pattern is detected and the demux outputs are correct-
ly assigned. When LOFis low, the frame detection cir-
cuitry is searching for the correct frame. A RSETFR
(TTL, active low) is included to reset the frame detector
when necessary.
The frame detector uses an algorithm to detect an in-
frame condition and a loss-of-frame condition; this algo-
rithm is implemented to meet the SONET in-frame and
false-frame specs. The frame_search state will occur
upon start-up or reset. In this state, the frame detector
scans through the incoming serial data searching for the
framing pattern in the channel 4 output of the demux.
While in this state, if the framing pattern is not found
within 250µs, the demux channels are shifted (rolled)
and the frame search continues (Figure 6).
In-frame will be declared if two consecutive framing
patterns are found at the correct byte locations within
the SONET frame (9720 bytes). If this pattern is not pre-
MAX3831/MAX3832
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
Pin Description (continued)
MAX3831/MAX3832sent at the correct location (false frame), the state
machine will return to the frame_search state described
above. While in the in_frame state, each frame will be
checked for a framing pattern at the correct location.
Four consecutive false frames will cause the state
machine to return to the frame_search state described
above. The false-frame counter is reset with three or
fewer consecutive false frames.
Built-In Self-Test
with On-Chip Serial LoopbackAn on-chip pattern generator can be enabled to pro-
duce a 622Mbps SDH/SONET-like transport overhead
followed by a pseudorandom bit sequence. This consists
of 12 A1s, 12 A2s, and a pseudorandom bit stream
(PRBS = 27- 1). When TESTis low, this pattern is distrib-
uted to all parallel inputs, bypassing the LVDS input
buffers. Note, this pattern is skewed by one 622MHz
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
