MAX3816ACUE+ Fast Delivery |IC PHOENIX CO.,LIMITED

MAX381CPE ,Precision, Low-Voltage Analog SwitchesMAX381/MAX383/MAX38519-0300; Rev 0; 9/94Precision, Low-Voltage Analog Switches_______________
MAX381CSE ,Precision, Low-Voltage Analog SwitchesApplicationsMAX381ESE -40°C to +85°C 16 Narrow SOSample-and-Hold Circuits Military RadiosMAX381EJE ..
MAX381EJE ,Precision, Low-Voltage Analog SwitchesMAX381/MAX383/MAX38519-0300; Rev 0; 9/94Precision, Low-Voltage Analog Switches_______________
MAX381EPE ,Precision, Low-Voltage Analog SwitchesGeneral Description ________
MAX381ESE ,Precision, Low-Voltage Analog SwitchesBlock Diagrams/Truth TablesTOP VIEWCOM1 1 16 1 1NO1 COM1 16 NO1 COM1 16 NO1 2N.C. 15 IN1 2 15 IN1 2 ..
MAX3831UCB ,+3.3V / 2.5Gbps / SDH/SONET / 4-Channel Interconnect Mux/Demux ICs with Clock GeneratorApplicationstern and rolls the demux to maintain proper channelSDH/SONET Backplanes ATM Switching N ..
MAX739CPD ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorslVI/lXI/VI -5V, -12V, -15V, and Adjustable Inverting Gurrent-Mode PWM Regulators
MAX739CWE ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorsGeneral Description The MAX736/MAX737/MAX739/MAX759 are CMOS, in- verting, switch-mode regulato ..
MAX739EWE ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorsFeatures . Pre-Set -5V, -12V, -15V or Adjustable Outputs . Convert Positive Voltages to Negative ..
MAX7400CSA ,8th-Order, Lowpass, Elliptic, Switched-Capacitor Filtersapplications. They fea-' Single-Supply Operationture a shutdown mode that reduces the supply curren ..
MAX7400ESA ,8th-Order, Lowpass, Elliptic, Switched-Capacitor FiltersELECTRICAL CHARACTERISTICS—MAX7400/MAX7403(V = +5V, filter output measured at OUT, 10kΩ || 50pF loa ..
MAX7400ESA+T ,8th-Order, Lowpass, Elliptic, Switched-Capacitor FiltersELECTRICAL CHARACTERISTICS—MAX7400/MAX7403(V = +5V, filter output measured at OUT, 10kΩ || 50pF loa ..

MAX3816ACUE+
I²C 2-Wire Extender for DDC in DVI, HDMI, and VGA Interfaces
MAX3816A2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
19-4109; Rev 0; 7/08
EVALUATION KIT
AVAILABLE
General Description
The MAX3816A DDC*/I2C extender automatically compen-
sates for excess load capacitance of long DVI™, HDMI™,
and VGA cables. A single MAX3816A placed at the dis-
play side of the link restores signal integrity bidirectionally
for both DDC clock and data over 0 to 60 meters of cable.
The MAX3816A features compensation for cable
capacitance with a guaranteed range up to 3000pF,
typically beyond 5000pF. The MAX3816A detects state-
change assertion by the logical “AND” of the source
side and display side. It asserts the new state with a
rail-to-rail slew-rate-limited driver capable of meeting
I2C rise- and fall-time requirements under the full load
of the cable. After assertion of the new state, a holdoff
period of 2.5µs prevents a subsequent state change
while the cable channel settles.
Under full load at 100kbps, the MAX3816A consumes
25mW, excluding pullup resistors. It is available in a
16-pin TSSOP package and operates from 0°C to +70°C.
Applications
Front-Projector DVI/HDMI Inputs
High-Definition Televisions, Displays, and
Computer Monitors
DVI/HDMI Cable-Extender Modules and Active
Cable Assemblies
FeaturesDDC or I2C Cable Extension Up to 60 Meters at
100kbps for Both Clock and Data ChannelsSingle-Sided Solution Requires Only One
MAX3816A at the Display SideCompensates for Cable Capacitance, 0 to 3000pF
Guaranteed (8x I2C Specification), or Beyond
5000pF TypicalParallel and Serial Operating ModesPrevents Ringing Due to Reflections by
Terminating Transmission Line Impedance After
TransitionsUse with MAX3815 TMDS®Equalizer to Form a
Complete Digital Video Extension Solution3.0V to 5.5V Power SupplyOptional Voltage Translation Between 5V Cable
DDC and 3.3V Display DDC Levelsypical Application Circuit (Parallel Mode)
Ordering Information
PARTTEMP RANGEPIN-PACKAGE
MAX3816ACUE+ 0°C to +70°C 16 TSSOP
+Denotes a lead-free/RoHS-compliant package.
Pin Configuration appears at end of data sheet.
*DDC (Display Data Channel) is part of the VESA Standard.
DVI is a trademark of Digital Display Working Group.
DRVR_EN
VCC
CLOCK_C
DATA_C
GND_REF
CLOCK_D
VSS
DATA_D
VDD
DDC SCL
DDC SDA
DDC +5V
CONNECTOR TO DISPLAY
DVI, HDMI, OR M1 CONNECTOR, < 3m
47kΩ47kΩ
10μF
10μF
LONG CABLE FROM VIDEO SOURCE:
DVI, HDMI, OR CAT-5 CABLE UP TO 60m
(200ft)
VCC
SHIELD GNDS
DDC SCL
DDC SDA
DDC +5V
SHIELD GNDS
DDC GNDDDC GND
CABLE HEAD OR EXTENDER BOX
VDD OR VSS (SEE DESCRIPTION)
MAX3816A
*TO MEET DVI/HDMI SPECIFICATIONS FOR THE DDC +5V LINK, THE VDD SIDE OF THE MAX3816A MUST BE EXTERNALLY POWERED. IF NOT APPLICABLE, CONNECT TO DDC +5V.
5V*
MODEVDD
MAX3816A2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +5.5V, VDD= +3.0V to +5.5V, TA= 0°C to +70°C. Typical values are at TA= +25°C, VCC= +5.0V, VDD= +3.3V,
unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range (relative to VSS) at VDD, VCC,
CLOCK_D, DATA_D,CLOCK_C, DATA_C,
DRVR_EN, MODE..................................................-0.5V to +6.0V
Continuous Power Dissipation (TA= +70°C)
(derate 11.1mW/°C above +70°C)..............................889mW
Voltage Range (relative to VSS) at GND_REF.......-0.5V to +0.5V
Operating Junction Temperature (TJ) Range....-55°C to +150°C
Storage Ambient Temperature (TS) Range.......-40°C to +150°C
Electrostatic Discharge (ESD)
Human Body Model......................................................> ±3kV
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLY
Supply Voltage VCC or VDDSee the Applications Information section
(Note 1) 3.0 5.5 V
ICC
VCC = 5.5V, VDD = 5.5V, 100kbps,
60pF load on cable, 10pF load on display,
current into VCC pin
1.3 3.0
Supply Current
IDD
VCC = 5.5V, VDD = 5.5V, 100kbps,
60pF load on cable, 10pF load on display,
current into VDD pin
4.3 7.0
mA
DC to 500kHz 100 Supply Noise Tolerance DC to 60Hz (series mode) 700mVP-P
CLOCK_C, DATA_C, CLOCK_D, DATA_D (Notes 2, 3)
Cable side (CLOCK_C, DATA_C) VCC - 0.1 VCCOutput-High Voltage VOHDisplay side (CLOCK_D, DATA_D) VDD - 0.1 VDDV
VOLVOL achieved within 1μs of negative
transition (see Figure 1a, State 2) 0.2 0.4 V
Cable
side 15 Output-Low Voltage
VHOLD
After VOL is achieved, VHOLD is
the most positive level allowed
if logic level is 0 and no other
driver is asserting low on the
same node (series mode)
Display
side 20
% of
Supply
High-to-Low Threshold VTRIGIH
Threshold used to detect high-to-low
transition relative to supply (VCC for cable
side, VDD for display side)
75 % of
Supply
Cable
side 12.5
Low-to-High Threshold VTRIGIL
Threshold used to detect low-to-
high transition relative to supply
(VCC for cable side, VDD for
display side)
Display
side 17.5
% of
Supply
Output-High-State Current Limit Output in ramp-up mode for DATA_C 5.0 16.5 mA
MAX3816A2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
3.0V to 3.6V supply 700 1000 Rise Time (Note 4) tR4.5V to 5.5V supply 700 ns
3.0V to 3.6V supply 200 300 Fall Time (Note 4) tF4.5V to 5.5V supply 300 ns
Driver On-Time Driver asserting high or low 1750 ns
Driver Active Termination Driver asserting high or low 60
TRANSITION SENSING
Level-Sense Filter Delay Time to transition decision and assert 300 ns
Holdoff Time tHOLDOFF Data/clock sensing off during this period 2.5 μs
LVTTL/LVCMOS CONTROL INPUTS (DRVR_EN, MODE)
Input-High Voltage VIH 2.0 V
Input-Low Voltage VIL 0.8 V
Input-High Current IIH VIH(MIN) < VIN -1 +1 μA
Input-Low Current IIL VIN < VIL(MAX) -1 +1 μA
Note 1:While the MAX3816A is operable over the continuous range of 3.0V to 5.5V, the DDC application requires VCCconnection to
DDC +5V.
Note 2:All levels in the cable side clock and data I/O are referenced to GND_REF, unless otherwise noted.
Note 3:All levels in the display side clock and data I/O are referenced to VSS, unless otherwise noted.
Note 4:Rise time measured 30% to 70%; fall time measured 70% to 30%. Load range is 60pF to 3000pF on source side, and 10pF
to 400pF on display side. Pullup resistors are chosen to supply I2C maximum of 3mA when asserting low state.
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +5.5V, VDD= +3.0V to +5.5V, TA= 0°C to +70°C. Typical values are at TA= +25°C, VCC= +5.0V, VDD= +3.3V,
unless otherwise noted.)
ICC vs. VCC
MAX3816A toc01
VCC (V)
ICC
(mA)
100kbps DATA, 100kHz CLOCK,
INCLUDES 3.3kΩ PULLUP RESISTORS
CABLE CLOAD = 3000pF
CABLE CLOAD = 60pF
IDD vs. VDD
MAX3816A toc02
VDD (V)
(mA)
100kbps DATA, 100kHz CLOCK, INCLUDES
3.3kΩ PULLUP RESISTORS FOR 5V SUPPLY
RANGE AND 2.2kΩ PULLUP RESISTORS FOR
3.3V SUPPLY RANGE
DISPLAY CLOAD = 330pF
DISPLAY CLOAD = 10pF
MAX3816A toc03
1V/div
2μs/div
3.3kΩ PULLUP RESISTOR AT EACH END OF CABLE.
PULLDOWN SOURCE: 25Ω CMOS SWITCH SIGNAL
INITIATED AND MEASURED AT REMOTE SOURCE.
CLOCK_C TRANSIENT RESPONSE
WITH AND WITHOUT MAX3816A, 30m CABLE LOAD
(2350pF)
WITH
MAX3816A
WITHOUT
MAX3816A
Typical Operating Characteristics
(VCC= +5.0V, VDD = +3.3V, TA= +25°C, unless otherwise noted.)
MAX3816A2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
Typical Operating Characteristics (continued)
(VCC= +5.0V, VDD = +3.3V, TA= +25°C, unless otherwise noted.)
MAX3816A toc04
1V/div
2μs/div
3.3kΩ PULLUP RESISTOR AT EACH END OF CABLE.
PULLDOWN SOURCE: 25Ω CMOS SWITCH SIGNAL
INITIATED AND MEASURED AT REMOTE SOURCE.
CLOCK_C TRANSIENT RESPONSE
WITH AND WITHOUT MAX3816A, 30m CABLE LOAD
(3100pF)
WITH
MAX3816A
WITHOUT
MAX3816A
MAX3816A toc05
1V/div
2μs/div
3.3kΩ PULLUP RESISTOR AT EACH END OF CABLE.
PULLDOWN SOURCE: 25Ω CMOS SWITCH SIGNAL
INITIATED AND MEASURED AT REMOTE SOURCE.
CLOCK_C TRANSIENT RESPONSE
WITH AND WITHOUT MAX3816A, 60m CABLE LOAD
(4700pF)
WITH
MAX3816A
WITHOUT
MAX3816A
MAX3816A toc06
1V/div
2μs/div
3.3kΩ PULLUP RESISTOR AT EACH END OF CABLE.
PULLDOWN SOURCE: 25Ω CMOS SWITCH SIGNAL
INITIATED AND MEASURED AT REMOTE SOURCE.
DATA_C TRANSIENT RESPONSE
WITH AND WITHOUT MAX3816A, 60m CABLE LOAD
(4700pF)
WITH
MAX3816A
WITHOUT
MAX3816A
MAX3816A toc07
1V/div
2μs/div
PULLUP RESISTORS: TWO 3.3kΩ IN PARALLEL.
PULLDOWN SOURCE: 25Ω CMOS SWITCH.
CLOCK_C TRANSIENT RESPONSE
WITH AND WITHOUT MAX3816A, 62pF CABLE LOAD
WITH
MAX3816A
WITHOUT
MAX3816A
CABLE SIDE TRANSITION TIME
vs. CABLE CAPACITANCE
MAX3816A toc08
CAPACITANCE (pF)
30% TO 70% RISE OR FALL (ns)
VCC = 5V, 3.3kΩ PULLUP RESISTOR AT EACH
END OF CABLE
RISE TIME
FALL TIME
MAX3816A2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
MAX3816A toc09
VIDEO SOURCE
CLOCK
5V/div
VIDEO SOURCE
DATA
5V/div
DISPLAY CLOCK
5V/div
DISPLAY DATA
5V/div
2μs/div
50m CABLE ON SOURCE SIDE, 330pF CAPACITANCE
ON DISPLAY SIDE, VCC = 5V, VDD = 5V CLOCK AND
DATA INITIATED AT VIDEO SOURCE AND MEASURED
AT MAX3816A
SERIES MODE TRANSIENT RESPONSE
(3000pF CABLE CAPACITANCE)
MAX3816A toc10CLOCK_C AT
MAX3816A
2V/div
CLOCK_C AT
REMOTE CLIENT
2V/div
1μs/div
REFLECTION
ABERRATION AT
CLOCK_C PIN
NOT SEEN AT SOURCE
ACTUAL SIGNAL
AT VIDEO SOURCE
60m CABLE, SIGNAL INITIATED AT DISPLAY SIDE
REFLECTION ABSORBED BY MAX3816A
VHOLD vs. (VSS - GND_REF)
MAX3816A toc11
VSS - GND_REF (V)
HOLD
(% OF SUPPLY VOLTAGE)
DISPLAY SIDE (REFERENCED
TO VDD RELATIVE TO VSS)
CABLE SIDE (REFERENCED
TO VDD RELATIVE TO GND_REF)
VTRIGIL vs. (VSS - GND_REF)
MAX3816A toc12
VSS - GND_REF (V)
TRIGIL
(% OF SUPPLY VOLTAGE)
DISPLAY SIDE
(REFERENCED TO VDD)
CABLE SIDE
(REFERENCED TO VCC)
Typical Operating Characteristics (continued)
(VCC= +5.0V, VDD = +3.3V, TA= +25°C, unless otherwise noted.)
MAX3816A2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
Pin Description
PINNAMEFUNCTION
1 DRVR_EN Driver Enable Input, LVTTL/LVCMOS. Set high to enable all data and clock drivers for normal
operation. Set low to disable drivers, permitting isolation of cable bus from display bus.
2 VCCPower Supply for Cable Side. In the DDC application, connect to DDC +5V. Connect 10μF or larger
bypass capacitor as shown in Figure 6.
3 CLOCK_C I2C Cable-Side Clock with Cable Driver, CMOS Input/Output. Connect a 47k pullup resistor to VCC.
4 GND_REF
Cable-Side Ground Return. Connect directly to cable DDC ground wire. The MAX3816A circuitry uses
the video source DDC GND as a threshold reference. Also connect 10μF or larger bypass capacitors
as shown in Figure 6.
5 DATA_C I2C Cable-Side Data with Cable Driver, CMOS Input/Output. Connect a 47k pullup resistor to VCC.GND_REF Cable-Side Ground Return (Alternate). Connected internally to pin 4 above.
7 VCC Power Supply for Cable Side (Alternate). Connected internally to pin 2 above.
8, 9, 10 DNC Do Not Connect
11 VDD Power Supply for Display Side and Core Circuitry. Connect bypass capacitor as shown in Figure 6.
12 DATA_D I2C Display-Side Data, CMOS Input/Output. Connect a 2.2k pullup resistor to VDD for VDD = 3.3V,
or a 3.3k pullup resistor to VDD for VDD = 5V.
13 VSS Ground for Display Side and Core Circuitry. Connect bypass capacitors as shown in Figure 6.
14 CLOCK_D I2C Display-Side Clock, CMOS Input/Output. Connect a 2.2k pullup resistor to VDD for VDD = 3.3V,
or a 3.3k pullup resistor to VDD for VDD = 5V.
15 VSS_T Must Be Connected to VSS for Normal Operation
16 MODE Mode Setting Input, LVTTL/LVCMOS. Force high for parallel mode (normal operation) and force low for
serial operation.
Theory of Operation
The MAX3816A has parallel and series modes. The
parallel mode is preferred for applications where high
tolerance to noncompliant source and sink devices is
desired (noncompliant VOLfrom displays and noncom-
pliant VIHfrom sources are common). Further, the par-
allel mode can be operated with other speed-up
devices on the same bus, either active (DRVR_EN = HI)
or in bypass (DRVR_EN = LO).
Series mode is preferred for applications where high
tolerance to ground offset or noise between and source
and sink is needed. Series mode also isolates display
circuits from transmission line reflections in very long
cables, providing full isolation between cable and dis-
play buses. For in-display applications, series mode
can provide level shifting between the 5V cable DDC
and 3.3V display internal DDC.
A single MAX3816A is applied at the display side of the
video link to compensate for excessive cable capaci-
tance. The overall operation of the MAX3816A, for
either the DATA or CLOCK signal, can be summarized
as follows (Figures 1a and 1b).High state. Drivers off. Level sensing on.
If no client device is controlling the “wired-AND” bus
from either the source or display side, all device dri-
vers are off and the bus (including the MAX3816A)
is waiting in the high state. The pullup resistors on
each side are holding the bus up to VCCon the
source side and VDDon the display side.High-to-low transition. Drivers assert low. Level
sensing off (Holdoff).
A change of state is initiated by any device driver
pulling low. Once the signal transitions below 75%
of the power supply, the MAX3816A drives both the
source and display sides toward ground with a low-
impedance driver, level sensing is turned off, and
the holdoff timer is started. The source side is
pulled down to the level of the VSS. This is accom-
plished using a low-impedance n-channel buffer
that is designed to drive a 1 meter (60pF) to 60
MAX3816A2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
meter (> 3000pF) cable with a controlled slew-rate.
Similarly, the display side is pulled down to VSSwith
a controlled slew rate, open-drain n-channel MOS
device. These buffers stay on for 1.75µs.Low state. Level sensing off (Holdoff).
Level sensing remains off until the completion of the
holdoff period, which is 2.5µs on both the clock and
data channels.
In series mode, drivers maintain low level (at or
below VHOLD). Either the client pulldowns sustain
the level below VOL, or the MAX3816A sustains the
level at VHOLDif no other driver on the same node
is pulling down. This action is in support of the
“wired-AND” function across source and display
sides.Low state, drivers off. Level sensing on.
After the MAX3816A holdoff time completes, level
sensing resumes.
In series mode, the MAX3816A supports a “wired-
AND” connection between source and display
sides; returning to the high state is supported only
when all client sources turn off. If either the source
or display side releases the bus, but not both, a
MAX3816A level-sensing buffer senses the transi-
tion at VTRIGIL, supporting the existing low state by
clamping the voltage to VHOLDand waiting for the
remaining side to release the bus.Low-to-high transition. Drivers on. Level sensing
off (Holdoff).
A change of state is initiated when no device is
holding the bus low on both source and display
sides. When both sides exceed their respective
VTRIGILlevels, the source side turns on a slew-rate
controlled open-drain p-channel device, pulling up
to VCCfor 1.75µs. Simultaneously, the display side
is released and the pullup resistors pull the display-
side bus up to VDD, as per normal I2C operation.High state. Drivers off. Level sensing off
(Holdoff).
During holdoff, no transitions are sensed. The high
state is maintained by external pullup resistors. Upon
the end of holdoff, when the cable and display levels
are above 85%, the state machine transitions to state
(1); otherwise, it waits until levels raise above 85% to
transition to state (1). Data, but not clock, has anoth-
er exit from state (6) to (1) upon data source or data
display levels dropping below 60%.
I2C continuous clock applications are not recommend-
ed for the MAX3816A. The MAX3816A is optimized for
DDC applications with a noncontinuous clock.
Detailed Description
The MAX3816A DDC/I2C 2-wire extender consists of
two controllers with level-shifters, cable drivers, display
drivers, and level-sensing circuitry (Figure 2).
Controllers and Level Shifters
The MAX3816A functionality is governed by two con-
trollers, one for CLOCK and one for DATA. Bidirectional
signaling is fully supported on both CLOCK and DATA.
The primary function of the controllers is to receive the
state-change information from the source- and display-
side level-sense circuitry and support the “wired-AND”
function between the two. When the state changes, a
holdoff period is timed during which the source and
display drivers assert the next state, high or low, and all
input sensing is ignored while I/O transients settle
(Figure 3). The holdoff period is approximately 2.5µs.
The cable transmission-line termination feature is active
only during the first 1.75µs of holdoff, sufficiently long
enough to absorb roundtrip reflections from a 60m
cable.
In series mode, the CLOCK and DATA controllers iso-
late the source electronics from the display electronics.
The cable side of the MAX3816A is referenced to VCC
and GND_REF, and the display side is referenced to
VDDand VSS. This power scheme provides tolerance to
offset and noise between the source and display
devices.
Cable Drivers
The low-impedance cable drivers (Figure 10) can
charge and discharge at least 3000pF of capacitive
cable load within the I2C rise and fall time limits. The
drivers each incorporate a slew-rate limiter to control
the amount of high-frequency energy transmitted. The
cable drivers also provide a back termination imped-
ance of approximately 60Ωto absorb transmission-line
reflections returning to the driver. The cable drivers
each include a high-state current-limiting feature to
clamp the output current to less than 16mA.
After 1.75µs of driver assertion, following a decision to
transition, the low-impedance drivers are turned off.
Subsequently, when another device asserts a new
state, it does not have to work against the low imped-
ance of the MAX3816A.
MAX3816A2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
LOW
STATE
HIGH
STATE
CLOCK_D > 17.5% AND CLOCK_C > 12.5%
CLOCK_C “OR” CLOCK_D < 75%
NOTES:
1) STATE CHANGE CONDITIONS ARE IN ITALICS. TRANSITION ACTIONS ARE UNDERLINED.
2) THE DATA CHANNEL STATE MACHINE IS IDENTICAL AND SYMMETRIC, EXCEPT THAT HOLDOFF TIME IS 2.0μs INSTEAD OF 2.5μs.
ALSO, IN ADDITION TO THE 85% CONDITION TO EXIT STATE 6, DATA HAS AN ADDITIONAL EXIT: DATA_C “OR” DATA_D < 60%.
3) DEPENDENT ON MODE PIN 16: MODE = LOW FOR SERIAL OPERATION (DRIVERS HOLD); MODE = HIGH FOR PARALLEL OPERATION (DRIVERS OFF).
HOLDOFF TIMER = START
HOLDOFF TIMER = START
SENSE OFF
DRIVERS ON
SENSE OFF
DRIVERS OFF
SENSE ON
(NOTE 3)
RAMP
RAMP
DOWN
SENSE OFF
(NOTE 3)
SENSE ON
DRIVERS OFF
SENSE OFF
DRIVERS ON
HOLDOFF TIMER = 1.75 sμ
HOLDOFF TIMER = 1.75 sμHOLDOFF TIMER ≥ 2.5 s
“AND”
CLOCK_C “AND” CLOCK_D > 85%
HOLDOFF TIMER = 2.5 sμ
Figure 1a. Clock State Machine Diagram
Locally, connect a 47kΩpullup resistor from CLOCK_C
and DATA_C to VCC. This assumes that a 1.65kΩ
pullup resistor resides at the opposite end of each
channel.
Display Drivers
The display drivers (Figure 11) are typical open-drain
pulldown devices capable of discharging up to 400pF
of capacitive load within the I2C fall-time limits.
Locally, connect a 2.2kΩpullup resistor from CLOCK_D
and DATA_D to VDDfor VDD= 3.3V, or a 3.3kΩpullup
resistor to VDDfor VDD= 5V.
Level Sense
The MAX3816A’s level-sensing circuitry monitors the
incoming data for state transitions. When the CLOCK or
DATA signal is high and drops below VTRIGIH, the con-
troller ramps the outputs low. When the DATA and
CLOCK are low and both rise above VTRIGIL, refer-
enced to GND_REF on the source side or VSSon the
display side, the output drives the level high.
MAX3816A2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
VXX
DDC VIH = 70% VXX
DDC VIL = 30% VXX
DDC VOL(max) = 0.4V
GND
GND
VXX
DDC VIH = 70% VXX
DDC VIL = 30% VXX
DDC VOL(max) = 0.4V
CABLE/
SOURCE
SIDE
(NOTE 1)
STATE
NUMBER
DISPLAY
SIDE
(NOTE 1)
VTRIGIH = 75% VXX
0μsHOLDOFF TIMER
NOTES:
1) THIS EXAMPLE APPLIES TO TRANSMISSION IN EITHER DIRECTION. SOURCE TO DISPLAY IS SHOWN.
2) VXX IS USED GENERICALLY FOR THE VOLTAGE AT THE VCC OR VDD PINS.
VTRIGIH = 12.5% VCC CLOCK_C,
17.5% VDD CLOCK_D
VHOLD = 15% VCC CLOCK_C,
20% VDD CLOCK_D
0μs1.75μs2.5μs1.75μs2.5μs124
Figure 1b. Signal Waveform Example Showing States

Partno	Mfg	Dc	Qty	Available	Descript
MAX3816ACUE+	MaximIC	N/a	1337	avai	I²C 2-Wire Extender for DDC in DVI, HDMI, and VGA Interfaces