MAX3786UTJ-T ,1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and EqualizationELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = 0°C to +85°C. Typical values at V = +3.3V, T = + ..
MAX3787ABL ,1Gbps to 12.5Gbps Passive Equalizer for Backplanes and CablesApplications Pin ConfigurationBackplane Interconnect CompensationTOP VIEW1 2 3Cable Interconnect Co ..
MAX3787ABL-T ,1Gbps to 12.5Gbps Passive Equalizer for Backplanes and CablesFeaturesThe MAX3787 is a 1Gbps to 12.5Gbps equalization ♦ No Power Supply Requirednetwork that comp ..
MAX378CPE ,High-Voltage, Fault-Protected Analog MultiplexersFeatures' Fault Input Voltage ±75V with Power Supplies OffThe MAX378 8-channel single-ended (1-of-8 ..
MAX378EJE ,High-Voltage, Fault-Protected Analog MultiplexersELECTRICAL CHARACTERISTICS (continued)(V+ = +15V, V- = -15V; V (Logic Level High) = +2.4V, V (Logic ..
MAX3795ETG ,3.3 V +/-10%, 1 to 4.25 Gbps multirate VCSEL driver with diagnostic monitorfeatures.♦ 2mA to 15mA Modulation CurrentThe automatic power control (APC) adjusts the laser♦ 1mA t ..
MAX736CWE ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorsFeatures
. Pre-Set -5V, -12V, -15V or Adjustable Outputs
. Convert Positive Voltages to Negative
..
MAX736EPD ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorsGeneral Description
The MAX736/MAX737/MAX739/MAX759 are CMOS, in-
verting, switch-mode regulato ..
MAX736EWE ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorslVI/lXI/VI
-5V, -12V, -15V, and Adjustable
Inverting Gurrent-Mode PWM Regulators
MAX7375AXR365+T ,3-Pin Silicon OscillatorApplicationsMAX7375AXR375-T -40°C to +125°C 3 SC70-3● White Goods ● Portable EquipmentMAX7375AXR405 ..
MAX7375AXR425+T ,3-Pin Silicon OscillatorFeaturesThe MAX7375 is a silicon oscillator, intended as a low-cost ● 2.7V to 5.5V Operationimprove ..
MAX7375AXR805+ ,3-Pin Silicon Oscillatorapplications.● ±10mA Output Drive CurrentThe MAX7375 is a fully integrated oscillator, supplied at ..
MAX3786UTJ-MAX3786UTJ+-MAX3786UTJ+T-MAX3786UTJ-T
1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization
General DescriptionThe MAX3786 is an AC-coupled, serial-ATA (SATA)-
compatible, 1.5Gbps multiplexer/buffer (mux/buffer) IC
that provides the capability to switch a single serial
data signal between two redundant I/O channels.
SATA out-of-band (OOB) signaling is supported using
loss-of-signal (LOS) detect on all three inputs and
shutdown on the corresponding outputs. The high-speed
inputs and outputs are all internally terminated, compati-
ble with 100Ωdifferential systems, and must be AC-cou-
pled to the controller IC and SATA-compatible disk drive.
Receive equalization (EQ) and transmit preemphasis
(PE) are provided on the dual I/O channels to mitigate
the effects of intersymbol interference in the signal
path. Loopback can be enabled on the nonselected
I/O channel.
The MAX3786 operates from a single +3.3V supply and
typically consumes 520mW with PE and EQ enabled. It
is available in a 5mm x 5mm, 32-lead thin QFN
exposed-pad package and operates over a 0°C to
+85°C temperature range.
Applications1.5Gbps Serial ATA Redundancy
Features< 50psP-PTotal Residual Jitter (20in FR-4, EQ
and PE On)Supports SATA OOB SignalingLoopback of Nonselected ChannelReceive Equalization and Transmit Preemphasis
on Controller-Side I/O Channels0°C to +85°C Operation32-Pin, 5mm ✕5mm Thin QFN Package+3.3V Power Supply
MAX3786
1.5Gbps Serial ATA-Compatible Mux/Buffer with
Loopback and Equalization
Ordering InformationMAX3786
OUT1CONTROLLER 1
CONTROLLER 2
DISK DRIVE
2in TO 24in FR-4
2in TO 24in FR-4
IN1
IN0OUT0
SATA
CONNECTOR
SATA
CONNECTOR
CONNECTORCONNECTOR
CONNECTORCONNECTOR
Typical Application Circuit19-2727; Rev 2; 6/04
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEPKG CODEMAX3786UTJ0°C to +85°C32 Thin QFN-EP*
(5mm × 5mm)T3255-2
MAX3786UTJ+0°C to +85°C32 Thin QFN-EP*
(5mm × 5mm)—
Pin Configuration and Functional Diagram appear at end of data sheet.+Denotes lead-free package.
*EP = Exposed pad.
MAX3786
1.5Gbps Serial ATA-Compatible Mux/Buffer with
Loopback and Equalization
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC...................................……...-0.5V to +5.0V
Continuous Current at Outputs
(TX±, OUT1±, OUT0±)............................………………±22mA
Input Voltage
(RX±, IN1±, IN0±)..................................-0.5V to (VCC+ 0.5V)
Differential Input Voltage
(RX±, IN1±, IN0±)...................................………………..±2.0V
Voltage at PE1EN, PE0EN, EQ1EN, EQ0EN,
LB_EN, SEL, CM1, CM0.........................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
32-Pin Thin QFN (derate 21.3mW/°C above +85°C).1384mW
Operating Temperature Range....................………0°C to +85°C
Storage Temperature Range.......................…..-55°C to +150°C
Lead Temperature (soldering, 10s).............……………..+300°C
ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSEQ and PE off125150Supply CurrentICCEQ and PE on158220mA
Maximum Data Rate(Note 1)1.5Gbps
Differential Input Voltage
(RX, IN1, IN0)(Note 2)250600mVP-P
Input TerminationDifferential85100115Ω
Input Return Loss|S11|100MHz to 2.5GHz14dB
Input EqualizationAt 750MHz4.5dB
PE off400500600Differential Output Voltage
(TX, OUT0, OUT1) (Note 2)Output disabled by OOB signaling30mVP-P
Output TerminationSingle ended to VCC42.55057.5Ω
Output Transition Time1.5Gbps data, 20% to 80% (Notes 1, 3)135200270ps
Output PreemphasisAt 750MHz (Note 4)4.5dB
Output JitterDJ + 14RJ, EQ and PE off (Notes 1, 5, 8)3040psP-P
Total Residual JitterDJ + 14RJ, EQ and PE on (Notes 1, 6, 8)4050psP-P
Differential Output Skew(Note 1)20ps
LOS Detector Threshold50150mVP-P
Output Startup/Shutdown Time(Note 7)5ns
LVCMOS Input High VoltageVIH1.5V
MAX3786
1.5Gbps Serial ATA-Compatible Mux/Buffer with
Loopback and Equalization
ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSLVCMOS Input Low VoltageVIL0.5V
LVCMOS Input High CurrentIOHVIH = +2.0V to (VCC + 0.3V)150µA
LVCMOS Input Low CurrentIOLVIL = -0.3V to +0.8V150µA
Note 1:AC specifications are guaranteed by design and characterization.
Note 2:Differential voltage is defined as VP-P= (V+ - V-). Inputs and outputs must be AC-coupled for proper operation.
Note 3:Output transition time measured using a 0000011111 pattern, with transmit PE off.
Note 4:Transmit PE compensates for 20in of 6-mil-wide differential stripline in FR-4 or equivalent path loss.
Note 5:Jitter after paths from RX to OUT_ or IN_ to TX. Measured with no jitter on the input, using a ±K28.5 pattern, and a path con-
sisting of the MAX3786 alone.
Note 6:Jitter after EQ for the paths from RX to OUT_ or IN_ to TX. Measured with no jitter on the input, using a ±K28.5 pattern, and a
path consisting of the MAX3786 plus 20in of 6-mil-wide differential stripline in FR-4 on the output.
Note 7:Total time for LOS to enable/disable the outputs.
Note 8:Measured with a 100mV sinusoidalcommon-mode signal in the 2MHz ≤f ≤200MHz range.
Typical Operating Characteristics(VCC= 3.3V, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATUREMAX3786 toc01
TEMPERATURE (°C)
CURRENT (mA)70506020304010
PE AND EQ ON
PE AND EQ OFF
DIFFERENTIAL INPUT RETURN LOSS
MAX3786 toc02
FREQUENCY (GHz)
|S11| (dB)
TOTAL RESIDUAL JITTER vs. PATH LENGTH
(FR-4 STRIPLINE AT OUT0, ±K28.5 PATTERN)MAX3786 toc03
FR-4 LENGTH (in)
TOTAL RESIDUAL JITTER (ps
P-P2051015
030
MAX3786
1.5Gbps Serial ATA-Compatible Mux/Buffer with
Loopback and EqualizationOUTPUT SWING vs. INPUT SWING
(±K28.5 PATTERN)
MAX3786 toc04
INPUT SWING (mVP-P)
OUTPUT SWING (mV
P-P
OUTPUT EYE DIAGRAM, TRANSMIT PE ON
(10in FR-4 STRIPLINE
AT OUT0, ±K28.5 PATTERN)70mV/div
MAX3786 toc06
100ps/div
OUTPUT EYE DIAGRAM, RECEIVE EQ ON
(10in FR-4 STRIPLINE
AT IN0, ±K28.5 PATTERN)70mV/div
MAX3786 toc05
100ps/div
OUTPUT EYE DIAGRAM, TRANSMIT PE ON
(20in FR-4 STRIPLINE
AT OUT0, ±K28.5 PATTERN)70mV/div
MAX3786 toc08
100ps/div
OUTPUT EYE DIAGRAM, RECEIVE EQ ON
(20in FR-4 STRIPLINE
AT IN0, ±K28.5 PATTERN)70mV/div
MAX3786 toc07
100ps/div
ypical Operating Characteristics (continued)(VCC= 3.3V, TA= +25°C, unless otherwise noted.)
Detailed DescriptionThe MAX3786 consists of three multiplexers, I/O buffers,
and LOS-detection circuitry (see the Functional Diagram).
The buffers on the controller side provide EQ on the
inputs and PE on the outputs.
Mux/Buffer LogicBy means of the LVCMOS input SEL, a SATA-compati-
ble device at TX/RX can be connected to either
IN0/OUT0 or IN1/OUT1. When SEL is low, TX/RX are
connected to IN0/OUT0, and when SEL is high, TX/RX
are connected to IN1/OUT1. Use of the SEL input pro-
vides the ability to operate a single SATA disk drive
from redundant controllers. Loopback is provided on
the IN_/OUT_ side and is controlled by the LVCMOS
input LB_EN. When LB_ENis low, the nonselected
IN_/OUT_ loops back (see Table 1). The SEL and
LB_ENcontrol lines are internally pulled high through
40kΩresistors (see the Functional Diagram).
Loss-of-Signal LogicAt each high-speed input to the MAX3786, an LOS cir-
cuit is provided. In this circuit, a differential signal of
50mVP-Por less is detected as OFF, and a signal of
greater than 150mVP-Pis detected as ON. The LOS
detectors, in combination with the select logic, control
their associated high-speed output-disable circuits, so
MAX3786
1.5Gbps Serial ATA-Compatible Mux/Buffer with
Loopback and Equalization
Pin Description
PINNAMEFUNCTION1, 4, 8, 15,
17, 20, 21,
24, 26, 30
VCC+3.3V Supply VoltageTX+Positive TX Data Output, CML. Serial ATA compatible.TX-Negative TX Data Output, CML. Serial ATA compatible.SELMultiplex Select Control Input, LVCMOS. Set high to connect RX/TX to OUT1/IN1.RX-Negative RX Data Input, CML. Serial ATA compatible.RX+Positive RX Data Input, CML. Serial ATA compatible.PE1ENChannel 1 Preemphasis Enable Input, LVCMOS. Set low to enable OUT1 PE.EQ1ENChannel 1 Equalization Enable Input, LVCMOS. Set low to enable IN1 EQ.LB_ENLoopback Enable Input, LVCMOS. Set low to loopback data on nonselected channel.CM1Input 1 Common-Mode Point. Normally not connected; can be connected to VCC through 1.0µF
capacitor. See Figure 1.IN1-Negative Channel 1 Data Input, CML. Serial ATA compatible.IN1+Positive Channel 1 Data Input, CML. Serial ATA compatible.
16, 25GNDSupply GroundOUT1-Negative Channel 1 Data Output, CML. Serial ATA compatible.OUT1+Positive Channel 1 Data Output, CML. Serial ATA compatible.OUT0-Negative Channel 0 Data Output, CML. Serial ATA compatible.OUT0+Positive Channel 0 Data Output, CML. Serial ATA compatible.IN0-Negative Channel 0 Data Input, CML. Serial ATA compatible.IN0+Positive Channel 0 Data Input, CML. Serial ATA compatible.CM0Input 0 Common-Mode Point. Normally not connected; can be connected to VCC through 1.0µF
capacitor. See Figure 1.EQ0ENChannel 0 Equalization Enable Input, LVCMOS. Set low to enable IN0 EQ.PE0ENChannel 0 Preemphasis Enable Input, LVCMOS. Set low to enable OUT0 PE.Exposed
pad
Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and
electrical performance.
MAX3786that OOB signaling is transmitted through the MAX3786
(see Table 1). The time for the LOS circuit to detect an
inactive input and disable the associated output, or
detect an active input and enable the output, is less
than 5ns.
Equalization and PreemphasisHigh-speed inputs IN0 and IN1 have integrated equal-
ization, and high-speed outputs OUT0 and OUT1 have
integrated PE to mitigate the effects of intersymbol
interference in an FR-4 transmission line signal path.
These circuits provide EQ or PE that matches the typi-
cal path loss of a 20in, 6-mil FR-4 differential stripline.
Four active-low LVCMOS inputs, EQ0EN, EQ1EN,
PE0EN, and PE1ENare provided to enable EQ and PE
independently. All four control lines are internally pulled
high through 40kΩresistors (see the Functional
Diagram). EQ and PE should be enabled when the total
path loss exceeds approximately 2.5dB.
Input TerminationsAll high-speed inputs accept current-mode logic (CML)
and are SATA compatible. The inputs contain internal
100Ωdifferential termination, and must be AC-coupled
to the controller IC and SATA-compatible disk drive for
proper operation.
Two pins (CM0 and CM1) provide access to the IN0
and IN1 common-mode points. CM0 and CM1 are nor-
mally left unconnected; however, a capacitor up to
1.0µF can be connected from each CM_ pin to VCC,
providing a low-impedance AC common-mode path to
VCC(see Figure 1).
Output TerminationsThe MAX3786 uses CML for its high-speed outputs.
They are SATA compatible and provide 50Ωtermina-
tions to VCC(see Figure 2). The high-speed outputs
must be AC-coupled to the controller IC and SATA-
compatible disk drive for proper operation.
Applications Information
Hot SwapThe MAX3786 is designed so that arbitrary sequencing
of VCCand I/O signals during startup does not affect
operation of the part.
Exposed-Pad PackageThe MAX3786 is available in a 5mm ✕5mm, 32-pin thin
QFN package with EP for signal integrity and place-
ment flexibility. The exposed pad provides thermal and
electrical connectivity to the IC, and must be soldered
to a high-frequency ground plane. It is recommended
to use at least nine vias to connect the ground pad
underneath the 32-lead thin QFN package to the PC
board ground plane.
Layout ConsiderationsUse controlled-impedance transmission lines to inter-
face with the MAX3786 high-speed inputs and outputs.
Power-supply decoupling capacitors should be placed
as close as possible to the VCCpins.
1.5Gbps Serial ATA-Compatible Mux/Buffer with
Loopback and EqualizationMAX3786
VCC
VCC
VCC
IN_+
CM_
IN_-
50Ω
50Ω2pF0.2mA
1.6kΩ
Figure 1. Input Structure (IN0, IN1)
50Ω50Ω
VCC
OUT_+
OUT_-
MAX3786
Figure 2. Output Structure (OUT0, OUT1)
