MAX3785UTT+ Fast Delivery |IC PHOENIX CO.,LIMITED

MAX3785UTT+ ,6.25Gbps, 1.8V PC Board EqualizerApplicationsPin ConfigurationsHSBI for ≤ 6.4GbpsTOP VIEW (BUMPS ON BOTTOM OF DIE)Double IEEE 802.3a ..
MAX3786UTJ ,1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and EqualizationMAX378619-2727; Rev 2; 6/041.5Gbps Serial ATA-Compatible Mux/Buffer withLoopback and Equalization
MAX3786UTJ+ ,1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and EqualizationApplications+Denotes lead-free package.*EP = Exposed pad.1.5Gbps Serial ATA RedundancyTypical Appli ..
MAX3786UTJ+T ,1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and EqualizationFeaturesThe MAX3786 is an AC-coupled, serial-ATA (SATA)-♦ < 50ps Total Residual Jitter (20in FR-4, ..
MAX3786UTJ-T ,1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and EqualizationELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = 0°C to +85°C. Typical values at V = +3.3V, T = + ..
MAX3787ABL ,1Gbps to 12.5Gbps Passive Equalizer for Backplanes and CablesApplications Pin ConfigurationBackplane Interconnect CompensationTOP VIEW1 2 3Cable Interconnect Co ..
MAX736CPD ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM Regulatorsapplications. The MAX736/MAX737/MAX739 have fixed outputs of -12V, -15V, and -5V respectively. ..
MAX736CPD ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM Regulatorsfeatures, along with high efficiency and an application circuit that lends itself to miniaturizat ..
MAX736CPD+ ,-12V, Inverting, PWM, Current-Mode DC-DC Converterapplications. The MAX736/MAX737/MAX739 have fixed outputs of -12V, -15V, and -5V respectively. ..
MAX736CWE ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorsFeatures . Pre-Set -5V, -12V, -15V or Adjustable Outputs . Convert Positive Voltages to Negative ..
MAX736EPD ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorsGeneral Description The MAX736/MAX737/MAX739/MAX759 are CMOS, in- verting, switch-mode regulato ..
MAX736EWE ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorslVI/lXI/VI -5V, -12V, -15V, and Adjustable Inverting Gurrent-Mode PWM Regulators

MAX3785UTT+
6.25Gbps, 1.8V PC Board Equalizer
MAX3785
6.25Gbps, 1.8V PC Board Equalizer
19-2630; Rev 4; 10/08
General Description
The MAX3785 6.25Gbps equalizer operates from a sin-
gle 1.8V supply and compensates for transmission-
medium losses encountered with FR-4 transmission
lines. Optimized for low-voltage, high-density, DC-cou-
pled interconnections between the line card and switch
card, the MAX3785 enables a system upgrade path
while maintaining a legacy rate of 2.5Gbps to
3.125Gbps. Roughly the size of two 0603 passive com-
ponents, the MAX3785 easily provides placement and
routing flexibility.
The MAX3785 is composed of an equalizer, limiting
amplifier, and output driver. For data rates of 3.2Gbps
and lower, the MAX3785 equalizes signals for spans up
to 40in of FR-4 board material. For data rates up to
6.25Gbps, the MAX3785 compensates for 30in of FR-4
board material. The MAX3785 is coding independent,
functioning equally well for 8b/10b or scrambled signals.
The MAX3785 features DC-coupled current-mode logic
(CML) data inputs and outputs. It is packaged in a tiny
1.5mm ×1.5mm chip-scale package (UCSP™) and a
6-pin TDFN package.
Applications
HSBI for ≤6.4Gbps
Double IEEE 802.3ae XAUI
Double STM-16/OC-48
FeaturesSingle 1.8V SupplyVery Low Power, 60mWSpans 30in with FR-4 at 6.25GbpsOperates from 1.0Gbps to 6.4GbpsCoding Independent, 8b/10b or ScrambledDC-Coupled CML Inputs and OutputsSmall 1.5mm ×1.5mm Footprint
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX3785UBL 0°C to +85°C 6 UCSP (3 3)
MAX3785UWL+ 0°C to +85°C 6 WLP
MAX3785UTT 0°C to +85°C 6 TDFN-EP*
MAX3785UTT+ 0°C to +85°C 6 TDFN-EP*
MAX3785ITT -20°C to +85°C 6 TDFN-EP*
MAX3785ITT+ -20°C to +85°C 6 TDFN-EP*
LINE CARD
MAC
SWITCH CARD
MAX3785OUTIN
1.8V
MAX3785INOUT
SWITCH
ASIC WITH
SERDES
1.8V
BACKPLANE
6.25Gbps
VCC
VCC
30in (0.75m)
Typical Application Circuit
UCSP is a trademark of Maxim Integrated Products, Inc.
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.A2A3C2C3
IN-GNDOUT-
IN+VCCOUT+
MAX3785UBL
MAX3785UTT
3 x 3 UCSPTDFN
TOP VIEW (BUMPS ON BOTTOM OF DIE)
GND
OUT+OUT-6IN+
5VCC
IN-
Pin Configurations
MAX3785
6.25Gbps, 1.8V PC Board Equalizer
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC to GND.................................-0.5V to +6.0V
Continuous Output Current (OUT+, OUT-).......-25mA to +25mA
Input Voltage (IN+, IN-)..............................-0.5V to (VCC+ 0.5V)
Operating Ambient Temperature Range
(UBL, UTB).........................................................0°C to +85°C
Operating Ambient Temperature Range (ITT).....-20°C to +85°C
Storage Ambient Temperature Range...............-55°C to +150°C
Continuous Power Dissipation (TA= +70°C)
6-Pin TDFN (derate 24.4mW above +70°C)..................1.95W
ELECTRICAL CHARACTERISTICS
(Typical values measured at VCC= 1.8V and TA= +25°C. Specifications guaranteed over specified operating conditions.)
(See Operating Conditionstable.)
PARAMETERCONDITIONSMINTYPMAXUNITS
Supply Current 35 55 mA
Input Swing (IN) Measured differentially at data source before
encountering loss (Point A in Figure 1) (Note 1) 400 1600 mVP-P
Input Common-Mode Voltage Range (Note 1) VCC -
(INMAX/4)
VCC -
(INMIN/4) V
Input Return Loss 100MHz to 3.2GHz, power off 15 dB
Differential Input Resistance IN+ and IN- 85 100 115
Output Swing Measured differentially at OUT+ and OUT- with 50
±1% load at each side 450 800 mVP-P
Output Resistance OUT+ or OUT- 42 50 58
Output Return Loss 100MHz to 3.2GHz, IN+ = high 14 dB
Output Transition Time (tr, tf) 20% to 80% (Note 2) 30 40 55 ps
2.5Gbps, 3.2Gbps, 5.0Gbps; 0in to 30in FR-4
400mVP-P IN 1600mVP-P 0.10 0.15
2.5Gbps, 3.2Gbps; 40in FR-4
400mVP-P IN 1600mVP-P 0.15 0.20
6.25Gbps; 0in to 30in FR-4
600mVP-P IN 1600mVP-P 0.15 0.25
Residual Deterministic Jitter
(Notes 1, 3, 4)
6.25Gbps; 0in to 30in FR-4
IN = 400mVP-P 0.20 0.30
Output Random Jitter (Notes 1, 2) 0.75 1.0 psRMS
Low-Frequency Cutoff Frequency 50 kHz
Latency 200 ps
Maximum Bit Rate (Note 1) 6.25 6.4 Gbps
Minimum Bit Rate (Note 1) 1.0 2.5 Gbps
Note 1:Guaranteed by design and characterization.
Note 2:Using input pattern 0000011111 at 6.25Gbps.
Note 3:Difference in deterministic jitter between data source and equalizer output, evaluated at 2.5Gbps, 3.2Gbps, 5Gbps, and
6.25Gbps. Pattern used: PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1.
Note 4:Signal is applied differentially at input to a 6-mil wide, loosely coupled stripline. Deterministic jitter at the output of the
transmission line is from media-induced loss, not from clock source modulation (see Figure 1).
MAX3785
6.25Gbps, 1.8V PC Board Equalizer
Operating Conditions
PARAMETERCONDITIONSMINTYPMAXUNITS
Supply Voltage (VCC)1.711.81.89V
Operating Ambient Temperature (UBL, UTT)02585°C
10Hz ≤ f < 100Hz100
100Hz ≤ f < 1MHz40Supply Noise Tolerance
1MHz ≤ f ≤ 1GHz10
mVP-P
Bit RateNRZ data2.506.25Gbps
Operating Ambient Temperature (ITT)-202585°C
Typical Operating Characteristics
(VCC= +1.8V, TA= +25°C, unless otherwise noted. Measurements done at 6.25Gbps, 500mVP-P at the source with a test pattern:
PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1. Deterministic jitter of the MAX3785 and the board was mea-
sured using Tektronix’s FrameScan™. Deterministic jitter of the system was subtracted from the measured value. Eye diagrams were
acquired by FrameScan, which includes system jitter but eliminates random jitter.)
Figure 1. Conditions of Testing
SIGNAL SOURCE
MAX3785INOUT
PC BOARD
3in ≤ L ≤ 30in
<1.0pF SMA
CONNECTOR
<1.0pF SMA
CONNECTORFR-4
4.0 < εr < 4.4
tanδ = 0.022C
FrameScan is a trademark of Tektronix.
EYE DIAGRAM OF UNEQUALIZED
SIGNAL AFTER 30in OF FR-4
MAX3785 toc01
30ps/div
70mV/div
TEST PATTERN, 6.25Gbps,
WITHOUT RANDOM JITTER,
INCLUDING 13ps SYSTEM JITTER
EYE DIAGRAM OF EQUALIZED
SIGNAL AFTER 30in OF FR-4
MAX3785 toc02
30ps/div
70mV/div
TEST PATTERN, 6.25Gbps,
WITHOUT RANDOM JITTER,
INCLUDING 13ps SYSTEM JITTER
EYE DIAGRAM OF EQUALIZED
SIGNAL AFTER 30in OF FR-4
MAX3785 toc03
30ps/div
70mV/div
210 - 1 PRBS, 6.25Gbps,
WITHOUT RANDOM JITTER,
INCLUDING 13ps SYSTEM JITTER
MAX3785
6.25Gbps, 1.8V PC Board Equalizer
Typical Operating Characteristics (continued)
(VCC= +1.8V, TA= +25°C, unless otherwise noted. Measurements done at 6.25Gbps, 500mVP-P at the source with a test pattern:
PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1. Deterministic jitter of the MAX3785 and the board was measured
using Tektronix’s FrameScan. Deterministic jitter of the system was subtracted from the measured value. Eye diagrams were acquired
by FrameScan, which includes system jitter but eliminates random jitter.)
EYE DIAGRAM OF UNEQUALIZED
SIGNAL AFTER 30in OF FR-4
MAX3785 toc04
50ps/div
70mV/div
TEST PATTERN, 3.125Gbps,
WITHOUT RANDOM JITTER,
INCLUDING 13ps SYSTEM JITTER
EYE DIAGRAM OF EQUALIZED
SIGNAL AFTER 30in OF FR-4
MAX3785 toc05
50ps/div
70mV/div
TEST PATTERN, 3.125Gbps,
WITHOUT RANDOM JITTER,
INCLUDING 13ps SYSTEM JITTER
EYE DIAGRAM OF EQUALIZED
SIGNAL AFTER 30in OF FR-4
MAX3785 toc06
50ps/div
70mV/div
CRPAT, 3.125Gbps,
WITHOUT RANDOM JITTER,
INCLUDING 13ps SYSTEM JITTER
EQUALIZER OPERATING CURRENT
vs. TEMPERATURE
MAX3785 toc07
TEMPERATURE (°C)
CURRENT (mA)70506020304010
DETERMINISTIC JITTER
vs. BOARD LENGTH (FR-4)
(INPUT LEVEL OF 500mVP-P, TEST PATTERN)
MAX3785 toc08
BOARD LENGTH (in)
JITTER (ps)3025201540
2.5Gbps
6Gbps3.125Gbps
5Gbps
DETERMINISTIC JITTER vs. SIGNAL LEVEL
(TEST PATTERN, 30in OF FR-4 BOARD)
MAX3785 toc09
DIFFERENTIAL SIGNAL LEVEL (VP-P)
JITTER (ps)
3.125Gbps2.5Gbps
6.4Gbps
5Gbps
MAX3785
6.25Gbps, 1.8V PC Board Equalizer
Typical Operating Characteristics (continued)
(VCC= +1.8V, TA= +25°C, unless otherwise noted. Measurements done at 6.25Gbps, 500mVP-P at the source with a test pattern:
PRBS (27), ninety-six 0s, 1, 0, 1, 0, PRBS (27), ninety-six 1s, 0, 1, 0, 1. Deterministic jitter of the MAX3785 and the board was measured
using Tektronix’s FrameScan. Deterministic jitter of the system was subtracted from the measured value. Eye diagrams were acquired
by FrameScan, which includes system jitter but eliminates random jitter.)
DETERMINISTIC JITTER vs. DATA RATE
FOR 10in OF FR-4 BOARD
(INPUT LEVEL OF 500mVP-P)
MAX3785 toc10
DATA RATE (Gbps)
JITTER (ps)
210 - 1
27 - 1TEST
PATTERN
K28.5
CRPAT
DETERMINISTIC JITTER vs. DATA RATE
FOR 20in OF FR-4 BOARD
(INPUT LEVEL OF 500mVP-P)
MAX3785 toc11
DATA RATE (Gbps)
JITTER (ps)
210 - 1
27 - 1TEST
PATTERN
K28.5
CRPAT
DETERMINISTIC JITTER vs. DATA RATE
FOR 30in OF FR-4 BOARD
(INPUT LEVEL OF 500mVP-P)
MAX3785 toc12
DATA RATE (Gbps)
JITTER (ps)
210 - 1
27 - 1
TEST PATTERN
K28.5
CRPAT
EQUALIZER INPUT RETURN GAIN (SDD11)
(INPUT SIGNAL LEVEL = -40dBm, POWER OFF)
MAX3785 toc13
FREQUENCY (MHz)
GAIN (dB)
10010,000
EQUALIZER INPUT RETURN GAIN (SDD22)
(INPUT SIGNAL LEVEL = -40dBm, IN+ HIGH)
MAX3785 toc14
FREQUENCY (MHz)
GAIN (dB)
10010,000
MAX3785
Functional Description
The MAX3785 6.25Gbps PC board equalizer consists
of an equalizer, limiting amplifier, offset driver, and off-
set cancellation circuit (see Figure 2). The equalizer
block compensates for the attenuation caused by the
PC board. The limiting amplifier squares up the signal
at the output of the equalizer block. The offset cancella-
tion circuit corrects for internal offset in the limiting
amplifier to minimize pulse-width distortion. This intro-
duces a low-frequency cutoff. The data must achieve a
50% mark/space ratio in less than 100µs. The specified
minimum differential input must be maintained to avoid
oscillation.
Input and Output Structures
An equivalent DC input circuit is shown in Figure 3. It
has an equivalent DC differential input resistance of
100Ω. The output buffer is implemented using current-
mode logic (CML), as shown in Figure 4.
Package Description
The chip-scale package (UCSP) has a bump pitch of
0.5mm (19.7 mils) and a bump diameter of 0.3mm (12
mils). Lay out the solder pad spacing on 0.5mm (19.7
mils), a pad size of 0.25mm (10 mils) and a solder
mask opening of 0.33mm (13 mils). Round or square
pads are permissible. For detailed information on UCSP
layout and handling, go to Maxim’s website,
. The enclosed package descrip-
tion was accurate at the time of publication. For the
MAX3785, all the balls shown in row B of the drawing
are unpopulated. See the Package Informationsection
for the latest package information.
6.25Gbps, 1.8V PC Board Equalizer
PINNAMEFUNCTION (MAX3785UBL)
A1 IN- Negative Data Input, CML
A2 GND Supply Ground
A3 OUT- Negative Data Output, CML
C1 IN+ Positive Data Input, CML
C2 VCC Supply Voltage
C3 OUT+ Positive Data Output, CML
MAX3785UBL Pin Description
PINNAMEFUNCTION (MAX3785UTT)IN- Negative Data Input (CML)
2 GND Supply Ground OUT- Negative Data Output (CML) OUT+ Positive Data Output (CML)
5 VCC Supply Voltage IN+ Positive Data Input (CML)
— EP Exposed Pad
MAX3785UTT Pin Description
Figure 2. Functional Diagram of the MAX3785
EQUALIZER
OFFSET
ADJUST
LIMITER
OUTPUT
BUFFER
MAX3785
OUT+
OUT-
IN+
IN-

Partno	Mfg	Dc	Qty	Available	Descript
MAX3785UTT+ \|MAX3785UTT	MAXIM	N/a	66	avai	6.25Gbps, 1.8V PC Board Equalizer