MAX3770CEE Fast Delivery |IC PHOENIX CO.,LIMITED

MAX3770CEE ,2.125Gbps/1.063Gbps / 3.3V Fibre Channel RepeatersFeaturesThe MAX3770 is a 2.125Gbps Fibre Channel repeater Meet Fibre Channel Jitter Tolerance Requ ..
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MAX3770CEE
2.125Gbps/1.063Gbps / 3.3V Fibre Channel Repeaters
General Description
The MAX3770 is a 2.125Gbps Fibre Channel repeater
IC. The MAX3771 provides a pin-compatible solution
for 1.063Gbps Fibre Channel. Both devices are opti-
mized for use in Fibre Channel arbitrated-loop applica-
tions and operate from a 3.3V supply.
The MAX3770 is compatible with Fibre Channel jitter toler-
ance requirements and can recover data signals with up
to 0.7 unit interval (UI) jitter. The circuit’s fully integrated
phase-locked loop (PLL) provides a frequency lock indi-
cation and does not need an external reference clock.
The MAX3770 provides low-jitter CML clock and data
outputs. To reduce the external parts count, all signal
inputs and outputs are internally terminated. The
MAX3770/MAX3771 are available in 16-pin QSOP
packages.
________________________Applications
2.125Gbps Fibre ChannelStorage Area Networks
1.063Gbps Fibre ChannelFibre Channel Hubs
Fibre Channel Storage Systems
FeaturesMeet Fibre Channel Jitter Tolerance Requirements3.0V to 3.6V OperationInternally Terminated Data and Clock I/OReference Clock Not RequiredFrequency Lock IndicationLow Power Consumption
215mW at 3.3V (MAX3770)
190mW at 3.3V (MAX3771)
MAX3770/MAX3771
2.125Gbps/1.063Gbps, 3.3V
Fibre Channel Repeaters
Pin Configuration
Typical Application Circuit
19-1634; Rev 0; 1/00
Ordering Information
*Future product—contact factory for availability.
MAX3770/MAX3771
2.125Gbps/1.063Gbps, 3.3V
Fibre Channel Repeaters
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, TA= 0°C to +70°C, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:Supply current includes output currents.
Supply Voltage, VCC..............................................-0.5V to +5.0V
Pin Voltage Levels (IN+, IN-, FILT+, FILT-,
LOCKEN, CLKEN, LOCK)....................-0.5V to (VCC+ 0.5V)
LOCK Output Current.........................................-1mA to +10mA
CML Output Currents OUT+, OUT-,
CLK+, CLK-.................................................-22mA to +22mA
Continuous Power Dissipation (TA= +70°C)
16-Pin TQFP (derate 6.7mW/°C above +70°C)..........533mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range.............................-55°C to +150°C
Processing Temperature (die).........................................+400°C
Lead Temperature (soldering, 10s).................................+300°C
MAX3770/MAX3771
2.125Gbps/1.063Gbps, 3.3V
Fibre Channel Repeaters
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, TA= 0°C to +70°C, unless otherwise noted. Typical values are at TA= +25°C.)
Note 2:K28.7+ pattern: 0011111000
Note 3:Compliant random pattern (CRPAT) in hex:
PatternNo. of Occurrences
3EAA2AAAAA6
3EAAA6A5A91
86BA6C6475 D0E8DCA8B4 7949EAA66516
72319A95AB1
C16AAA9AA61
Note 4:K28.5±pattern: 00111110101100000101
Note 5:Random and deterministic jitter generation at 2.125Gbps is measured with 0.38UI deterministic jitter, and 0.22UI random
jitter (BER = 1 x 10-12) applied to the input. Random and deterministic jitter generation at 1.063Gbps is measured with
0.18UI deterministic jitter, and 0.08UI random jitter (BER = 1 x 10-12) applied to the input.
Jitter tolerance at 2.125Gbps is measured with 0.38UI deterministic jitter and 0.22UI random jitter (BER = 1 x 10-12) applied
to the input. Jitter tolerance at 1.063Gbps is measured with 0.18UI deterministic jitter, and 0.08UI jitter (BER = 1 x 10-12)
applied to the input.
Note 6:Compliant jitter tolerance pattern in hex (CJTPAT):
PatternNo. of Occurrences
3EAA2AAAAA6
3EAAA6A5A91
871E3871E341
871E3870BC78F4AAAAAA1
AAAAAAAAAA12
AAA15555E3 871E3871E11
AB9C9686E61
C16AAA9AA61
Note 7:Jitter tolerance measurements at 85kHz and 1270kHz are limited by test equipment. Actual jitter tolerance > indicated.
MAX3770/MAX3771
2.125Gbps/1.063Gbps, 3.3V
Fibre Channel Repeaters
MAX3770
JITTER TRANSFER
MAX3770/1 toc01
JITTER FREQUENCY (Hz)
RANS
R (d
-101M10M100M10k100k1G
MAX3770
JITTER TOLERANCE
MAX3770/1 toc02
JITTER FREQUENCY (Hz)
PUT
ER (
0.110M100M10k100k
DATA
CLOCK
MAX3770
RECOVERED DATA AND CLOCK SIGNALS
MAX3770/1 toc03
100ps/div
Typical Operating Characteristics
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
Pin Description
MAX3770/MAX3771
2.125Gbps/1.063Gbps, 3.3V
Fibre Channel Repeaters
Figure 2. Functional Diagram
MAX3770/MAX3771
2.125Gbps/1.063Gbps, 3.3V
Fibre Channel Repeaters
Detailed Description
Figure 2 shows the functional diagram of the MAX3770
Fibre Channel repeater IC. The MAX3770 consists of a
fully integrated phased-lock loop (PLL), CML input and
output buffers, and a data latch. The PLL consists of a
phase/frequency detector (PFD), a loop filter, and a
voltage-controlled oscillator (VCO). The input and out-
put signal buffers employ low-noise CML architecture
and are terminated on-chip.
Phase and Frequency Detector
The phase/frequency detector generates an output signal
that reflects the phase relationship between the incoming
data and the internal clock generated by the VCO. Data
recovery is accomplished by feedback in the PLL, which
drives the error voltage to zero, aligning the falling edge
of the recovered clock to the center of the data eye.
The phase frequency detector generates a frequency
lock indication that can be monitored at the LOCK pin
(Table 1). When the PLL is frequency-locked onto the
incoming data, lock transitions high.
VCO and Latch
The fully integrated VCO contains an internal current ref-
erence and filter circuitry to minimize the influence
of VCCnoise. The VCO is trimmed to 2.125GHz
(MAX3770) and creates a clock output with frequency
proportional to the control voltage applied by the loop
filter. Data recovery is accomplished by using the recov-
ered clock signal to latch the incoming data to the CML
output buffers, significantly reducing the output jitter.
Applications Information
Figures 3 and 4 show models for the MAX3770/MAX3771
inputs and outputs, including package parasitics. Figure
5 shows typical 50Ωtermination applications.
Design Procedure
The MAX3770’s performance can be greatly affected
by circuit board layout and design. Use good high-fre-
quency design techniques, including minimizing
ground inductance and using fixed-impedance trans-
mission lines on the data and clock signals. All IN,
OUT, and CLK pins can be connected with 0.1µF or
0.01µF coupling capacitors. If DC coupling is desired,
pay particular attention to the DC voltage and current
requirements at the pins of interest (see DC Electrical
Characteristics). The MAX3750/MAX3751 port bypass
circuit can be DC-coupled to the MAX3770/MAX3771
repeater. A 0.22µF capacitor should be used for the
loop filter.
Control Functions
The lock enable (LOCKEN) and clock enable (CLKEN)
pins can be configured to control the PLL’s clock.
Table 1 shows the operational modes available.

Partno	Mfg	Dc	Qty	Available	Descript
MAX3770CEE	MAXIM ?	N/a	2000	avai	2.125Gbps/1.063Gbps / 3.3V Fibre Channel Repeaters