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MAX3752CCM
2.125Gbps / 3.3V Quad-Port Bypass with Repeater
MAX3752
2.125Gbps, 3.3V
Quad-Port Bypass with Repeater 19-1701; Rev 2; 2/01
General DescriptionThe MAX3752 quad-port bypass IC is designed for use
in the Fibre Channel Arbitrated Loop topology. This
device consists of four serially connected port bypass
circuits (PBCs) and a repeater that provides clock and
data recovery (CDR).
The quad-port bypass circuit allows connection of up to
four Fibre Channel L-Ports, which can each be enabled
or bypassed by controlling the PBC select inputs.
Additional quad PBCs can be cascaded for applica-
tions requiring more than four L-Ports. To reduce the
external parts count, all signal inputs and outputs have
internal termination resistors.
The MAX3752 complies with Fibre Channel jitter toler-
ance requirements and can recover data signals with up
to 0.7 unit intervals (UIs) of high-frequency jitter. When
the repeater is not needed, it can be disabled to reduce
power consumption. A fully integrated phase-locked loop
(PLL) provides a frequency lock indication and does not
need an external reference clock.
________________________Applications2.125Gbps Fibre Channel
Fibre Channel Data Storage Systems
Storage Area Networks
Fibre Channel Hubs
FeaturesFour High-Speed Data Ports Meets Fibre Channel Jitter Tolerance
RequirementsLarge Output Signal Swing (>1000mVp-p)+3.0V to +3.6V Single-Supply VoltageOn-Chip Termination Resistors Compatible with
75ΩTransmission Lines at All Ports
Pin Configuration
Ordering Information
Typical Operating Circuit appears at end of data sheet.*EP = Exposed pad
MAX3752
2.125Gbps, 3.3V
Quad-Port Bypass with Repeater
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA= 0°C to +70°C. Typical values are at +3.3V, TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +5.0V
Current into OUT+, OUT-, LOUT1+, LOUT1-, LOUT2+, LOUT2-,
LOUT3+, LOUT3-, LOUT4+, LOUT4-......................0 to 22mA
Voltage at OUT+, OUT-, LOUT1+, LOUT1-, LOUT2+, LOUT2-,
LOUT3+, LOUT3-, LOUT4+, LOUT4-.......................................
.......................................................(VCC - 1.65V) to (VCC + 0.5V)
Voltage at IN+, IN-, LIN1+, LIN1-, LIN2+, LIN2-,LIN3+, LIN3-,
LIN4+, LIN4-...........................................-0.5V to (VCC + 0.5V)
Voltage at CLKEN, CFP, CFM, SEL1, SEL2, SEL3, SEL4,
CDREN, LOCKEN.......................................-0.5V to (VCC + 0.5V)
Voltage at LOCK.........................................-0.5V to (VCC + 0.5V)
Current at LOCK.................................................-10mA to +1mA
Continuous Power Dissipation (TA= +70°C)
TQFP-EP (derate 27.0mW/°C above +70°C)......................2W
Operating Junction Temperature Range...........-55°C to +150°C
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range.............................-50°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX3752
2.125Gbps, 3.3V
Quad-Port Bypass with Repeater
AC ELECTRICAL CHARACTERISTICS—MAX3752 Operating at 2.125Gbps
MAX3752
2.125Gbps, 3.3V
Quad-Port Bypass with Repeater
AC ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics(TA= +25°C and VCC = +3.3V, unless otherwise noted.)
MAX3752
2.125Gbps, 3.3V
Quad-Port Bypass with Repeater
Typical Operating Characteristics (continued)(TA= +25°C and VCC = +3.3V, unless otherwise noted.)
MAX3752
2.125Gbps, 3.3V
Quad-Port Bypass with Repeater
MAX3752
2.125Gbps, 3.3V
Quad-Port Bypass with Repeater
Detailed DescriptionThe MAX3752 quad PBC consists of an input buffer, a
clock/data recovery circuit (for optional data recovery),
four serially connected port bypass circuits, and an
output buffer (Figure 1). The circuit design is optimized
for both high-speed (2Gbps) and low-voltage (+3.3V)
operation.
Input BufferThe input buffer provides line termination and level con-
version. It accepts a differential input voltage of 200mV
to 2200mV at the IN+ and IN- pins. Internal resistors
terminate each input to 75Ω(150Ωtotal between the
two inputs), eliminating the need for external termina-
tion resistors in most applications (see Applications
Informationfor a suggested interface to 50Ωsystems).
Clock and Data RecoveryThe purpose of the clock and data recovery (CDR) is to
improve jitter transfer performance by attenuating jitter
that may be present in the input data. The CDR can
recover data signals that are corrupted by up to 0.7UI
of high-frequency jitter (BER = 10-12). When data recov-
ery is not needed, the CDR may be disabled in order to
save power.
The input buffer drives the CDR circuit, as well as one
input of a 2:1 multiplexer. A TTL high on the CDR enable
pin (CDREN) enables the CDR and connects the CDR
data output to the port bypass circuits. The recovered
clock signal is available for test purposes at LOUT1 (the
output of the first port bypass circuit) when the clock
enable input (CLKEN) is set to a TTL high level. A TTL
low on CDREN disables the CDR and connects the
input buffer output directly to the port bypass circuits.
Port Bypass CircuitsThe output of the 2:1 input multiplexer drives a cascad-
ed series of four PBCs. Each PBC consists of a differen-
tial output buffer, a differential input buffer, and a 2:1
multiplexer. The multiplexer select input (SELn) controls
which multiplexer input is connected to the multiplexer
output. A TTL low on the multiplexer select pin causes
the data signal from the previous stage to be connected
to the multiplexer output (port bypass mode). A TTL
high on the multiplexer select pin causes the data signal
from the input buffer to be connected to the multiplexer
output (port enable mode). The output of the last PBC
drives the output buffer.
Output BufferThe output signal of the last PBC drives the differential
high-power output buffer. The output buffer drives the
output port (OUT±). Internal resistors terminate each
output to 75Ω(150Ωtotal between the two outputs),
eliminating the need for external termination resistors in
most applications (see Applications Informationfor a
suggested interface to 50Ωsystems). The output buffer
produces a differential output voltage of 1000mV to
1600mV when driving a differential 150Ωload.
Figure 1. Functional Diagram
