MAX3748ETE ,Compact 155Mbps to 3.2Gbps Limiting AmplifierApplicationsFunctional Diagram and Pin Configuration appear at end ofGigabit Ethernet SFF/SFP Trans ..
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MAX3748AETE-MAX3748ETE
Compact 155Mbps to 3.2Gbps Limiting Amplifier
General DescriptionThe MAX3748/MAX3748A multirate limiting amplifier func-
tions as a data quantizer for SONET, Fibre Channel, and
Gigabit Ethernet optical receivers. The amplifier accepts
a wide range of input voltages and provides constant-
level current-mode logic (CML) output voltages with con-
trolled edge speeds.
A received-signal-strength indicator (RSSI) is available
when the MAX3748/MAX3748A is combined with the
MAX3744 SFP transimpedance amplifier (TIA). A receiver
consisting of the MAX3744* and the MAX3748/
MAX3748A can provide up to 19dB RSSI dynamic range.
Additional features include a programmable loss-of-signal
(LOS) detect, an optional disable function (DISABLE),
and an output signal polarity reversal (OUTPOL). Output
disable can be used to implement squelch.
The combination of the MAX3748/MAX3748A and the
MAX3744 allows for the implementation of all the small-
form-factor SFF-8472 digital diagnostic specifications
using a standard 4-pin TO-46 header. The MAX3748/
MAX3748A is packaged in a 3mm ✕3mm 16-pin QFN
package with an exposed pad.
*Future product—contact factory for availability.
ApplicationsGigabit Ethernet SFF/SFP Transceiver Modules
Fibre Channel SFF/SFP Transceiver Modules
Multirate OC-3 to OC-48-FEC SFF/SFP
Transceiver Modules
FeaturesSFP Reference Design Available16-Pin QFN Package with 3mm ✕3mm FootprintSingle +3.3V Supply Voltage86ps Rise and Fall TimeLoss of Signal with Programmable ThresholdRSSI Interface (with MAX3744 TIA)Output DisablePolarity Select8.5psP-PDeterministic Jitter (3.2Gbps)
MAX3748/MAX3748A
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
Ordering Information
Typical Operating Circuits19-2717; Rev 1; 7/03
*EP = Exposed pad.
Functional Diagram and Pin Configuration appear at end of
data sheet.
MAX3748/MAX3748A
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= 2.97V to 3.63V, ambient temperature = -40°C to +85°C, CML output load is 50Ωto VCC, CAZ= 0.1µF, typical values are at
+25°C, VCC= 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with f-3dB=
0.75 ✕2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB= 0.75 ✕3.2GHz for a data rate of 3.2Gbps.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Power-Supply Voltage (VCC).................................-0.5V to +6.0V
Voltage at IN+, IN-..........................(VCC- 2.4V) to (VCC+ 0.5V)
Voltage at DISABLE, OUTPOL, RSSI,
CAZ1, CAZ2, LOS, TH............................-0.5V to (VCC+ 0.5V)
Current into LOS...................................................-1mA to +9mA
Differential Input Voltage (IN+ - IN-).....................................2.5V
Continuous Current at CML Outputs
(OUT+, OUT-)...............................................-25mA to +25mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QFN (derate 17.7mW above +70°C)....................1.4W
Operating Junction Temperature Range (TJ)....-55°C to +150°C
Storage Ambient Temperature Range (Ts)........-55°C to +150°C
MAX3748/MAX3748A
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
Note 1:Between sensitivity and overload, all AC specifications are met.
Note 2:Guaranteed by design and characterization.
Note 3:The deterministic jitter caused by this filter is not included in the DJ generation specifications (input).
Note 4:223- 1 PRBS pattern was substituted by K28.5 pattern to determine the high-speed portion of the deterministic jitter. The
low-speed portion of the DJ (baseline wander) was obtained by measuring the eye width difference between outputs gen-
erated using K28.5 and 223- 1 PRBS patterns.
Note 5:Random jitter was measured without using a filter at the input.
Note 6:The supply current measurement excludes the CML output currents by connecting the CML outputs to a separate VCC
(see Figure 1).
Note 7:Unless otherwise specified, the pattern for all LOS detect specifications is 223- 1 PRBS.
Note 8:The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2.
Note 9:ICM_INPUTis the input common mode. IRSSIis the current at the RSSI output.
Note 10:Stability is defined as variation over temperature and power supply with respect to the typical gain of the part.
ELECTRICAL CHARACTERISTICS (continued)(VCC= 2.97V to 3.63V, ambient temperature = -40°C to +85°C, CML output load is 50Ωto VCC, CAZ= 0.1µF, typical values are at
+25°C, VCC= 3.3V, unless otherwise specified. The data input transition time is controlled by a 4th-order Bessel filter with f-3dB=
0.75 ✕2.667GHz for all data rates of 2.667Gbps and below, and with f-3dB= 0.75 ✕3.2GHz for data rate of 3.2Gbps.)
MAX3748/MAX3748A
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
Typical Operating Characteristics(TA= +25°C and VCC= +3.3V, unless otherwise specified.)
MAX3748/MAX3748A
Compact 155Mbps to 3.2Gbps
Limiting Amplifier
OUTPUT EYE DIAGRAM WITH MAXIMUM INPUT
(DATA RATE OF 2.6667Gbps)MAX3748 toc10
50ps/div
100mV/div
OUTPUT EYE DIAGRAM AT +100°C
(MINIMUM INPUT)MAX3748 toc11
50ps/div
100mV/div
ASSERT/DEASSERT LEVELS vs. RTHMAX3748 toc12
RTH (kΩ)
ASSERT/DEASSERT (mV
P-P
INPUT RETURN GAIN vs. FREQUENCY (SDD11)
(INPUT SIGNAL LEVEL = -40dBm)
MAX3748 toc13
FREQUENCY (Hz)
GAIN (dB)
100M10G
OUTPUT RETURN GAIN vs. FREQUENCY (SDD22)
(INPUT SIGNAL LEVEL = -40dBm)MAX3748 toc14
FREQUENCY (Hz)
GAIN (dB)
100M10G
DETERMINISTIC JITTER vs. INPUT OFFSET VOLTAGE
(2.667Gbps, K28.5)MAX3748 toc15
INPUT OFFSET VOLTAGE (mVP-P)
DETERMINISTIC JITTER (ps
P-P20-2-46
LOS HYSTERESIS vs. TEMPERATURE
(2.667bps, 210 - 1 PRBS)MAX3748 toc16
TEMPERATURE (°C)
10LOG (DEASSERT/ASSERT) (dB)80706050403020100-10-20-30
RSSI CURRENT GAIN vs. INPUT TIA CURRENT
(MAX3744 AND MAX3748)
MAX3748 toc17
INPUT TIA CURRENT (µA)
OUTPUT RSSI CURRENT (
Typical Operating Characteristics (continued)(TA= +25°C and VCC= +3.3V, unless otherwise specified.)
MAX3748/MAX3748A
Detailed DescriptionThe limiting amplifier consists of an input buffer, a multi-
stage amplifier, offset correction circuitry, an output
buffer, power-detection circuitry, and signal-detect cir-
cuitry (see Functional Diagram).
Input BufferThe input buffer is shown in Figure 3. It provides 50Ω
termination for each input signal IN+ and IN-. The
MAX3748/MAX3748A can be DC- or AC-coupled to a
TIA (TIA output offset degrades receiver performance if
DC-coupled). The CML input buffer is optimized for the
MAX3744 TIA.
Gain StageThe high-bandwidth gain stage provides approximately
53dB of gain.
Compact 155Mbps to 3.2Gbps
Limiting AmplifierFigure 1. Power-Supply Current Measurement
