MAX3693ECJ ,+3.3V / 622Mbps / SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS InputsApplicationsOrdering Information622Mbps SDH/SONET Transmission SystemsPART TEMP. RANGE PIN-PACKAGE6 ..
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MAX3693ECJ
+3.3V / 622Mbps / SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs
General DescriptionThe MAX3693 serializer is ideal for converting 4-bit-
wide, 155Mbps parallel data to 622Mbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts low-voltage
differential-signal (LVDS) clock and data inputs for
interfacing with high-speed digital circuitry, and deliv-
ers a 3.3V PECL serial-data output. A fully integrated
PLL synthesizes an internal 622Mbps serial clock from
a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz ref-
erence clock.
The MAX3693 is available in the extended temperature
range (-40°C to +85°C), in a 32-pin TQFP package.
Applications622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
FeaturesSingle +3.3V Supply155Mbps (4-bit-wide) Parallel to
622Mbps Serial ConversionClock Synthesis for 622Mbps215mW Power Multiple Clock Reference Frequencies
(155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)LVDS Parallel Clock and Data InputsDifferential 3.3V PECL Serial-Data Output
MAX3693
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
Typical Operating Circuit
Pin Configuration appears at end of data sheet.
MAX3693
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3V to +3.6V, differential LVDS loads = 100W±1%, PECL loads = 50W±1% to (VCC - 2V), TA= -40°C to +85°C, unless other-
wise noted. Typical values are at VCC= +3.3V, TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Terminal Voltage (with respect to GND)
VCC.......................................................................-0.5V to +5V
All Inputs, FIL+, FIL-,
PCLKO+, PCLKO-..............................-0.5V to (VCC+ 0.5V)
Output Current
LVDS Outputs (PCLKO±)................................................10mA
PECL Outputs (SD±).......................................................50mA
Continuous Power Dissipation (TA= +85°C)
TQFP (derate 10.20mW/°C above +85°C)...................663mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX3693
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
Note 1:AC characteristics guaranteed by design and characterization.
AC ELECTRICAL CHARACTERISTICS(VCC= +3V to +3.6V, differential LVDS load = 100W±1%, PECL loads = 50W ±1% to (VCC - 2V), TA= -40°C to +85°C, unless other-
wise noted. Typical values are at VCC= +3.3V, TA= +25°C.) (Note 1)
Typical Operating Characteristics(VCC = +3.3V, differential LVDS loads = 100W±1%, PECL loads = 50Ω±1% to (VCC- 2V), TA= +25°C, unless otherwise noted.)
MAX3693
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
Typical Operating Characteristics (continued)(VCC = +3.3V, differential LVDS loads = 100W±1%, PECL loads = 50Ω±1% to (VCC- 2V), TA= +25°C, unless otherwise noted.)
Pin Description
MAX3693
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________Detailed DescriptionThe MAX3693 serializer comprises a 4-bit parallel input
register, a 4-bit shift register, control and timing logic, a
PECL output buffer, LVDS input/output buffers, and a
frequency-synthesizing PLL (consisting of a phase/
frequency detector, loop filter/amplifier, voltage-
controlled oscillator, and prescaler). This device con-
verts 4-bit-wide, 155Mbps data to 622Mbps serial data
(Figure 1).
The PLL synthesizes an internal 622Mbps reference
used to clock the output shift register. This clock is
generated by locking onto the external 155.52MHz,
77.76MHz, 51.84MHz, or 38.88MHz reference-clock
signal (RCLK).
The incoming parallel data is clocked into the
MAX3693 on the rising transition of the parallel-clock-
input signal (PCLKI). The control and timing logic
ensure proper operation if the parallel-input register is
latched within a window of time that is defined with
respect to the parallel-clock-output signal (PCLKO).
PCLKO is the synthesized 622Mbps internal serial-
clock signal divided by four. The allowable PCLKO-to-
PCLKI skew is 0 to +4ns. This defines a timing window
at about the PCLKO rising edge, during which
a PCLKI rising edge may occur (Figure 2).
MAX3693
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
Low-Voltage Differential-Signal (LVDS)
Inputs and OutputsThe MAX3693 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifi-
cation. This technology uses 250mV to 400mV differ-
ential low-voltage swings to achieve fast transition
times, minimized power dissipation, and noise immu-
nity.
For proper operation, the parallel-clock LVDS outputs
(PCLKO+, PCLKO-) require 100Wdifferential DC termi-
nation between the inverting and noninverting outputs.
Do not terminate these outputs to ground.
The parallel data and parallel clock LVDS inputs (PD_+,
PD_-, PCLKI+, PCLKI-, RCLK+, RCLK-) are internally
terminated with 100Wdifferential input resistance, and
therefore do not require external termination.
PECL OutputsThe serial-data PECL outputs (SD+, SD-) require 50W
DC termination to (VCC- 2V) (see the Alternative PECL-
Output Terminationsection).
