MAX3690ECJ ,+3.3V / 622Mbps / SDH/SONET 8:1 Serializer with Clock Synthesis and TTL InputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, PECL loads = 50Ω ±1% to (V - 2V), T = -40°C to +85°C ..
MAX3690ECJ ,+3.3V / 622Mbps / SDH/SONET 8:1 Serializer with Clock Synthesis and TTL InputsApplicationsOrdering Information622Mbps SDH/SONET Transmission SystemsPART TEMP. RANGE PIN-PACKAGE6 ..
MAX3690ECJ+ ,+3.3V, 622Mbps SDH/SONET 8:1 Serializer with Clock Synthesis and TTL InputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, PECL loads = 50Ω ±1% to (V - 2V), T = -40°C to +85°C ..
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The MAX731 and MAX752 are fixed and adjustable
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MAX3690ECJ
+3.3V / 622Mbps / SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs
General DescriptionThe MAX3690 serializer is ideal for converting 8-bit-
wide, 77Mbps parallel data to 622Mbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts TTL clock and
data inputs, and delivers a 3.3V differential PECL serial-
data output. A fully integrated PLL synthesizes an inter-
nal 622MHz serial clock from a low-speed crystal
reference clock (77.76MHz, 51.84MHz, or 38.88MHz).
The MAX3690 is available in the extended-industrial
temperature range (-40°C to +85°C) in a 32-pin TQFP
package.
________________________Applications622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
____________________________FeaturesSelectable Reference Clock Frequency:
77.76MHz, 51.84MHz, or 38.88MHzSingle +3.3V Supply77Mbps (8-bit) Parallel to 622Mbps Serial
ConversionClock Synthesis for 622Mbps Serial Data200mW Power TTL Parallel Clock and Data InputsDifferential 3.3V PECL Serial-Data Output
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
Typical Operating Circuit19-4774; Rev 1; 4/99
Pin Configuration appears at end of data sheet.
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, PECL loads = 50Ω±1% to (VCC- 2V), TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC= +3.3V, TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:AC characteristics guaranteed by design and characterization.
Note 2:All TTL thresholds set to VCC/ 2.
Terminal Voltage (with respect to GND)
VCC.......................................................................-0.5V to +5V
All Inputs, FIL-, FIL+, PCLKO.................-0.5V to (VCC+ 0.5V)
Output Current
PECL Outputs (SD±).......................................................50mA
Continuous Power Dissipation (TA= +85°C)
TQFP (derate 10.2mW/°C above +85°C).....................663mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, PECL loads = 50Ω±1% to (VCC- 2V), all TTL thresholds set to VCC/2, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at VCC= +3.3V, TA= +25°C.) (Note 1)
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
__________________________________________Typical Operating Characteristics(VCC= +3.3V, TA= +25°C, unless otherwise noted.)
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
______________________________________________________________Pin Description
_______________Detailed DescriptionThe MAX3690 serializer comprises an 8-bit parallel
input register, an 8-bit shift register, control and timing
logic, a PECL output buffer, TTL input/output buffers,
and a frequency-synthesizing PLL (consisting of a
phase/frequency detector, loop filter/amplifier, voltage-
controlled oscillator, and programmable prescaler).
This device converts 8-bit-wide, 77Mbps parallel data
to 622Mbps serial data (Figure 1).
The PLL synthesizes an internal 622MHz reference
used to clock the output shift register. This clock is
generated by locking onto the external crystal refer-
ence clock signal (RCLK) operating at either
77.76MHz, 51.84MHz, or 38.88MHz. The incoming par-
allel data is clocked into the MAX3690 on the rising
transition of the parallel-clock-input signal (PCLKI). The
control and timing logic ensure proper operation if the
parallel-input register is latched within a window of time
that is defined with respect to the parallel-clock-output
signal (PCLKO). PCLKO is the synthesized 622MHz
internal serial-clock signal divided by eight. Parallel-
clock output to parallel-clock-input delay (skew) must
be observed. Figure 2 shows the timing diagram.
PECL OutputsThe serial-data PECL outputs (SD+, SD-) require 50W
DC termination to (VCC- 2V). See the Alternative PECL-
Output Terminationsection.
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL InputsFigure 1. Functional Diagram
Figure 2. Timing Diagram
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
__________Applications Information
Alternative PECL-Output TerminationFigure 3 shows alternative PECL-output-termination
methods. Use Thevenin-equivalent termination when a
(VCC- 2V) termination voltage is not available. If AC
coupling is necessary, be sure that the coupling
capacitor is placed following the 50Wor Thevenin-
equivalent DC termination.
Layout TechniquesFor best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled-impedance transmission lines to
interface with the MAX3690 data outputs.
Figure 3. Alternative PECL-Output Termination
