MAX3690ECJ+ Fast Delivery |IC PHOENIX CO.,LIMITED

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MAX3690ECJ+
+3.3V, 622Mbps SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs
General Description
The MAX3690 serializer is ideal for converting 8-bit-
wide, 77Mbps parallel data to 622Mbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts TTL clock and
data inputs, and delivers a 3.3V differential PECL serial-
data output. A fully integrated PLL synthesizes an inter-
nal 622MHz serial clock from a low-speed crystal
reference clock (77.76MHz, 51.84MHz, or 38.88MHz).
The MAX3690 is available in the extended-industrial
temperature range (-40°C to +85°C) in a 32-pin TQFP
package.
________________________Applications
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
____________________________FeaturesSelectable Reference Clock Frequency:
77.76MHz, 51.84MHz, or 38.88MHzSingle +3.3V Supply77Mbps (8-bit) Parallel to 622Mbps Serial
ConversionClock Synthesis for 622Mbps Serial Data200mW Power TTL Parallel Clock and Data InputsDifferential 3.3V PECL Serial-Data Output
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
MAX3690
MAX3668
SD-GNDPCLKO
38.88MHz TTL CRYSTAL
REFERENCE
PCLKIRCLKVCCCKSET
SD+
FIL-
FIL+
130Ω130Ω
82Ω82Ω
VCC = +3.3V
VCC = +3.3V
VCC = +3.3V
OVERHEAD
GENERATION
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE (Z0 = 50Ω).
1μF1μF
Typical Operating Circuit
19-4774; Rev 2; 7/04
PART
MAX3690ECJ-40°C to +85°C
TEMP RANGEPIN-PACKAGE
32 TQFP
Ordering Information
Pin Configuration appears at end of data sheet.
MAX3690ECJ+-40°C to +85°C32 TQFP
+Denotes lead-free package.
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, PECL loads = 50Ω±1% to (VCC- 2V), TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC= +3.3V, TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:AC characteristics guaranteed by design and characterization.
Note 2:All TTL thresholds set to VCC/ 2.
Terminal Voltage (with respect to GND)
VCC.......................................................................-0.5V to +5V
All Inputs, FIL-, FIL+, PCLKO.................-0.5V to (VCC+ 0.5V)
Output Current
PECL Outputs (SD±).......................................................50mA
Continuous Power Dissipation (TA= +85°C)
TQFP (derate 10.2mW/°C above +85°C).....................663mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C= 0°C to +85°C
PECL outputs unterminated
IOL= -400µA
IOH= 400µA
VIN= 0
VIN= VCC= 0°C to +85°C
CONDITIONS
VCC- 1.025 VCC- 0.8860100ICCSupply Current0.44VOLOutput Low Voltage2.4VOHOutput High Voltage-1010IILInput Low Current-1010IIHInput High Current
VCC- 1.81 VCC- 1.622.0VIHInput High Voltage0.8VILInput Low Voltage
UNITSMINTYPMAXSYMBOLPARAMETER
CLOAD= 15pF, VOUT= 0.8V to 2.0V
CLOAD= 15pF, VOUT= 0.8V to 2.0V
CONDITIONS1000tHParallel Data Hold Time1200tSU
MHz622.08fSCLKSerial Clock Rate
Parallel Data Setup Time550tFTTL Output Fall Time650tRTTL Output Rise Time05.0tSKEWAllowable Parallel Clock Output
to Parallel Clock Input Delay
psRMS11Φ0Output Random Jitter
UNITSMINTYPMAXSYMBOLPARAMETER
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, PECL loads = 50Ω±1% to (VCC- 2V), all TTL thresholds set to VCC/2, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at VCC= +3.3V, TA= +25°C.) (Note 1)
CKSET = 0 or VCCµA500ICKSETCKSET Input Current= -40°CVVCC- 1.085 VCC- 0.88VOHOutput High Voltage= -40°CVVCC- 1.83 VCC- 1.555VOLOutput Low Voltage
PECL OUTPUTS (SD±)
TTL INPUTS AND OUTPUTS (PCLKI, RCLK, PCLKO, PD_)
20% to 80%ps200tR, tFPECL Differential Output
Rise/Fall Time
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
SUPPLY CURRENT vs. TEMPERATURE
MAX3690-01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
PARALLEL DATA SETUP TIME
vs. TEMPERATURE
MAX3690-02
TEMPERATURE (¡C)
PARALLEL DATA SETUP TIME (ps)
PARALLEL DATA HOLD TIME
vs. TEMPERATURE
MAX3690-03
TEMPERATURE (°C)
PARALLEL DATA HOLD TIME (ps)-5050100
ALLOWED PCLKO to PCLKI SKEW
vs. TEMPERATURE
MAX3690-07
TEMPERATURE (°C)
TIME (ns)
2mV/
div
5ps/div
SERIAL DATA RANDOM JITTER
(RCLKI = 77.76MHz)
MAX3690-05
TEMPERATURE (°C)
VCC = 3.3V
RJ = 4.66psRMS
__________________________________________Typical Operating Characteristics
(VCC= +3.3V, TA= +25°C, unless otherwise noted.)
100mV/
div
200ps/div
SERIAL-DATA OUTPUT EYE DIAGRAM
(622Mbps, PRBS)
MAX3690-08
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
______________________________________________________________Pin Description
NAMEFUNCTION
1–8PD0–PD7TTL Parallel-Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
9, 10, 17,
18, 19, 24,
25, 26,
31, 32
GNDGround
PINPCLKOTTL Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead management
circuit.
12, 13, 16,
21, 28, 29VCC+3.3V Supply VoltageCKSET
Reference Clock Rate Programming Pin.
CKSET = open: Reference clock rate = 77.76MHz
CKSET = 20kΩto GND: Reference clock rate = 51.84MHz
CKSET = GND: Reference clock rate = 38.88MHzSD+Noninverting PECL Serial-Data OutputSD-Inverting PECL Serial-Data OutputPCLKITTL Parallel-Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI input. The
active edge is the positive transitioning edge.RCLKTTL Reference-Clock Input. Connect a crystal reference clock (77.76MHz, 51.84MHz or 38.88MHz) to
the RCLK input. The active edge is the positive transitioning edge.FIL+Filter Capacitor Input. Connect a 1µF capacitor between FIL- and VCC.
_______________Detailed Description
The MAX3690 serializer comprises an 8-bit parallel
input register, an 8-bit shift register, control and timing
logic, a PECL output buffer, TTL input/output buffers,
and a frequency-synthesizing PLL (consisting of a
phase/frequency detector, loop filter/amplifier, voltage-
controlled oscillator, and programmable prescaler).
This device converts 8-bit-wide, 77Mbps parallel data
to 622Mbps serial data (Figure 1).
The PLL synthesizes an internal 622MHz reference
used to clock the output shift register. This clock is
generated by locking onto the external crystal refer-
ence clock signal (RCLK) operating at either
77.76MHz, 51.84MHz, or 38.88MHz. The incoming par-
allel data is clocked into the MAX3690 on the rising
transition of the parallel-clock-input signal (PCLKI). The
control and timing logic ensure proper operation if the
parallel-input register is latched within a window of time
that is defined with respect to the parallel-clock-output
signal (PCLKO). PCLKO is the synthesized 622MHz
internal serial-clock signal divided by eight. Parallel-
clock output to parallel-clock-input delay (skew) must
be observed. Figure 2 shows the timing diagram.
PECL Outputs
The serial-data PECL outputs (SD+, SD-) require 50Ω
DC termination to (VCC- 2V). See the Alternative PECL-
Output Terminationsection.FIL-Filter Capacitor Input. Connect a 1µF capacitor between FIL- and VCC.
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
MAX3690
TTLPD7
TTLPD6
TTL
8-BIT
PARALLEL
INPUT
REGISTER
PHASE/FREQ
DETECTCONTROL
8-BIT
SHIFT
REGISTER
PD5
TTLPD4
TTLPD3
TTLPD2
TTLPD1
TTL
TTLPD0
TTLPCLKI
CKSET
TTL
FIL+FIL-PCLKO
VCORCLK
PECLSDOH
SDOL
SHIFT
LATCH
PRE-
SCALER
Figure 1. Functional Diagram
tSU
VALID PARALLEL DATA
PCLKO
PCLKI
PD_D7D6D5D4D3D2
NOTE: PD7 = D7, PD6 = D6, PD5 = D5, PD4 = D4, PD3 = D3, PD2 = D2, PD1 = D1, PD0 = D0D0
tSKEW
Figure 2. Timing Diagram
MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
__________Applications Information
Alternative PECL-Output Termination
Figure 3 shows alternative PECL-output-termination
methods. Use Thevenin-equivalent termination when a
(VCC- 2V) termination voltage is not available. If AC
coupling is necessary, be sure that the coupling
capacitor is placed following the 50Ωor Thevenin-
equivalent DC termination.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled-impedance transmission lines to
interface with the MAX3690 data outputs.
MAX3690
SD+
SD-
VCC - 2V
50Ω50Ω
Z0 = 50ΩHIGH-
IMPEDENCE
INPUTS
Z0 = 50Ω
MAX3690
SD+
SD-
+3.3V
130Ω130Ω
82Ω82Ω
Z0 = 50ΩPECL
INPUTS
Z0 = 50Ω
Figure 3. Alternative PECL-Output Termination

Partno	Mfg	Dc	Qty	Available	Descript
MAX3690ECJ+ \|MAX3690ECJ	MAXIM	N/a	4	avai	+3.3V, 622Mbps SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs