MAX3681EAG ,+3.3V / 622Mbps / SDH/SONET 1:4 Deserializer with LVDS OutputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, differential loads = 100W , T = -40°C to +85°C, unle ..
MAX3681EAG ,+3.3V / 622Mbps / SDH/SONET 1:4 Deserializer with LVDS OutputsApplications________________Ordering Information622Mbps SDH/SONET Transmission SystemsPART TEMP. RA ..
MAX3681EAG+ ,+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS OutputsApplications________________Ordering Information622Mbps SDH/SONET Transmission SystemsPART TEMP RAN ..
MAX368CPN ,Fault-Protected Analog Multiplexer with LatchGeneral Description
Maxim's MAX368/369 are 8 channel single-ended (1 of
8) and 4 channel differ ..
MAX368EJN ,Fault-Protected Analog Multiplexer with Latch19-0982; Rev 1; T/96
Analog Multiplexer with Latch,
MAX368EWN ,Fault-Protected Analog Multiplexer with LatchELECTRICAL CHARACTERISTICS
(V' - +15V, V - -leN, GND = o, WR = (j, RS = 2 4V Ljrnless Otherw1ser10 ..
MAX7318AUG+ ,2-Wire-Interfaced, 16-Bit, I/O Port Expander with Interrupt and Hot-Insertion ProtectionApplicationsPKGPART TEMP RANGE PIN-PACKAGECODEServersMAX7318AWG -40°C to +125°C 24 Wide SO —RAID Sy ..
MAX7319AEE+ ,I²C Port Expander with Eight Inputs and Maskable Transition DetectionFeatures2The MAX7319 2-wire serial-interfaced peripheral ● 400kHz, +5.5V -Tolerant I C Serial Inte ..
MAX7319AEE+ ,I²C Port Expander with Eight Inputs and Maskable Transition DetectionApplications● Cell Phones ● Notebooks● SAN/NAS ● Satellite Radio● ServersSelector GuidePART INPUTS ..
MAX731CPA ,+5V/Adjustable Step-Up Current-Mode DC-DC ConvertersELECTRICAL CHARACTERISTICS - MAX731
(Circuit of Figure 1a, VIN = +3V, ILOAD = 0mA, TA = TMIN to ..
MAX731CPA ,+5V/Adjustable Step-Up Current-Mode DC-DC ConvertersFeatures
. 200mA Load Currents Guaranteed with
No External M
OSFET
. Step-Up from a 2.5 ..
MAX731CWE ,5V step-up current-mode DC-DC converter
MAX3681EAG
+3.3V / 622Mbps / SDH/SONET 1:4 Deserializer with LVDS Outputs
_________________General DescriptionThe MAX3681 deserializer is ideal for converting
622Mbps serial data to 4-bit-wide, 155Mbps parallel
data in ATM and SDH/SONET applications. Operating
from a single +3.3V supply, this device accepts PECL
serial clock and data inputs, and delivers low-voltage
differential-signal (LVDS) clock and data outputs for
interfacing with high-speed digital circuitry. It also pro-
vides an LVDS synchronization input that enables data
realignment and reframing.
The MAX3681 is available in the extended-industrial
temperature range (-40°C to +85°C), in a 24-pin SSOP
package.
__________________________Applications622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
______________________________FeaturesSingle +3.3V Supply622Mbps Serial to 155Mbps Parallel Conversion265mW PowerLVDS Data Outputs and Synchronization InputsSynchronization Input for Data Realignment and
Reframing Differential 3.3V PECL Clock and Data Inputs
MAX3681
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
________________________________________________________________Maxim Integrated Products1
___________________________________________________________________Typical Operating Circuit
& the latest literature: http://,
Pin Configuration appears at end of data sheet.
MAX3681
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, differential loads = 100W, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V,= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:AC Characteristics guaranteed by design and characterization.
Terminal Voltage (with respect to GND)
VCC...........................................................................-0.5V to 5V
PECL Inputs (SD+/-, SCLK+/-).................................VCC+ 0.5V
LVDS Inputs (SYNC+/-)............................................VCC+ 0.5V
Output Current, LVDS Outputs (PCLK+/-, PD_+/-).............10mA
Continuous Power Dissipation (TA= +85°C)
SSOP (derate 8.00mW/°C above +85°C)......................520mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, differential loads = 100W, TA= +25°C, unless otherwise noted.) (Note 1)
MAX3681
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
_______________________________________________________________________________________3MAXIMUM SERIAL CLOCK FREQUENCYvs. TEMPERATURE
MAX3681-01
MAX SERIAL CLOCK FREQUENCY (GHz)
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE
MAX3681-02
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
SERIAL DATA-SETUP TIME
vs. TEMPERATURE
MAX3681-03
SERIAL DATA-SETUP TIME (ps)
TEMPERATURE (°C)
SERIAL DATA-HOLD TIME
vs. TEMPERATURE
MAX3681-04
SERIAL DATA-HOLD TIME (ps)
TEMPERATURE (°C)
PARALLEL CLOCK TO DATAOUTPUT PROPAGATION DELAY
vs. TEMPERATURE
MAX3681-05
PARALLEL CLOCK TO DATA
PROPAGATION DELAY (ps)
TEMPERATURE (°C)
__________________________________________Typical Operating Characteristics
(VCC= +3.0V to +3.6V, differential loads = 100W, unless otherwise noted.)
MAX3681
_______________Detailed DescriptionThe MAX3681 deserializer uses a 4-bit shift register,
4-bit parallel output register, 2-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 622Mbps serial data to
4-bit-wide, 155Mbps parallel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 2-bit counter generates a parallel out-
put clock (PCLK) by dividing down the serial clock fre-
quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by four, causing the output
register to latch every four bits of incoming serial data.
The synchronization inputs (SYNC+, SYNC-) are used
for data realignment and reframing. When the SYNC
signal is pulsed high for at least two SCLK cycles, the
parallel output data is delayed by one SCLK cycle. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC signal’s positive transition. As a
result, the first incoming bit of data during that PCLK
cycle is dropped, shifting the alignment between PCLK
and data by one bit.
See Figure 2 for the functional timing diagram and
Figure 3 for the timing parameters diagram.
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs_______________________________________________________________________________________
______________________________________________________________Pin DescriptionFigure 1. Functional Diagram
MAX3681
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
_______________________________________________________________________________________5Figure 2. Functional Timing Diagram
Figure 3. Timing Parameters
MAX3681
Low-Voltage Differential-Signal (LVDS)
Inputs and OutputsThe MAX3681 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 250mVp-p to 400mVp-p, dif-
ferential low-voltage swings to achieve fast transition
times, minimized power dissipation, and noise immunity.
The parallel clock and data LVDS outputs (PCLK+,
PCLK-, PD_+, PD_-) require 100Ωdifferential DC termi-
nation between the inverting and noninverting outputs
for proper operation. Do not terminate these outputs to
ground.
The synchronization LVDS inputs (SYNC+, SYNC-) are
internally terminated with 100Ωof differential input
resistance, and therefore do not require external termi-
nation.
PECL InputsThe serial data and clock PECL inputs (SD+, SD-,
SCLK+, SCLK-) require 50Wtermination to (VCC- 2V)
when interfacing with a PECL source (see the
Alternative PECL Input Termination section).
__________Applications Information
Alternative PECL Input TerminationFigure 4 shows alternative PECL input-termination
methods. Use Thevenin-equivalent termination when a
(VCC- 2V) termination voltage is not available. If AC
coupling is necessary, such as when interfacing with
an ECL-output device, use the ECL AC-coupling termi-
nation.
Layout TechniquesFor best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3681 data inputs and outputs.
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs_______________________________________________________________________________________Figure 4. Alternative PECL Input Termination
