MAX3681EAG+ Fast Delivery |IC PHOENIX CO.,LIMITED

MAX3681EAG+ ,+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS OutputsApplications________________Ordering Information622Mbps SDH/SONET Transmission SystemsPART TEMP RAN ..
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MAX3681EAG+
+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs
_________________General Description
The MAX3681 deserializer is ideal for converting
622Mbps serial data to 4-bit-wide, 155Mbps parallel
data in ATM and SDH/SONET applications. Operating
from a single +3.3V supply, this device accepts PECL
serial clock and data inputs, and delivers low-voltage
differential-signal (LVDS) clock and data outputs for
interfacing with high-speed digital circuitry. It also pro-
vides an LVDS synchronization input that enables data
realignment and reframing.
The MAX3681 is available in the extended-industrial
temperature range (-40°C to +85°C), in a 24-pin SSOP
package.
__________________________Applications
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
______________________________FeaturesSingle +3.3V Supply622Mbps Serial to 155Mbps Parallel Conversion265mW PowerLVDS Data Outputs and Synchronization InputsSynchronization Input for Data Realignment and
Reframing Differential 3.3V PECL Clock and Data Inputs
MAX3681
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
MAX3675
MAX3664
MAX3681
DATA
AND
CLOCK
RECOVERY
OVERHEAD
TERMINATION
LIMITING
AMPPREAMP100Ω
100Ω*
100Ω*
100Ω*
100Ω*
100Ω*
PHOTODIODE
VCC = +3.3V
VCC = +3.3V
PD3+
PD3-
PD2+
PD2-
PD1+
PD1-
PD0+
PD0-
PCLK+
PCLK-
SYNC+
SYNC-
SD+
SD-
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.
VCC
GND
130Ω130Ω
82Ω82Ω
VCC = +3.3V
130Ω130Ω
82Ω82Ω
VCC = +3.3V
SCLK+
SCLK-
___________________________________________________________________Typical Operating Circuit
19-1091; Rev 1; 5/04
PART
MAX3681EAG-40°C to +85°C
TEMP RANGEPIN-PACKAGE
24 SSOP
EVALUATION KIT
AVAILABLE
________________Ordering Information
+Denotes Lead Free Package
MAX3681EAG+-40°C to +85°C24 SSOP
Pin Configuration appears at end of data sheet.
MAX3681
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, differential loads = 100Ω, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V,= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:AC Characteristics guaranteed by design and characterization.
Terminal Voltage (with respect to GND)
VCC...........................................................................-0.5V to 5V
PECL Inputs (SD+/-, SCLK+/-).................................VCC+ 0.5V
LVDS Inputs (SYNC+/-)............................................VCC+ 0.5V
Output Current, LVDS Outputs (PCLK+/-, PD_+/-).............10mA
Continuous Power Dissipation (TA= +85°C)
SSOP (derate 8.00mW/°C above +85°C)......................520mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C= +25°C
Common-mode voltage = 50mV
Differential input voltage = 100mV
VIN= VIH(MAX)
VIN= VIL(MAX)
CONDITIONS±1±10ΔRO
Change in Magnitude of Single-
Ended Output Resistance for
Complementary States4070140ROSingle-Ended Output Resistance25ΔVOS
Change in Magnitude of Output
Offset Voltage for Complementary
States1.1251.275VOSOutput Offset Voltage25ΔVOD
Change in Magnitude of Differential
Output Voltage for Complementary
States250400VODDifferential Output Voltage0.925VOLOutput Low Voltage1.475VOHOutput High VoltageVCC- 1.16VCC- 0.88VIHInput High Voltage5580120ICCSupply Current85100115RINDifferential Input Resistance70VHYSTThreshold Hysteresis-100100VIDTHDifferential Input Threshold02.4VIInput Voltage RangeVCC- 1.81VCC- 1.48VILInput Low Voltage-1010IIHInput High Current-1010IILInput Low Current
UNITSMINTYPMAXSYMBOLPARAMETER
CONDITIONS50tHSerial Data Hold Time800tSU
MHz622fSCLKMaximum Serial Clock Frequency
Serial Data Setup Time200550900tCLK-QParallel Clock to Data Output Delay
UNITSMINTYPMAXSYMBOLPARAMETER
PECL INPUTS(SD+/-, SCLK+/-)
LVDS INPUTS AND OUTPUTS(SYNC+/-, PCLK+/-, PD_+/-)
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, differential loads = 100Ω, TA= +25°C, unless otherwise noted.) (Note 1)
MAX3681
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
MAXIMUM SERIAL CLOCK FREQUENCY
vs. TEMPERATURE
MAX3681-01
MAX SERIAL CLOCK FREQUENCY (GHz)
TEMPERATURE (°C)
VCC = 3.0V
VCC = 3.6V
SUPPLY CURRENT
vs. TEMPERATURE
MAX3681-02
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
VCC = +3.0V
VCC = +3.6V
VCC = +3.3V
SERIAL DATA-SETUP TIME
vs. TEMPERATURE
MAX3681-03
SERIAL DATA-SETUP TIME (ps)
TEMPERATURE (°C)
SERIAL DATA-HOLD TIME
vs. TEMPERATURE
MAX3681-04
SERIAL DATA-HOLD TIME (ps)
TEMPERATURE (°C)
PARALLEL CLOCK TO DATA
OUTPUT PROPAGATION DELAY
vs. TEMPERATURE
MAX3681-05
PARALLEL CLOCK TO DATA
PROPAGATION DELAY (ps)
TEMPERATURE (°C)
__________________________________________Typical Operating Characteristics
(VCC= +3.0V to +3.6V, differential loads = 100Ω, unless otherwise noted.)
MAX3681
_______________Detailed Description
The MAX3681 deserializer uses a 4-bit shift register,
4-bit parallel output register, 2-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 622Mbps serial data to
4-bit-wide, 155Mbps parallel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 2-bit counter generates a parallel out-
put clock (PCLK) by dividing down the serial clock fre-
quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by four, causing the output
register to latch every four bits of incoming serial data.
The synchronization inputs (SYNC+, SYNC-) are used
for data realignment and reframing. When the SYNC
signal is pulsed high for at least two SCLK cycles, the
parallel output data is delayed by one SCLK cycle. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC signal’s positive transition. As a
result, the first incoming bit of data during that PCLK
cycle is dropped, shifting the alignment between PCLK
and data by one bit.
See Figure 2 for the functional timing diagram and
Figure 3 for the timing parameters diagram.
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
______________________________________________________________Pin Description
NAMEFUNCTION
1, 2, 5, 8, 12VCC+3.3V Supply VoltageSD+Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
PINSD-Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.SCLK+Noninverting PECL Serial Clock InputSYNC-Inverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.SYNC+Noninverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK
periods to shift the data alignment by dropping one bit.
9, 15, 22GNDGroundSCLK-Inverting PECL Serial Clock Input
17, 19, 21, 24PD0+ to PD3+Noninverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.
16, 18, 20, 23PD0- to PD3-Inverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal.
See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment.PCLK+Noninverting LVDS Parallel Clock OutputPCLK-Inverting LVDS Parallel Clock Output
4-BIT
SHIFT
REGISTER
4-BIT
PARALLEL
OUTPUT
REGISTER
2-BIT
COUNTER
LVDSPECL
PECL
LVDS
LVDS
LVDS
LVDS
LVDS
PD3+
PD3-
PD2+
PD2-
PD1+
PD1-
PD0+
PD0-
PCLK+
PCLK-
SD+
SD-
SCLK+
SCLK-
SYNC+
SYNC-
100Ω
MAX3681
Figure 1. Functional Diagram
MAX3681
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
SCLK
SYNC
PCLK
PD3
PD2
PD1
PD0
D1-D0D1
D4-D0D5
D3-D1D6
D2-D2D7
D1-D3D8D3D4D5D6D7D8D9D10D11
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2. Functional Timing Diagram
SCLK
PCLK
PD0–PD3
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
tSCLK = 1 / fSCLK
tSU
tCLK-Q
Figure 3. Timing Parameters
MAX3681
Low-Voltage Differential-Signal (LVDS)
Inputs and Outputs
The MAX3681 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 250mVp-p to 400mVp-p, dif-
ferential low-voltage swings to achieve fast transition
times, minimized power dissipation, and noise immunity.
The parallel clock and data LVDS outputs (PCLK+,
PCLK-, PD_+, PD_-) require 100Ωdifferential DC termi-
nation between the inverting and noninverting outputs
for proper operation. Do not terminate these outputs to
ground.
The synchronization LVDS inputs (SYNC+, SYNC-) are
internally terminated with 100Ωof differential input
resistance, and therefore do not require external termi-
nation.
PECL Inputs
The serial data and clock PECL inputs (SD+, SD-,
SCLK+, SCLK-) require 50Ωtermination to (VCC- 2V)
when interfacing with a PECL source (see the
Alternative PECL Input Termination section).
__________Applications Information
Alternative PECL Input Termination
Figure 4 shows alternative PECL input-termination
methods. Use Thevenin-equivalent termination when a
(VCC- 2V) termination voltage is not available. If AC
coupling is necessary, such as when interfacing with
an ECL-output device, use the ECL AC-coupling termi-
nation.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3681 data inputs and outputs.
+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
MAX3681
PECL
INPUTS
ZO = 50Ω
ZO = 50Ω
130Ω
82Ω
130Ω
82Ω
+3.3V
MAX3681
PECL
INPUTS
ZO = 50Ω
50Ω
ZO = 50Ω
1.6k
2.7k
1.6k
2.7k
+3.3V
-2V
50Ω
-2V
THEVENIN-EQUIVALENT TERMINATION
ECL AC-COUPLING TERMINATION
Figure 4. Alternative PECL Input Termination

Partno	Mfg	Dc	Qty	Available	Descript
MAX3681EAG+ \|MAX3681EAG	MAXIM	N/a	1200	avai	+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs