MAX3676EHJ+ Fast Delivery |IC PHOENIX CO.,LIMITED

MAX3676EHJ+ ,622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting AmplifierELECTRICAL CHARACTERISTICS(V = +3.0V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical ..
MAX3676EHJ+ ,622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting AmplifierApplications+Denotes a lead(Pb)-free/RoHS-compliant package.SDH/SONET Receivers and RegeneratorsSDH ..
MAX3679CTJ+ , 3.3V, Low-Jitter Crystal to LVPECL Clock Generator
MAX367CWN ,Signal-Line Circuit ProtectorsGeneral Description ________
MAX367EWN ,Signal-Line Circuit ProtectorsFeaturesThe MAX366 and MAX367 are multiple, two-terminal circuit' ±40V Overvoltage Protectionprotec ..
MAX367EWN ,Signal-Line Circuit ProtectorsApplicationsMAX367 available after January 1, 1995.* Dice are tested at T = +25°C only.Process Cont ..
MAX7314ATG+T ,18-Port GPIO with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionApplications3.3VLCD Backlights 0.047μFLED Status IndicationV+ P0μCP1Relay DriversSDA SDA P2MAX7314S ..
MAX7314ATG+T ,18-Port GPIO with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionFeatures2The MAX7314 I C-compatible serial interfaced periph- ♦ 400kbps, 2-Wire Serial Interface, ..
MAX7315AEE+ ,8-Port I/O Expander with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionFeatures2The MAX7315 I C-/SMBus-compatible serial interfaced♦ 400kbps, 2-Wire Serial Interface, 5 ..
MAX7315AEE+ ,8-Port I/O Expander with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionMAX731519-3056; Rev 3; 1/058-Port I/O Expander with LED IntensityControl, Interrupt, and Hot-Insert ..
MAX7315AEE+T ,8-Port I/O Expander with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionApplications Pin ConfigurationsLCD Backlights Keypad BacklightsTOP VIEWLED Status Indication RGB LE ..
MAX7315ATE ,8-Port I/O Expander with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionFeatures2The MAX7315 I C-/SMBus-compatible serial interfaced♦ 400kbps, 2-Wire Serial Interface, 5 ..

MAX3676EHJ+
622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
Typical Operating Circuit
General Description
The MAX3676 is a complete clock-recovery and data-
retiming IC incorporating a limiting amplifier. It is intend-
ed for 622Mbps SDH/SONET applications and operates
from a single +3.3V supply.
The MAX3676 is designed for both section-regenerator
and terminal-receiver applications in OC12/STM-4 trans-
mission systems. Its jitter performance exceeds all
SONET/SDH specifications.
The MAX3676 has two differential input amplifiers: one
accepts positive-referenced emitter-coupled logic
(PECL) levels, while the other accepts small-signal ana-
log levels. The analog inputs access the limiting amplifi-
er stage, which provides both a received-signal-strength
indicator (RSSI) and a programmable-threshold loss-of-
power (LOP) monitor. Selecting the PECL amplifier dis-
ables the limiting amplifier, conserving power. A
loss-of-lock (LOL) monitor is also incorporated as part of
the fully integrated phase-locked loop (PLL).
Applications
SDH/SONET Receivers and Regenerators
SDH/SONET Access Nodes
Add/Drop Multiplexers
ATM Switches
Digital Cross-Connects
Features♦Single +3.3V or +5.0V Power Supply♦Exceeds ITU/Bellcore SDH/SONET Regenerator
Specifications ♦Low Power: 237mW at +3.3V♦Selectable Data Inputs, Differential PECL or
Analog♦Received-Signal-Strength Indicator♦Loss-of-Power and Loss-of-Lock Monitors♦Differential PECL Clock and Data Outputs♦No External Reference Clock Required
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
VCC
ZO = 50Ω
100Ω
20k
INREF
FILT
OUT+
CIN
0.01μF
CIN
0.01μF
COLC
33nF
CFILT
47nF
+3.3V
220pF
100pF
PHOTO-
DIODEADI+
DDI-
DDI+SDO+
SDO-
0.1μF
CLOL
0.01μF
0.01μF
ADI-
CFILTOLC+OLC-
GNDRSSIINVVTHLOP
INSELPHADJ+PHADJ-FIL+
2.2μF
FIL-
OUT-
GNDCOMPZO = 50Ω
+3.3V
VCC
SCLKO+
SCLKO-ZO = 50Ω
ZO = 50Ω
+3.3V
+3.3V
82Ω82Ω
130Ω130Ω
ZO = 50Ω
ZO = 50Ω
+3.3V
82Ω82Ω
130Ω130Ω
LOL
MAX3676
MAX3664
19-1537; Rev 4; 3/09
Ordering Information
Pin Configuration appears at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package.
PART TEMP RANGE PIN-PACKAGE
MAX3676EHJ -40°C to +85°C 32 TQFP
MAX3676EHJ+ -40°C to +85°C 32 TQFP
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +6.5V
Input Voltage Levels,
DDI+, DDI-, ADI+, ADI-...........................-0.5V to (VCC+ 0.5V)
Input Differential Voltage (ADI+) - (ADI-)...............................±3V
PECL Output Currents, SDO+, SDO-, SCLKO+, SCLKO-...100mA
LOL, LOP, INSEL, PHADJ+, PHADJ-.........-0.5V to (VCC+ 0.5V)
FIL-, OLC+, OLC-, RSSI, VTH....................-0.5V to (VCC+ 0.5V)
(OLC+) - (OLC-).....................................................................±3V
FIL+..................................................Internally connected to VCC
CFILT...............................................(VCC- 2.5V) to (VCC+ 0.5V)
INV.........................................................................-0.5V to +2.0V
Continuous Power Dissipation (TA= +85°C)
TQFP (derate 18.7mW/°C above +85°C)................1214.8mW
Operating Junction Temperature Range...........-40°C to +150°C
Storage Temperature Range.............................-65°C to +150°C
Processing Temperature (die).........................................+400°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX3676EHJ,
PECL outputs
unterminated= 0°C to +85°C= 0°C to +85°C
CONDITIONSVCC- 1.16VCC- 0.88VIHPECL Input-Voltage High811110.4VOLLOP, LOL Voltage Low2.4VOHLOP, LOL Voltage High
VCC- 1.81VCC- 1.620VCC- 1.81VCC- 1.48VILPECL Input-Voltage Low-1010IIHPECL Input-Current High-1010IILPECL Input-Current Low
VCC- 1.025VCC- 0.88
UNITSMINTYPMAXSYMBOLPARAMETER
INSEL = VCC
INSEL = GND
Note 1:At TA= -40°C, DC characteristics are guaranteed by design and characterization.ICCSupply Current= -40°CVVCC- 1.085VCC- 0.88VOHPECL Output-Voltage High= -40°CVVCC- 1.83VCC- 1.555VOLPECL Output-Voltage Low
4kΩbetween INV and VTHV1.101.231.30INV Input Bias Voltage
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V and TA= +25°C.)
(Notes 2, 3)
Note 2:AC parameters are guaranteed by design and characterization.
Note 3:The MAX3676 is characterized with a PRBS of 223- 1 maintaining a BER of ≤10-10having a confidence level of 99.9%.
Note 4:A lower minimum input voltage of 2mVP-Pis achievable; however, the LOP hysteresis is not guaranteed below 3.6mVP-P.
Note 5:Hysteresis = 20log(VRELEASE/VASSERT).
Note 6:R1= 20kΩ, R2 = 3.0kΩ, resulting inVRELEASE ≈3.6mVP-P.
Note 7:Small-signal bandwidth cannot be measured directly.
Note 8:RSSI slope = [VRSSI2- VRSSI1]/[20log (VID2/VID1)].
Note 9:1UI = 1 unit interval = (622.08MHz)-1= 1.608ns.
Note 10:At jitter frequencies <10kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency
jitter tolerance outperforms the instrument’s measurement capability.
Note 11:See Typical Operating Characteristicsfor worst-case distribution.
PARAMETERSYMBOLMINTYPMAXUNITS
RSSI Output Voltage1.40
Limiting Amplifier Small-
Signal BandwidthBW650MHz
Power-Detect Hysteresis36dB
Input-Referred NoiseVN80μVRMS
Threshold VoltageVTH1.41V
Differential Input Voltage
RangeVID0.0031.2000VP-P
CONDITIONS
(ADI+) - (ADI-) = 2mVP-P
(Note 7)
(Notes 5, 6)
ADI inputs
(Note 6)
BER < 10-10, ADI inputs (Note 4)
1.93V(ADI+) - (ADI-) = 20mVP-P
Jitter-Transfer Peaking0.030.08dB
Maximum Consecutive Input
Run Length (1 or 0)1200Bits= 2.2μF
8.9= 2.2μF(Note 11)3.64Jitter Tolerance (Note 10)0.550.77
0.450.69= 2.2μFLoop Bandwidth250500kHz
RSSI Linearity±0.7%(ADI+) - (ADI-) = 2mVP-Pto 50mVP-P
RSSI SlopemV/dB(ADI+) - (ADI-) = 2mVP-Pto 50mVP-P
(Note 8)=10kHz=25kHz=250kHz=1MHz= 2.2μFJitter Generation (Note 9)2.02.6mUI
LOP Threshold Accuracy-2+2dB(Note 6)
Clock Transition Timetr, tf205245ps20% to 80%
Data Transition Timetr, tf180230ps20% to 80%
Serial Clock-to-Q DelaytCLK-Q140275400ps
Serial Clock FrequencyfSCLK622.08MHz
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
Typical Operating Characteristics
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
400ps/div
CLOCK
DATA
RECOVERED DATA AND
CLOCK (SINGLE-ENDED)
MAX3676 toc01223 -1 PATTERN
20ps/div
RECOVERED CLOCK JITTER
MAX3676 toc02
223 -1 PATTERN
WIDEBAND RMS
JITTER = 5.84ps
600μ500μ400μ800μ700μ900μ1m1.1m1.2m
BIT-ERROR RATE
vs. ADI INPUT VOLTAGE
MAX3676 toc03
INPUT VOLTAGE (V)
BIT-ERROR RATE
223 -1 PATTERN
10k100k1M10M
JITTER TOLERANCE
MAX3676 toc04
JITTER FREQUENCY (Hz)
INPUT JITTER (UI
P-P
223 -1 PATTERN
BELLCORE
MASK
-3.010k100k700k
JITTER TRANSFER
MAX3676 toc05
JITTER FREQUENCY (Hz)
JITTER TRANSFER (dB)
223 - 1 PRBS
BELLCORE
MASK
DISTRIBUTION OF JITTER TOLERANCE
(WORST-CASE CONDITIONS)
MAX3676 toc06
JITTER TOLERANCE (UIP-P)
PERCENT OF UNITS (%)
fJITTER = 25kHz
VCC = +3.0V
TA = +85°C
MEAN = 2.42UI σ = 0.227UI
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
Typical Operating Characteristics (continued)
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
LOSS-OF-POWER
HYSTERESIS vs. TEMPERATURE
MAS3676 toc07
AMBIENT TEMPERATURE (°C)
HYSTERESIS (dB)
223 -1 PATTERN
VCC = +3.3V OR +5.0V
RECEIVED-SIGNAL-STRENGTH INDICATOR
vs. INPUT VOLTAGE
MAX3676 toc08
INPUT VOLTAGE (mVP-P)
RSSI (V)
223 -1 PATTERN
1010 PATTERN
LOSS-OF-POWER
ASSERT AND RELEASE LEVEL
vs. DETECTOR THRESHOLD VOLTAGE
MAX3676 toc09
DETECTOR THRESHOLD VOLTAGE, VTH (V)
ANALOG VOLTAGE (mVp-p)
LOP RELEASE
LOP ASSERT
223 -1 PATTERN
RECEIVED-SIGNAL-STRENGTH INDICATOR
vs. INPUT VOLTAGE
MAX3676 toc10
INPUT VOLTAGE (mVP-P)
RSSI (V)
2.5223 -1 PATTERN
VCC = +3.3V OR +5.0V
SUPPLY CURRENT
vs. TEMPERATURE
MAX3676 toc11
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
VCC = +5.0V
VCC = +3.3V
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
Pin DescriptionCFILTRSSI Filter Capacitor Input. Connect a 47nF capacitor between CFILT and VCC.ADI+Positive Analog Data Input, 622.08Mbps serial-data streamADI-Negative Analog Data Input, 622.08Mbps serial-data streamINSELInput Select. Connect to GND to select digital data inputs or VCCfor analog data inputs.DDI-Negative Digital Data Input, PECL, 622.08Mbps serial-data stream DDI+Positive Digital Data Input, PECL, 622.08Mbps serial-data stream FIL+Positive Filter Input. PLL loop filter connection. Internally connected to VCC.FIL-Negative Filter Input. PLL loop filter connection. Connect a 2.2μF capacitor between FIL- and FIL+.PHADJ+Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCCif not used.PHADJ-Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCCif not used.
NAMEFUNCTIONOLC+Positive Offset-Correction Loop Capacitor InputOLC-Negative Offset-Correction Loop Capacitor Input
PINRSSIReceived-Signal-Strength Indicator Output
4, 8, 16,
24, 25GNDSupply Ground
9, 12, 15,
18, 21, 31VCCPositive Supply VoltageLOPLoss-of-Power Output, TTL. Limiting amplifier loss-of-power monitor. Asserts high when input signal
is below threshold set by VTH.VTHVoltage Threshold Input. Threshold voltage for loss-of-power monitor. Attach to VCCif LOP function
is not used.INVOp Amp Inverting Input. Attach to ground if op amp is not used.LOLLoss-of-Lock Output, TTL. PLL loss-of-lock monitor, active low (see the Design Proceduresection).SDO+Positive Serial-Data Output, PECL, 622.08Mbps SDO-Negative Serial-Data Output, PECL, 622.08Mbps SCLKO+Positive Serial-Clock Output, PECL, 622.08MHz. SDO+ is clocked out on the rising edge of SCLKO+.SCLKO-Negative Serial-Clock Output, PECL, 622.08MHz. SDO- is clocked out on the falling edge of SCLKO-.
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
_______________Detailed Description
The block diagram in Figure 1 shows the MAX3676’s
architecture. It consists of a limiting-amplifier input
stage followed by a fully integrated clock/data-recovery
(CDR) block implemented with a PLL. The input stage
is selectable between a limiting amplifier or a simple
PECL input buffer. The limiting amplifier provides an
LOP monitor and an RSSI output. The PLL consists of a
phase/frequency detector (PFD), a loop filter amplifier,
and a voltage-controlled oscillator (VCO).
Limiting Amplifier
The MAX3676’s on-chip limiting amplifier accepts an
input signal level from 3.0mVP-Pto 1.2VP-P. The amplifi-
er consists of a cascade of gain stages that include full-
wave logarithmic detectors. The combined small-signal
gain is approximately 42dB, and the -3dB bandwidth is
650MHz. Input-referred noise is typically 80μVRMS, pro-
viding excellent sensitivity for small-amplitude data
streams.
In addition to driving the CDR, the limiting amplifier pro-
vides both an RSSI output and an LOP monitor that
allow the user to program the threshold voltage. The
RSSI circuitry provides an output voltage that is linearly
proportional to the input power (in decibels) detected
between the ADI+ and ADI- input pins and is sensitive
enough to reliably detect signals as small as 2mVP-P
(see the Typical Operating Characteristics).
Input DC offset reduces the accuracy of the power
detector; therefore, an integrated feedback loop is
included that automatically nulls the input offset of the
gain stage. The addition of this offset-correction loop
requires that the input signal be AC-coupled when
using the ADI+ and ADI- inputs.
Finally, for applications that do not require the limiting
amplifier, selecting the digital inputs conserves power
by turning off the postamplifier block.
MAX3676
LOL
PHASE/FREQ
DETECTOR
POWER
DETECT
OFFSET
CORRECTION
FILTER
622.08MHz
LIMITER
42dBBIAS
VCOΣ
CFILTRSSIINVVTHLOP
FIL+FIL-PHADJ+
DDI+
DDI-
INSEL
ADI-
ADI+
PHADJ-
1.23V
SDO+
SDO-
PECL
VCC
VCC
6kΩ
6kΩ
PECLPECL
SCLKO+
SCLKO-
OLC+OLC-
Figure 1. Functional Diagram
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
Phase Detector
The phase detector produces a voltage proportional to
the phase difference between the incoming data and
the internal clock. Because of its feedback nature, the
PLL drives the error voltage to zero, aligning the recov-
ered clock to the incoming data. The external phase
adjustment pins (PHADJ+, PHADJ-) allow the user to
vary the internal phase alignment.
Frequency Detector
The frequency detector incorporated into the PLL uses
the input data stream edges to sample the quadrature
components of the VCO clock. This generates a differ-
ence frequency that aids acquisition during startup.
Depending on the polarity of the difference frequency,
the PFD drives the VCO so that the difference frequen-
cy is reduced to zero. Once frequency acquisition is
obtained, the frequency detector returns to a neutral
state.
Loop Filter and VCO
The VCO is fully integrated, while the loop filter requires
an external capacitor (CF). This filter network determines
the bandwidth and peaking of the second-order PLL.
__________________Design Procedure
Received-Signal-Strength Indicator
The RSSI output voltage is insensitive to temperature
and supply fluctuations. The power detector functions
as a broadband power meter that detects the total RMS
power of all signals within the detector bandwidth
(including input signal noise). The RSSI voltage varies
linearly (in decibels) for inputs of 2mVP-Pto 50mVP-P.
The slope over this input range is approximately
26mV/dB.
The high-speed RSSI signal is filtered to an RMS level
with one external capacitor tied from CFILT to VCC. The
impedance looking into CFILT is about 500Ωto VCC. As
a result, the lower -3dB cutoff frequency is set by the
following simple relationship:
fFILT= 1/[2π(500)CFILT]
For 622Mbps applications, Maxim recommends a cut-
off frequency of 6.8kHz, which requires CFILT= 47nF.
The RSSI output is designed to drive a minimum load
resistance of 100kΩto ground and a maximum of
20pF. Loads greater than 20pF must be buffered by a
series resistance of 100kΩ(i.e., voltmeter).
Input Offset Correction
The on-chip limiting amplifier provides more than 42dB
of gain. A low-frequency feedback loop is integrated
into the MAX3676 to remove the input offset. DC-cou-
pling to the ADI+ and ADI- inputs is not allowed, as this
would prevent the proper functioning of the DC offset-
correction circuitry.
The differential input impedance (ZIN) is approximately
2.5kΩ. The impedance between OLC+ and OLC- (ZOLC)
is approximately 120kΩ. Take care when setting the
combined low-frequency cutoff (fCUTOFF), due to the
input DC-blocking capacitor (CIN) and the offset correc-
tion loop capacitor (COLC). See Table 1 for selecting the
values of CINand COLC.
These values ensure that the poles associated with CIN
and COLCwork together to provide a flat response at the
lower -3dB corner frequency (no gain peaking).
CINmust be a low-TC, high-quality capacitor of type X7R
or better in order to minimize fCUTOFFdeviations. COLC
must be a capacitor of type Z5U or better.
Loss-of-Power Monitor
An LOP monitor with a user-programmable threshold
and a hysteresis comparator is also included with the
limiting amplifier circuitry. Internally, one comparator
input is tied to the RSSI output signal, and the other is
tied to the threshold voltage (VTH), which is set exter-
nally and provides a trip point for the LOP indication. A
low-voltage, low-drift op amp, referenced to an internal
bandgap voltage (1.23V), is supplied for programming
a supply independent threshold voltage. This op amp
requires two external resistors to program the LOP trip
point. VTHis programmable from 1.23V to 2.6V using
the equation:
VTH= 1.23(1 + R2/R1)
The op amp can source only 100μA of current.
Therefore, an R1 value of 20kΩis recommended for
proper operation. The input bias current of the op amp
at the INV pin is less than ±100nA.
COLCCOMBINED LOW
fCUTOFF (kHz)
2200pF0.015μF29
1000pF0.01μF68
CIN
470pF3300pF135
330pF2200pF190
220pF1500pF290
Table 1. Setting the Low-Frequency Cutoff
4700pF0.033μF13.5
6800pF0.082μF10
0.010μF0.1μF6.8
0.022μF0.15μF3.0

Partno	Mfg	Dc	Qty	Available	Descript
MAX3676EHJ+	MAXIM	N/a	46	avai	622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
MAX3676EHJ+ \|MAX3676EHJ	MAX	N/a	630	avai	622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier