MAX3675ECJ ,622Mbps / Low-Power / 3.3V Clock-Recovery and Data-Retiming IC with Limiting AmplifierELECTRICAL CHARACTERISTICS(V = +3.0V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical ..
MAX3676EHJ+ ,622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting AmplifierELECTRICAL CHARACTERISTICS(V = +3.0V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical ..
MAX3676EHJ+ ,622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting AmplifierApplications+Denotes a lead(Pb)-free/RoHS-compliant package.SDH/SONET Receivers and RegeneratorsSDH ..
MAX3679CTJ+ , 3.3V, Low-Jitter Crystal to LVPECL Clock Generator
MAX367CWN ,Signal-Line Circuit ProtectorsGeneral Description ________
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MAX7314AEG+ ,18-Port GPIO with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionELECTRICAL CHARACTERISTICS(Typical Operating Circuit, V+ = 2V to 3.6V, T = T to T , unless otherwis ..
MAX7314ATG ,18-Port GPIO with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionApplications 3.3VLCD Backlights0.047µFLED Status IndicationV+ P0µCP1Relay DriversSDASDA MAX7314 P2S ..
MAX7314ATG+ ,18-Port GPIO with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionMAX731419-3170; Rev 4; 4/0518-Port GPIO with LED Intensity Control,Interrupt, and Hot-Insertion Pro ..
MAX7314ATG+T ,18-Port GPIO with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionApplications3.3VLCD Backlights 0.047μFLED Status IndicationV+ P0μCP1Relay DriversSDA SDA P2MAX7314S ..
MAX7314ATG+T ,18-Port GPIO with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionFeatures2The MAX7314 I C-compatible serial interfaced periph- ♦ 400kbps, 2-Wire Serial Interface, ..
MAX7315AEE+ ,8-Port I/O Expander with LED Intensity Control, Interrupt, and Hot-Insertion ProtectionFeatures2The MAX7315 I C-/SMBus-compatible serial interfaced♦ 400kbps, 2-Wire Serial Interface, 5 ..
MAX3675ECJ
622Mbps / Low-Power / 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
___________________________________________________Typical Operating Circuit
_____________________ General DescriptionThe MAX3675 is a complete clock-recovery and data-
retiming IC incorporating a limiting amplifier. It is
intended for 622Mbps SDH/SONET applications and
operates from a single +3.3V supply.
The MAX3675 has two differential input amplifiers: one
accepts PECL levels, while the other accepts small-sig-
nal analog levels. The analog inputs access the limiting
amplifier stage, which provides both a received-signal-
strength indicator (RSSI) and a programmable-threshold
loss-of-power (LOP) monitor. Selecting the PECL amplifier
disables the limiting amplifier, conserving power. A loss-
of-lock (LOL) monitor is also incorporated as part of the
fully integrated PLL.
________________________ApplicationsSDH/SONET Transmission Systems
SDH/SONET Access Nodes
Add/Drop Multiplexers
ATM Switches
Digital Cross-Connects
____________________________FeaturesSingle +3.3V or +5.0V Power SupplyComplies with ANSI, ITU, and Bellcore
SDH/SONET Specifications Low Power: 215mW at +3.3VSelectable Data Inputs, Differential PECL or
AnalogReceived-Signal-Strength Indicator (RSSI)Loss-of-Power and Loss-of-Lock MonitorsDifferential PECL Clock and Data OutputsNo External Reference Clock Required
MAX3675
622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
Pin Configuration appears at end of data sheet.*Contact factory for availability. Dice are designed to operate
from -40°C to +85°C, but are tested and guaranteed only at = +45°C.
MAX3675
622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +6.5V
Input Voltage Levels,
DDI+, DDI-, ADI+, ADI-...........................-0.5V to (VCC+ 0.5V)
Input Differential Voltage (ADI+) - (ADI-)...............................±3V
PECL Output Currents, SDO+, SDO-, SCLKO+, SCLKO-...100mALOL, LOP, INSEL, PHADJ+, PHADJ-.........-0.5V to (VCC+ 0.5V)
FIL+, FIL-, OLC+, OLC-, RSSI, VTH...........-0.5V to (VCC+ 0.5V)
(OLC+) - (OLC-).....................................................................±3V
(FIL+) - (FIL-)..................................................................±700mV
CFILT...............................................(VCC- 2.5V) to (VCC+ 0.5V)
INV.........................................................................-0.5V to +2.0V
Continuous Power Dissipation (TA= +85°C)
TQFP (derate 11.1mW/°C above +85°C).....................721mW
Operating Junction Temperature Range...........-40°C to +150°C
Storage Temperature Range.............................-65°C to +160°C
Processing Temperature (die).........................................+400°C
Lead Temperature (soldering, 10sec).............................+300°C
Note 1:Dice are tested at Tj= +45°C, VCC= +4.25V
Note 2:At TA= -40°C, DC characteristics are guaranteed by design and characterization.
MAX3675
622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V and TA= +25°C.)
(Notes 3, 4)
Note 3:AC parameters are guaranteed by design and characterization.
Note 4:The MAX3675 is characterized with a PRBS of 223- 1 maintaining a BER of ≤10-10having a confidence level of 99.9%.
Note 5:A lower minimum input voltage of 2mVp-p is achievable; however, the LOP hysteresis is not guaranteed below 3.6mVp-p.
Note 6:Hysteresis = 20log(VRELEASE / VASSERT)
Note 7:Small-signal bandwidth cannot be measured directly.
Note 8:RSSI slope = [VRSSI2- VRSSI1] / [20log (VID2/ VID1)]
Note 9:1UI = 1 unit interval = (622.08MHz)-1= 1.608ns
MAX3675
622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
__________________________________________Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
MAX3675
622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
____________________________Typical Operating Characteristics (continued)(TA = +25°C, unless otherwise noted.)
MAX3675
622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
______________________________________________________________Pin Description
MAX3675
622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
_______________Detailed DescriptionThe block diagram in Figure 1 shows the MAX3675’s
architecture. It consists of a limiting amplifier input
stage followed by a fully integrated clock/data-recovery
(CDR) block implemented with a phase-locked loop
(PLL). The input stage is selectable between a limiting
amplifier or a simple PECL input buffer. The limiting
amplifier provides a loss-of-power (LOP) monitor and a
received-signal-strength indicator (RSSI). The PLL con-
sists of a phase/frequency detector (PFD), a loop filter
amplifier, and a voltage-controlled oscillator (VCO).
Limiting AmplifierThe MAX3675’s on-chip limiting amplifier accepts an
input signal level from 3.0mVp-p to 1.2Vp-p. The ampli-
fier consists of a cascade of gain stages that include
full-wave logarithmic detectors. The combined small-
signal gain is approximately 42dB, and the -3dB band-
width is 800MHz. Input-referred noise is less than
100µVRMS, providing excellent sensitivity for small-
amplitude data streams.
In addition to driving the CDR, the limiting amplifier pro-
vides both an RSSI output and an LOP monitor that
allow the user to program the threshold voltage. The
RSSI circuitry provides an output voltage that is linearly
proportional to the input power (in decibels) detected
between the ADI+ and ADI- input pins and is sensitive
enough to reliably detect signals as small as 2mVp-p.
Input DC offset reduces the accuracy of the power
detector; therefore, an integrated feedback loop is
included that automatically nulls the input offset of the
gain stage. The addition of this offset-correction loop
requires that the input signal be AC coupled when
using the ADI+ and ADI- inputs.
Finally, for applications that do not require the limiting
amplifier, selecting the digital inputs conserves power
by turning off the post-amplifier block.
Figure 1. Functional Diagram
MAX3675
622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
Phase DetectorThe phase detector produces a voltage proportional to
the phase difference between the incoming data and
the internal clock. Because of its feedback nature, the
PLL drives the error voltage to zero, aligning the recov-
ered clock to the incoming data. The external phase
adjustment pins (PHADJ+, PHADJ-) allow the user to
vary the internal phase alignment.
Frequency DetectorA frequency detector incorporated into the PLL aids
frequency acquisition during start-up conditions. The
input data stream is sampled by quadrature compo-
nents of the VCO clock, generating a difference fre-
quency. Depending on the polarity of the difference
frequency, the PFD drives the VCO so that the differ-
ence frequency is reduced to zero. Once frequency
acquisition is obtained, the frequency detector returns
to a neutral state.
Loop Filter and VCOThe VCO is fully integrated, while the loop filter requires
an external R-C network. This filter network determines
the bandwidth and peaking of the second-order PLL.
__________________Design Procedure
Received-Signal-Strength
Indicator (RSSI)The RSSI output voltage is insensitive to temperature
and supply fluctuations. The power detector functions
as a broadband power meter that detects the total RMS
power of all signals within the detector bandwidth
(including input signal noise). The RSSI voltage varies
linearly (in decibels) for inputs of 2mVp-p to 50mVp-p.
The slope over this input range is approximately
29mV/dB.
The high-speed RSSI signal is filtered to an RMS level
with one external capacitor tied from CFILT to VCC. The
impedance looking into CFILT is about 500Ωto VCC. As
a result, the lower -3dB cutoff frequency is set by the
following simple relationship:
For 622Mbps applications, Maxim recommends a cut-
off frequency of 6.8kHz, which requires CF= 47nF. The
RSSI output is designed to drive a minimum load resis-
tance of 10kWto ground and a maximum of 20pF.
Loads greater than 20pF must be buffered by a series
resistance of 10kW(i.e., voltmeter).
Input Offset CorrectionThe on-chip limiting amplifier provides more than 42dB
of gain. A low-frequency feedback loop is integrated
into the MAX3675 to remove the input offset. DC cou-
pling to the ADI+ and ADI- inputs is not allowed, as this
would prevent the proper functioning of the DC offset-
correction circuitry.
The differential input impedance (ZIN) is approximately
2.5kW. The impedance between OLC+ and OLC- (ZOLC)
is approximately 120kW. Take care when setting the
combined low-frequency cutoff (fCUTOFF), due to the
input DC-blocking capacitor (CIN) and the offset correc-
tion loop capacitor (COLC). Refer to Table 1 for selecting
the values of CINand COLC.
These values ensure that the poles associated with CIN
and COLCwork together to provide a flat response at the
lower -3dB corner frequency (no gain peaking).
CINmust be a low-TC, high-quality capacitor of type X7R
or better in order to minimize fCUTOFFdeviations. COLC
must be a capacitor of type Z5U or better.
Loss-of-Power (LOP) MonitorA LOP monitor with a user-programmable threshold
and a hysteresis comparator is also included with the
limiting amplifier circuitry. Internally, one comparator
input is tied to the RSSI output signal, and the other is
tied to the threshold voltage (VTH), which is set exter-
nally and provides a trip point for the LOP indication. A
low-voltage, low-drift op amp, referenced to an internal
bandgap voltage (1.18V), is supplied for programming
a supply-independent threshold voltage. This op amp
requires two external resistors to program the LOP trip
point. VTHis programmable from 1.18V to 2.4V using
the equation:
The op amp can source only 20µA of current.
Therefore, an R1 value greater than or equal to 100kΩ
is recommended for proper operation. The input bias
