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MAX3670EGJ
Low-Jitter 155MHz/622MHz Clock Generator
General DescriptionThe MAX3670 is a low-jitter 155MHz/622MHz reference
clock generator IC designed for system clock distribution
and frequency synchronization in OC-48 and OC-192
SONET/SDH and WDM transmission systems. The
MAX3670 integrates a phase/frequency detector, an
operational amplifier (op amp), prescaler dividers and
input/output buffers. Using an external VCO, the
MAX3670 can be configured easily as a phase-lock loop
with bandwidth programmable from 15Hz to 20kHz.
The MAX3670 operates from a single +3.3V or +5.0V
supply, and dissipates 150mW (typ) at 3.3V. The operat-
ing temperature range is from -40°C to +85°C. The chip
is available in a 5mm ✕5mm, 32-pin QFN package.
ApplicationsOC-12 to OC-192 SONET/WDM Transport
Systems
Clock Jitter Clean-Up and Frequency
Synchronization
Frequency Conversion
System Clock Distribution
FeaturesSingle +3.3V or +5.0V SupplyPower Dissipation: 150mW at +3.3V SupplyExternal VCO Center Frequencies (fVCO): 155MHz
to 670MHzReference Clock Frequencies: fVCO, fVCO/2,
fVCO/8Main Clock Output Frequency: fVCOOptional Output Clock Frequencies: fVCO, fVCO/2,
fVCO/4, fVCO/8Low Intrinsic Jitter: <0.4psRMSLoss-of-Lock IndicatorPECL Clock Output Interface
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
Ordering Information
Typical Application Circuit19-2166; Rev 0; 9/01
Pin Configuration appears at end of data sheet.*Exposed pad
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.3V ±10% or VCC= +5.0V ±10%, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless other-
wise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage.........................................................-0.5V to +7V
Voltage at C2+, C2-, THADJ, CTH, GSEL1, GSEL2, GSEL3,
LOL, RSEL, REFCLK-, REFCLK+, VSEL, VCOIN+, VCOIN-,
VC, POLAR, PSEL1, PSEL2, COMP,
OPAMP+, OPAMP-..................................-0.5V to (VCC+ 0.5V)
PECL Output Current (MOUT+,
MOUT-, POUT+, POUT-).................................................56mA
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s).................................+300°C
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.3V ±10% or VCC= +5.0V ±10%, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless other-
wise noted.) (Note 1)
AC ELECTRICAL CHARACTERISTICS(VCC= +3.3V ±10% or VCC= +5.0V ±10%, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless other-
Note 2:Measured with PECL outputs unterminated.
Note 3:OPAMP specifications met with 10kΩload to ground or 5kΩload to VCC (POLAR = 0 and POLAR = VCC).
Note 4:PFD/CP currents are measured from pins OPAMP+ to OPAMP-. See Table 3 for gain settings.
Note 5:AC characteristics are guaranteed by design and characterization.
Note 6:Measured with 50% VCO input duty cycle.
Note 7:Random noise voltage at op amp output with 800kΩresistor connected between VC and OPAMP-, PFD/CP gain (KPD) =
5µA/UI, and POLAR = 0. Measured with the PLL open loop and no REFCLK or VCO input.
Note 8:Spurious noise voltage due to PFD/CP output pulses measured at op amp output with R1= 800kΩ, KPD= 5µA/UI, and
compare frequency 400 times greater than the higher-order pole frequency (see Design Procedure).
Note 9:PSR measured with a 100mVp-p sine wave on VCCin a frequency range from 100Hz to 2MHz. External resistors R1matched
to within 1%, external capacitors C1matched to within 10%. Measured closed loop with PLL bandwidth set to 200Hz.
Note 10:The PLL 3dB bandwidth is adjusted from 15Hz to 20kHz by changing external components R1and C1, by selecting the inter-
nal programmable divider ratio and phase-detector gain. Measured with VCO gain of 220ppm/V and C1limited to 2.2µF.
Note 11:Measured at BW = 20kHz. When input jitter frequency is above PLL transfer bandwidth (BW), the jitter transfer function rollsoff at -20dB/decade.
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
AC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.3V ±10% or VCC= +5.0V ±10%, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless other-
wise noted.) (Note 5)
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
SUPPLY CURRENT
vs. TEMPERATUREMAX3670 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX3670 toc02
TEMPERATURE (°C)
EDGE SPEED 20%-80% (ps)
EDGE SPEED
vs. TEMPERATURE-10100k10k1M10M
POWER-SUPPLY REJECTION
vs. FREQUENCYMAX3670 toc03
FREQUENCY (Hz)
SUPPLY REJECTION (dB)
200mV/
div
500ps/div
622MHz CLOCK OUTPUT
(DIFFERENTIAL OUTPUT)MAX3670 toc04
200mV/
div
2.0ns/div
155MHz CLOCK OUTPUT
(DIFFERENTIAL OUTPUT)MAX3670 toc05
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
Detailed DescriptionThe MAX3670 contains all the blocks needed to form a
PLL except for the VCO, which must be supplied sepa-
rately. The MAX3670 consists of input buffers for the ref-
erence clock and VCO, input and output clock-divider
circuitry, LOL detection circuitry, gain-control logic, a
phase-frequency detector and charge pump, an op
amp, and PECL output buffers.
This device is designed to clean up the noise on the
reference clock input and provide a low-jitter system
clock output.
Input Buffer for Reference
Clock and VCOThe MAX3670 contains differential inputs for the refer-
ence clock and the VCO. These inputs can be DC-cou-
pled and are internally biased with high impedance so
that they can be AC-coupled (Figure 1 in the Interface
Schematicsection). A single-ended VCO or reference
clock can also be applied.
Input and Output Clock-Divider CircuitryThe reference clock and VCO input buffers are followed
by a pair of clock dividers that prescale the input fre-
quency of the reference clock and VCO to 77.76MHz.
MAX3670
Low-Jitter 155MHz/622MHz
Clock Generator
Functional Diagram
