MAX3634ETM+-MAX3634ETM+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX3634ETM+T ,622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT ApplicationsApplications(ITU G.984) optical line terminal (OLT) receiver applica-tions. The MAX3634 provides cl ..
MAX3640UCM ,3.3V, 622Mbps LVDS, Dual 4:2 Crosspoint SwitchELECTRICAL CHARACTERISTICS(V = +3.0V to 3.6V, LVDS differential load = 100Ω ±1%, T = 0°C to +85°C. ..
MAX3640UCM ,3.3V, 622Mbps LVDS, Dual 4:2 Crosspoint SwitchApplications Ordering InformationSONET/SDH BackplanesPART TEMP. RANGE PIN-PACKAGEMAX3640UCM 0°C to ..
MAX3640UCM+ ,3.3V, 622Mbps LVDS, Dual 4:2 Crosspoint SwitchFeaturesThe MAX3640 is a dual-path crosspoint switch for use Single +3.3V Supplyat OC-12 data rate ..
MAX3643ETG+T ,155Mbps to 2.5Gbps Burst-Mode Laser DriverApplicationsPin Configuration appears at end of data sheet.A/B/G/XGPON ONT Modules Up to 2.5Gbps1.2 ..
MAX3645EEE ,+2.97 to +5.5 V, 125 Mbps to 200 Mbps limiting amplifier with loss-of-signal detectorApplicationsSONET 155Mbps TransceiversTOP VIEWFast Ethernet ReceiversCAZ21 16 THFDDI 125Mbps Receiv ..
MAX727ECK ,5V/3.3V/3V 2A Step-Down / PWM / Switch-Mode DC-DC RegulatorsELECTRICAL CHARACTERISTICS(V = 25V, T = T to T , unless otherwise noted.)IN j MIN MAXPARAMETER COND ..
MAX728ECK ,5V/3.3V/3V 2A Step-Down / PWM / Switch-Mode DC-DC RegulatorsFeatures' Input Range: Up to 40VThe MAX727/MAX728/MAX729 are monolithic, bipolar,pulse-width modula ..
MAX729CCK ,5V/3.3V/3V 2A Step-Down / PWM / Switch-Mode DC-DC RegulatorsApplicationsMAX727ECK -40°C to +85°C 5 TO-220Distributed Power from High-Voltage BusesMAX728CCK 0°C ..
MAX730 ,5V / Step-Down / Current-Mode PWM DC-DC ConvertersFeaturesThe MAX730A/MAX738A/MAX744A are 5V-output' 750mA Load Currents (MAX738A/MAX744A)CMOS, step- ..
MAX7300AAX+ ,2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O ExpanderMAX7300 2-Wire-Interfaced, 2.5V to 5.5V,20-Port or 28-Port I/O Expander
MAX7300ATL , 2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port I/O Expander

MAX3634ETM+-MAX3634ETM+T
622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications
General Description
The MAX3634 burst-mode clock phase aligner (CPA) is
designed specifically for 622Mbps or 1244Mbps GPON
(ITU G.984) optical line terminal (OLT) receiver applica-
tions. The MAX3634 provides clock and clock-aligned
resynchronized upstream data through differential
LVPECL outputs. Using the OLT system clock as a ref-
erence, the MAX3634 aligns to the input data and
acquires within the first 13 bits of the burst. The CPA
operates with received data that is frequency locked to
the OLT reference. The acquisition time, bit-error ratio,
and jitter tolerance all support GPON PMD specifica-
tions. LVPECL high-speed clock and data outputs pro-
vide compatibility with FPGAs at 622Mbps and with the
MAX3885 deserializer at 1244Mbps.
The MAX3634 is available in a low-profile, 7mm x 7mm,
48-lead TQFN package. The MAX3634 operates from a
single +3.3V supply, over the -40°C to +85°C tempera-
ture range.
Applications
622Mbps GPON OLT Receivers
1244Mbps GPON OLT Receivers
FeaturesDC-Coupled Clock Phase Aligner for Burst-Mode
GPON Applications13-Bit Burst Acquisition Time0.85UI High-Frequency Jitter ToleranceContinuous Clock OutputByte Rate (1/8th Data Rate) Reference Clock InputLock Detect OutputLVPECL Serial Data Input and OutputLVPECL Reset Input
MAX3634
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
Ordering Information
19-3818; Rev 0; 9/05
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-
PACKAGE
PKG
CODE
MAX3634ETM-40°C to +85°C48 TQFN
(7mm x 7mm)T4877-6
MAX3634
MAX3738
BURST-MODE
TIA/LA
MAX3656
BURST-MODE
LASER DRIVER
MAX3864
MAX3748A
TIA/LA
MAX3872
SONET
CDR
MAX3892
DATA
SERIALIZER
DATA
CLOCK
OLT CLOCK
DATA
BURST RESET
RATESEL
DIVIDE BY 16
DIVIDE BY 8
CONTINUOUS
LASER DRIVER
GPON OPTICAL LINE TERMINATIONGPON OPTICAL NETWORK TERMINATION
DATA
DATA
BURST ENABLE
CLOCK
CLOCK
UPSTREAM
1244Mbps
DOWNSTREAM
2488Mbps
BURST-MODE
CLOCK PHASE
ALIGNER
Typical ApplicationCircuit
Pin Configuration appears at end of data sheet.
MAX3634
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, VCCI, VCCO, VCCV........................................-0.5V to +4.0V
SDI±, RST±, REFCLK±,
RATESEL, FILT, TEST.............................-0.5V to (VCC+ 0.5V)
LVPECL Output Current (SDO±, SCLK±, LOCK±).............50mA
Continuous Power Dissipation (TA= +85°C)
48-Lead TQFN package
(derate 27.8mW/°C above +85°C).............................1800mW
Storage Temperature Range.............................-55°C to +150°C
Operating Ambient Temperature Range.............-40°C to +85°C
Lead Temperature (soldering, 10s).................................+400°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Supply CurrentICCNot including LVPECL output current315390mA
RATESEL = low1244.16Data RateRATESEL = high622.08Mbps
RATESEL = low155.52Reference Clock Input FrequencyRATESEL = high77.76MHz
SDI, RST, REFCLK Differential
InputVIN2001600mVP-P
SDI±, RST±, REFCLK± Input
Current-180+180µA
Rate = 1244Mbps200RST Input Rise/Fall Timestr, tfRate = 622Mbps200ps
SDI±, RST±, REFCLK± Common-
Mode Input
VCC
- 1.49
VCC
- VIN/4V
TA = 0°C to +85°C (Note 1)VCC
- 1.81
VCC
- 1.62SDO±, SCLK±, LOCK± Output
Voltage LowVOL
TA = -40°C to 0°C (Note 1)VCC
- 1.83
VCC
- 1.555
TA = 0°C to +85°C (Note 1)VCC
- 1.025
VCC
- 0.88SDO±, SCLK±, LOCK± Output
Voltage HighVOH
TA = -40°C to 0°C (Note 1)VCC
- 1.085
VCC
- 0.88
622Mbps (Notes 2, 5, 6)0.730.83Jitter Tolerance1244Mbps (Notes 2, 5, 6)0.730.81UIP-P
Acquisition Time(Notes 2, 3)13Bits
Bit-Error RatioAfter acquisition (Notes 2, 4)10-10
SDO±, LOCK± Transition Timetr, tf20% to 80% (Note 1)265ps
SCLK± Transition Timetr, tf20% to 80% (Note 1)200ps
MAX3634
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
622Mbps (Notes 1, 2)500Serial Data Output Clock-to-Q
Delay (Figure 1)tCLK-Q1244Mbps (Notes 1, 2)250ps
622Mbps (Notes 1, 2)500Serial Data Output Q-to-Clock
Delay (Figure 1)tQ-CLK1244Mbps (Notes 1, 2)250ps
RATESEL Input HighVIH2V
RATESEL Input LowVIL0.8V
RATESEL Input CurrentVIN = 0V or VCC-100+100µA
Note 1:PECL output must have external termination of 50Ωto VCC- 2V (Thevenin equivalent).
Note 2:AC parameters are guaranteed by design and characterization.
Note 3:From start of PON burst, 101010101010 preamble sequence.
Note 4:BER, acquisition time requirements are met with 100mVP-Psinusoidal noise on VCC, 0 < fNOISE≤10MHz.
Note5:Measured with 20psRMSinput random jitter (1.244Mbps), 30psRMS(622Mbps)
Note6:Jitter tolerance refers to the variation in phase between REFCLK and SDI after acquisition.
Typical Operating Characteristics
(VCC= +3.3V and TA= +25°C, unless otherwise noted)
1.244Gbps
INPUT AND OUTPUT EYE DIAGRAMS
MAX3634 toc01
200ps/div
SDI
SDO
622Mbps
INPUT AND OUTPUT EYE DIAGRAMS
MAX3634 toc02
400ps/div
SDI
SDO
BURST CAPTURE AT 1.244Gbps
MAX3634 toc03
1ns/div
RST
SDI
SDO
LOCK
(SCLK+) - (SCLK-)
(SDO+) - (SDO-)
tCLK-QtQ-CLK
Figure 1. Definition of Clock-to-Q and Q-to-Clock Delay
MAX3634
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
PINNAMEFUNCTION
1, 2, 12, 25, 36, 37, 48GNDSupply Ground
3, 6, 7, 10VCCI+3.3V Supply for Input BuffersSDI+Positive Serial Data Input, LVPECLSDI-Negative Serial Data Input, LVPECLRST+Positive Reset Input, LVPECL. Reset (= RST+ - RST-) is falling edge triggered.RST-Negative Reset Input, LVPECL
11, 38, 39, 44, 47VCC+3.3V Supply for Digital Circuitry
13–20, 22, 23TESTProduction Test Pins, Reserved. Leave open for normal operation.
21, 24, 26, 29, 32, 35VCCO+3.3V Supply for Output BuffersLOCK-Negative Lock Status Output, LVPECLLOCK+Positive Lock Status Output, LVPECL. Lock (= (LOCK+) - (LOCK-)) high indicates that the
MAX3634 has acquired the correct phase.SDO-Negative Serial Data Output, LVPECLSDO+Positive Serial Data Output, LVPECLSCLK-Negative Serial Clock Output, LVPECLSCLK+Positive Serial Clock Output, LVPECLRATESELRate Select Input, TTL. High selects 622.08Mbps operation.
41, 43VCCV+3.3V Supply for VCOFILTPLL Filter Capacitor. Connect a 0.1µF X7R capacitor from pin 42 to VCCV.REFCLK-Negative Reference Clock Input, LVPECL (1/8th data rate)REFCLK+Positive Reference Clock Input, LVPECLExposed PadThe exposed pad must be connected to the ground plane for proper thermal performance.
Pin Description
Typical Operating Characteristics (continued)
(VCC= +3.3V and TA= +25°C, unless otherwise noted)
JITTER TOLERANCE vs. SDI-TO-REFCLK
PHASE (1.244Gbps)
MAX3634 toc04
SDI-TO-REFCLK PHASE (ps)
JITTER TOLERANCE (UI
P-P
LIMITED BY TEST EQUIPMENT
JITTER TOLERANCE vs. SDI-TO-REFCLK
PHASE (622Mbps)
MAX3634 toc05
SDI-TO-REFCLK PHASE (ps)
JITTER TOLERANCE (UI
P-P
LIMITED BY TEST EQUIPMENT
SUPPLY CURRENT
vs. TEMPERATURE
MAX3634 toc06
AMBIENT TEMPERATURE (°C)
SUPPLY CURRENT (mA)0
EXCLUDES PECL OUTPUT CURRENT
General Description
Theory of Operation
The MAX3634 CPA provides serial clock and data out-
puts for GPON upstream bursts.
The burst-mode CPA operates on the principle that the
recovered clock from the ONT CDR is used at each
ONT to clock upstream data bursts out of the ONT con-
troller. The burst-mode CPA has logic that determines
the correct phase relationship between the upstream
data and the OLT reference clock at the beginning of
each ONT’s burst, and resamples the upstream data at
each bit using that clock.
The burst-mode CPA contains a phase-locked loop
(PLL) that synchronizes its oscillator to the reference
clock input. This oscillator drives a phase splitter, which
generates eight evenly spaced phases of the serial
clock, which are used to sample the input data at 1/8th
bit intervals in eight flip-flops. Combinatorial and
sequential logic measures the preamble, and based on
the phase of the preamble, determines which one of
the eight clock phases is at the center of the input data
bits. The data from the flip-flop associated with this
phase is then steered through a multiplexer to the CPA
output, which requires four or five additional clock peri-
ods until valid data is output. The CPA serial output
clock is continuous, without any phase jumps or dis-
continuities from burst to burst.
The burst-mode CPA requires a preamble sequence of
1010101010101 (13 bits) for correct phase alignment.
Typically, output begins after the 12th bit, although for
certain data/phase relationships, 13 bits are required.
An LVPECL-compatible lock status output is provided,
which indicates when the correct phase has been
acquired and valid serial output data is available. This
output remains low until reset by the burst reset input
(RST). The output data is disabled (held low) during the
period between reset and lock.
Reference Clock Input
The MAX3634 includes a PLL, which multiplies the ref-
erence clock by eight for use in the retiming circuitry.
For correct operation, the REFCLK input must be con-
nected to the OLT byte-rate reference clock, which
must be equal to 1/8th the serial data rate, and must
have a 40% to 60% duty cycle. This must be the same
clock source used to time the downstream data, and
the upstream data must be frequency locked to this
source.
The RATESEL input is used to configure 622Mbps or
1244Mbps operation; when RATESEL is high, the
MAX3634 operates at 622Mbps.
MAX3634
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
MAX3634LVPECL
REFCLK+
REFCLK-
LVPECL
LVPECL
LVPECL
SDI+
SDI-
TTLRATESEL
622Mbps/1244Mbps
PLL/PHASE SPLITTER
MUX
SYNCHRONIZER
PHASE-ACQUISITION LOGIC
RST+
RST-
SDO+
SDO-
LVPECL
SCLK+
SCLK-
LVPECL
LOCK+
LOCK-
BURST-MODE CPAφ0φ7
Figure 2. Functional Block Diagram
MAX3634
Input Stage
The LVPECL serial data input, SDI±, and burst-mode
reset input, RST±, provide 200mVP-P sensitivity. The
RST±input rise and fall times (20% to 80%) must not
exceed 200ps. LVPECL inputs must be DC-coupled with
external termination for correct operation with burst data
(see Maxim Application Note HFAN 1.0for termination
configuration).
Lock Detect
After the first 12 or 13 bits of the preamble, plus 4 or 5
bits of synchronizer delay, LOCK asserts to indicate the
beginning of valid data output.
Applications Information
GPON Burst-Mode Timing
Internally, the MAX3634 requires five internal clock
cycles (8x REFCLK) to initialize itself after receiving the
rest (BRST) signal. It then uses the next 8 bits of pream-
ble (10101010) to measure the phase relationship
between the reference clock and upstream data (after
the internal logic has been reset), and 3 to 5 bits later
begins outputting data. The time interval from BRST to
the end of the preamble must be no less than 18 bits
long. If the 8 bits of preamble that it uses to measure
phase have been excessive pulse-width distortion, the
phase measurement is in error.
The active edge of the reset input (BRST) must arrive at
the MAX3634 after the TIA has finished its level recovery,
but no sooner than 18 bits prior to the end of the (repeat-
ing 10 pattern) preamble, in order to provide adequate
time for the MAX3634 to initialize, measure the phase,
and load the output pipelines. This timing is shown in
Figure 3.
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
DATA INPUT
TO MAX3634
RESET
TDSR: BURST-TO-BURST SEPARATION TIME
TLR: TIA/LA LEVEL RECOVERY TIME
TCR: CPA RESET AND ACQUISITION TIME, ≥ 19 BITS
TDSR
DATA VALIDGUARD TIMETIA/LA ACQUISITIONCPA RESET
(5 BITS)
CPA ACQUISITION
(12 OR 13 BITS)
OUTPUT DATA
VALID
TLRTCR
Figure 3. Clock Phase Aligner Operation Timing Diagram

Partno	Mfg	Dc	Qty	Available	Descript
MAX3634ETM+	MAXIM	N/a	7	avai	622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications
MAX3634ETM+T	MAXIM	N/a	36	avai	622Mbps/1244Mbps Burst-Mode Clock Phase Aligner for GPON OLT Applications